194a4c329SAtsushi Nemoto /* 294a4c329SAtsushi Nemoto * TX4938/4937 setup routines 394a4c329SAtsushi Nemoto * Based on linux/arch/mips/txx9/rbtx4938/setup.c, 494a4c329SAtsushi Nemoto * and RBTX49xx patch from CELF patch archive. 594a4c329SAtsushi Nemoto * 694a4c329SAtsushi Nemoto * 2003-2005 (c) MontaVista Software, Inc. 794a4c329SAtsushi Nemoto * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 894a4c329SAtsushi Nemoto * 994a4c329SAtsushi Nemoto * This file is subject to the terms and conditions of the GNU General Public 1094a4c329SAtsushi Nemoto * License. See the file "COPYING" in the main directory of this archive 1194a4c329SAtsushi Nemoto * for more details. 1294a4c329SAtsushi Nemoto */ 1394a4c329SAtsushi Nemoto #include <linux/init.h> 1494a4c329SAtsushi Nemoto #include <linux/ioport.h> 1594a4c329SAtsushi Nemoto #include <linux/delay.h> 1694a4c329SAtsushi Nemoto #include <linux/param.h> 17*51f607c7SAtsushi Nemoto #include <linux/mtd/physmap.h> 1894a4c329SAtsushi Nemoto #include <asm/txx9irq.h> 1994a4c329SAtsushi Nemoto #include <asm/txx9tmr.h> 2094a4c329SAtsushi Nemoto #include <asm/txx9pio.h> 2194a4c329SAtsushi Nemoto #include <asm/txx9/generic.h> 2294a4c329SAtsushi Nemoto #include <asm/txx9/tx4938.h> 2394a4c329SAtsushi Nemoto 2468314725SAtsushi Nemoto static void __init tx4938_wdr_init(void) 2594a4c329SAtsushi Nemoto { 2694a4c329SAtsushi Nemoto /* clear WatchDogReset (W1C) */ 2794a4c329SAtsushi Nemoto tx4938_ccfg_set(TX4938_CCFG_WDRST); 2894a4c329SAtsushi Nemoto /* do reset on watchdog */ 2994a4c329SAtsushi Nemoto tx4938_ccfg_set(TX4938_CCFG_WR); 3094a4c329SAtsushi Nemoto } 3194a4c329SAtsushi Nemoto 3268314725SAtsushi Nemoto void __init tx4938_wdt_init(void) 3368314725SAtsushi Nemoto { 3468314725SAtsushi Nemoto txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL); 3568314725SAtsushi Nemoto } 3668314725SAtsushi Nemoto 3794a4c329SAtsushi Nemoto static struct resource tx4938_sdram_resource[4]; 3894a4c329SAtsushi Nemoto static struct resource tx4938_sram_resource; 3994a4c329SAtsushi Nemoto 4094a4c329SAtsushi Nemoto #define TX4938_SRAM_SIZE 0x800 4194a4c329SAtsushi Nemoto 4294a4c329SAtsushi Nemoto void __init tx4938_setup(void) 4394a4c329SAtsushi Nemoto { 4494a4c329SAtsushi Nemoto int i; 4594a4c329SAtsushi Nemoto __u32 divmode; 4694a4c329SAtsushi Nemoto int cpuclk = 0; 4794a4c329SAtsushi Nemoto u64 ccfg; 4894a4c329SAtsushi Nemoto 4994a4c329SAtsushi Nemoto txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE, 5094a4c329SAtsushi Nemoto TX4938_REG_SIZE); 51d10e025fSAtsushi Nemoto set_c0_config(TX49_CONF_CWFON); 5294a4c329SAtsushi Nemoto 5394a4c329SAtsushi Nemoto /* SDRAMC,EBUSC are configured by PROM */ 5494a4c329SAtsushi Nemoto for (i = 0; i < 8; i++) { 5594a4c329SAtsushi Nemoto if (!(TX4938_EBUSC_CR(i) & 0x8)) 5694a4c329SAtsushi Nemoto continue; /* disabled */ 5794a4c329SAtsushi Nemoto txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i); 5894a4c329SAtsushi Nemoto txx9_ce_res[i].end = 5994a4c329SAtsushi Nemoto txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1; 6094a4c329SAtsushi Nemoto request_resource(&iomem_resource, &txx9_ce_res[i]); 6194a4c329SAtsushi Nemoto } 6294a4c329SAtsushi Nemoto 6394a4c329SAtsushi Nemoto /* clocks */ 6494a4c329SAtsushi Nemoto ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg); 6594a4c329SAtsushi Nemoto if (txx9_master_clock) { 6694a4c329SAtsushi Nemoto /* calculate gbus_clock and cpu_clock from master_clock */ 6794a4c329SAtsushi Nemoto divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK; 6894a4c329SAtsushi Nemoto switch (divmode) { 6994a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_8: 7094a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_10: 7194a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_12: 7294a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_16: 7394a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_18: 7494a4c329SAtsushi Nemoto txx9_gbus_clock = txx9_master_clock * 4; break; 7594a4c329SAtsushi Nemoto default: 7694a4c329SAtsushi Nemoto txx9_gbus_clock = txx9_master_clock; 7794a4c329SAtsushi Nemoto } 7894a4c329SAtsushi Nemoto switch (divmode) { 7994a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_2: 8094a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_8: 8194a4c329SAtsushi Nemoto cpuclk = txx9_gbus_clock * 2; break; 8294a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_2_5: 8394a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_10: 8494a4c329SAtsushi Nemoto cpuclk = txx9_gbus_clock * 5 / 2; break; 8594a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_3: 8694a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_12: 8794a4c329SAtsushi Nemoto cpuclk = txx9_gbus_clock * 3; break; 8894a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_4: 8994a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_16: 9094a4c329SAtsushi Nemoto cpuclk = txx9_gbus_clock * 4; break; 9194a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_4_5: 9294a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_18: 9394a4c329SAtsushi Nemoto cpuclk = txx9_gbus_clock * 9 / 2; break; 9494a4c329SAtsushi Nemoto } 9594a4c329SAtsushi Nemoto txx9_cpu_clock = cpuclk; 9694a4c329SAtsushi Nemoto } else { 9794a4c329SAtsushi Nemoto if (txx9_cpu_clock == 0) 9894a4c329SAtsushi Nemoto txx9_cpu_clock = 300000000; /* 300MHz */ 9994a4c329SAtsushi Nemoto /* calculate gbus_clock and master_clock from cpu_clock */ 10094a4c329SAtsushi Nemoto cpuclk = txx9_cpu_clock; 10194a4c329SAtsushi Nemoto divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK; 10294a4c329SAtsushi Nemoto switch (divmode) { 10394a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_2: 10494a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_8: 10594a4c329SAtsushi Nemoto txx9_gbus_clock = cpuclk / 2; break; 10694a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_2_5: 10794a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_10: 10894a4c329SAtsushi Nemoto txx9_gbus_clock = cpuclk * 2 / 5; break; 10994a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_3: 11094a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_12: 11194a4c329SAtsushi Nemoto txx9_gbus_clock = cpuclk / 3; break; 11294a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_4: 11394a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_16: 11494a4c329SAtsushi Nemoto txx9_gbus_clock = cpuclk / 4; break; 11594a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_4_5: 11694a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_18: 11794a4c329SAtsushi Nemoto txx9_gbus_clock = cpuclk * 2 / 9; break; 11894a4c329SAtsushi Nemoto } 11994a4c329SAtsushi Nemoto switch (divmode) { 12094a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_8: 12194a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_10: 12294a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_12: 12394a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_16: 12494a4c329SAtsushi Nemoto case TX4938_CCFG_DIVMODE_18: 12594a4c329SAtsushi Nemoto txx9_master_clock = txx9_gbus_clock / 4; break; 12694a4c329SAtsushi Nemoto default: 12794a4c329SAtsushi Nemoto txx9_master_clock = txx9_gbus_clock; 12894a4c329SAtsushi Nemoto } 12994a4c329SAtsushi Nemoto } 13094a4c329SAtsushi Nemoto /* change default value to udelay/mdelay take reasonable time */ 13194a4c329SAtsushi Nemoto loops_per_jiffy = txx9_cpu_clock / HZ / 2; 13294a4c329SAtsushi Nemoto 13394a4c329SAtsushi Nemoto /* CCFG */ 13494a4c329SAtsushi Nemoto tx4938_wdr_init(); 13594a4c329SAtsushi Nemoto /* clear BusErrorOnWrite flag (W1C) */ 13694a4c329SAtsushi Nemoto tx4938_ccfg_set(TX4938_CCFG_BEOW); 13794a4c329SAtsushi Nemoto /* enable Timeout BusError */ 13894a4c329SAtsushi Nemoto if (txx9_ccfg_toeon) 13994a4c329SAtsushi Nemoto tx4938_ccfg_set(TX4938_CCFG_TOE); 14094a4c329SAtsushi Nemoto 14194a4c329SAtsushi Nemoto /* DMA selection */ 14294a4c329SAtsushi Nemoto txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL); 14394a4c329SAtsushi Nemoto 14494a4c329SAtsushi Nemoto /* Use external clock for external arbiter */ 14594a4c329SAtsushi Nemoto if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB)) 14694a4c329SAtsushi Nemoto txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL); 14794a4c329SAtsushi Nemoto 14894a4c329SAtsushi Nemoto printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n", 14994a4c329SAtsushi Nemoto txx9_pcode_str, 15094a4c329SAtsushi Nemoto (cpuclk + 500000) / 1000000, 15194a4c329SAtsushi Nemoto (txx9_master_clock + 500000) / 1000000, 15294a4c329SAtsushi Nemoto (__u32)____raw_readq(&tx4938_ccfgptr->crir), 15394a4c329SAtsushi Nemoto (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg), 15494a4c329SAtsushi Nemoto (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg)); 15594a4c329SAtsushi Nemoto 15694a4c329SAtsushi Nemoto printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str); 15794a4c329SAtsushi Nemoto for (i = 0; i < 4; i++) { 15894a4c329SAtsushi Nemoto __u64 cr = TX4938_SDRAMC_CR(i); 15994a4c329SAtsushi Nemoto unsigned long base, size; 16094a4c329SAtsushi Nemoto if (!((__u32)cr & 0x00000400)) 16194a4c329SAtsushi Nemoto continue; /* disabled */ 16294a4c329SAtsushi Nemoto base = (unsigned long)(cr >> 49) << 21; 16394a4c329SAtsushi Nemoto size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21; 16494a4c329SAtsushi Nemoto printk(" CR%d:%016llx", i, (unsigned long long)cr); 16594a4c329SAtsushi Nemoto tx4938_sdram_resource[i].name = "SDRAM"; 16694a4c329SAtsushi Nemoto tx4938_sdram_resource[i].start = base; 16794a4c329SAtsushi Nemoto tx4938_sdram_resource[i].end = base + size - 1; 16894a4c329SAtsushi Nemoto tx4938_sdram_resource[i].flags = IORESOURCE_MEM; 16994a4c329SAtsushi Nemoto request_resource(&iomem_resource, &tx4938_sdram_resource[i]); 17094a4c329SAtsushi Nemoto } 17194a4c329SAtsushi Nemoto printk(" TR:%09llx\n", 17294a4c329SAtsushi Nemoto (unsigned long long)____raw_readq(&tx4938_sdramcptr->tr)); 17394a4c329SAtsushi Nemoto 17494a4c329SAtsushi Nemoto /* SRAM */ 17594a4c329SAtsushi Nemoto if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) { 17694a4c329SAtsushi Nemoto unsigned int size = TX4938_SRAM_SIZE; 17794a4c329SAtsushi Nemoto tx4938_sram_resource.name = "SRAM"; 17894a4c329SAtsushi Nemoto tx4938_sram_resource.start = 17994a4c329SAtsushi Nemoto (____raw_readq(&tx4938_sramcptr->cr) >> (39-11)) 18094a4c329SAtsushi Nemoto & ~(size - 1); 18194a4c329SAtsushi Nemoto tx4938_sram_resource.end = 18294a4c329SAtsushi Nemoto tx4938_sram_resource.start + TX4938_SRAM_SIZE - 1; 18394a4c329SAtsushi Nemoto tx4938_sram_resource.flags = IORESOURCE_MEM; 18494a4c329SAtsushi Nemoto request_resource(&iomem_resource, &tx4938_sram_resource); 18594a4c329SAtsushi Nemoto } 18694a4c329SAtsushi Nemoto 18794a4c329SAtsushi Nemoto /* TMR */ 18894a4c329SAtsushi Nemoto /* disable all timers */ 18994a4c329SAtsushi Nemoto for (i = 0; i < TX4938_NR_TMR; i++) 19094a4c329SAtsushi Nemoto txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL); 19194a4c329SAtsushi Nemoto 19294a4c329SAtsushi Nemoto /* DMA */ 19394a4c329SAtsushi Nemoto for (i = 0; i < 2; i++) 19494a4c329SAtsushi Nemoto ____raw_writeq(TX4938_DMA_MCR_MSTEN, 19594a4c329SAtsushi Nemoto (void __iomem *)(TX4938_DMA_REG(i) + 0x50)); 19694a4c329SAtsushi Nemoto 19794a4c329SAtsushi Nemoto /* PIO */ 19894a4c329SAtsushi Nemoto txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO); 19994a4c329SAtsushi Nemoto __raw_writel(0, &tx4938_pioptr->maskcpu); 20094a4c329SAtsushi Nemoto __raw_writel(0, &tx4938_pioptr->maskext); 20194a4c329SAtsushi Nemoto 20294a4c329SAtsushi Nemoto if (txx9_pcode == 0x4938) { 20394a4c329SAtsushi Nemoto __u64 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); 20494a4c329SAtsushi Nemoto /* set PCIC1 reset */ 20594a4c329SAtsushi Nemoto txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST); 20694a4c329SAtsushi Nemoto if (pcfg & (TX4938_PCFG_ETH0_SEL | TX4938_PCFG_ETH1_SEL)) { 20794a4c329SAtsushi Nemoto mdelay(1); /* at least 128 cpu clock */ 20894a4c329SAtsushi Nemoto /* clear PCIC1 reset */ 20994a4c329SAtsushi Nemoto txx9_clear64(&tx4938_ccfgptr->clkctr, 21094a4c329SAtsushi Nemoto TX4938_CLKCTR_PCIC1RST); 21194a4c329SAtsushi Nemoto } else { 21294a4c329SAtsushi Nemoto printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str); 21394a4c329SAtsushi Nemoto /* stop PCIC1 */ 21494a4c329SAtsushi Nemoto txx9_set64(&tx4938_ccfgptr->clkctr, 21594a4c329SAtsushi Nemoto TX4938_CLKCTR_PCIC1CKD); 21694a4c329SAtsushi Nemoto } 21794a4c329SAtsushi Nemoto if (!(pcfg & TX4938_PCFG_ETH0_SEL)) { 21894a4c329SAtsushi Nemoto printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str); 21994a4c329SAtsushi Nemoto txx9_set64(&tx4938_ccfgptr->clkctr, 22094a4c329SAtsushi Nemoto TX4938_CLKCTR_ETH0RST); 22194a4c329SAtsushi Nemoto txx9_set64(&tx4938_ccfgptr->clkctr, 22294a4c329SAtsushi Nemoto TX4938_CLKCTR_ETH0CKD); 22394a4c329SAtsushi Nemoto } 22494a4c329SAtsushi Nemoto if (!(pcfg & TX4938_PCFG_ETH1_SEL)) { 22594a4c329SAtsushi Nemoto printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str); 22694a4c329SAtsushi Nemoto txx9_set64(&tx4938_ccfgptr->clkctr, 22794a4c329SAtsushi Nemoto TX4938_CLKCTR_ETH1RST); 22894a4c329SAtsushi Nemoto txx9_set64(&tx4938_ccfgptr->clkctr, 22994a4c329SAtsushi Nemoto TX4938_CLKCTR_ETH1CKD); 23094a4c329SAtsushi Nemoto } 23194a4c329SAtsushi Nemoto } 23294a4c329SAtsushi Nemoto } 23394a4c329SAtsushi Nemoto 23494a4c329SAtsushi Nemoto void __init tx4938_time_init(unsigned int tmrnr) 23594a4c329SAtsushi Nemoto { 23694a4c329SAtsushi Nemoto if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS) 23794a4c329SAtsushi Nemoto txx9_clockevent_init(TX4938_TMR_REG(tmrnr) & 0xfffffffffULL, 23894a4c329SAtsushi Nemoto TXX9_IRQ_BASE + TX4938_IR_TMR(tmrnr), 23994a4c329SAtsushi Nemoto TXX9_IMCLK); 24094a4c329SAtsushi Nemoto } 24194a4c329SAtsushi Nemoto 2427779a5e0SAtsushi Nemoto void __init tx4938_sio_init(unsigned int sclk, unsigned int cts_mask) 24394a4c329SAtsushi Nemoto { 24494a4c329SAtsushi Nemoto int i; 24594a4c329SAtsushi Nemoto unsigned int ch_mask = 0; 24694a4c329SAtsushi Nemoto 24794a4c329SAtsushi Nemoto if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL) 24894a4c329SAtsushi Nemoto ch_mask |= 1 << 1; /* disable SIO1 by PCFG setting */ 24994a4c329SAtsushi Nemoto for (i = 0; i < 2; i++) { 25094a4c329SAtsushi Nemoto if ((1 << i) & ch_mask) 25194a4c329SAtsushi Nemoto continue; 2527779a5e0SAtsushi Nemoto txx9_sio_init(TX4938_SIO_REG(i) & 0xfffffffffULL, 2537779a5e0SAtsushi Nemoto TXX9_IRQ_BASE + TX4938_IR_SIO(i), 2547779a5e0SAtsushi Nemoto i, sclk, (1 << i) & cts_mask); 25594a4c329SAtsushi Nemoto } 25694a4c329SAtsushi Nemoto } 257c49f91f5SAtsushi Nemoto 258c49f91f5SAtsushi Nemoto void __init tx4938_spi_init(int busid) 259c49f91f5SAtsushi Nemoto { 260c49f91f5SAtsushi Nemoto txx9_spi_init(busid, TX4938_SPI_REG & 0xfffffffffULL, 261c49f91f5SAtsushi Nemoto TXX9_IRQ_BASE + TX4938_IR_SPI); 262c49f91f5SAtsushi Nemoto } 263c49f91f5SAtsushi Nemoto 264c49f91f5SAtsushi Nemoto void __init tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1) 265c49f91f5SAtsushi Nemoto { 266c49f91f5SAtsushi Nemoto u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg); 267c49f91f5SAtsushi Nemoto 268c49f91f5SAtsushi Nemoto if (addr0 && (pcfg & TX4938_PCFG_ETH0_SEL)) 269c49f91f5SAtsushi Nemoto txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH0, addr0); 270c49f91f5SAtsushi Nemoto if (addr1 && (pcfg & TX4938_PCFG_ETH1_SEL)) 271c49f91f5SAtsushi Nemoto txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH1, addr1); 272c49f91f5SAtsushi Nemoto } 273*51f607c7SAtsushi Nemoto 274*51f607c7SAtsushi Nemoto void __init tx4938_mtd_init(int ch) 275*51f607c7SAtsushi Nemoto { 276*51f607c7SAtsushi Nemoto struct physmap_flash_data pdata = { 277*51f607c7SAtsushi Nemoto .width = TX4938_EBUSC_WIDTH(ch) / 8, 278*51f607c7SAtsushi Nemoto }; 279*51f607c7SAtsushi Nemoto unsigned long start = txx9_ce_res[ch].start; 280*51f607c7SAtsushi Nemoto unsigned long size = txx9_ce_res[ch].end - start + 1; 281*51f607c7SAtsushi Nemoto 282*51f607c7SAtsushi Nemoto if (!(TX4938_EBUSC_CR(ch) & 0x8)) 283*51f607c7SAtsushi Nemoto return; /* disabled */ 284*51f607c7SAtsushi Nemoto txx9_physmap_flash_init(ch, start, size, &pdata); 285*51f607c7SAtsushi Nemoto } 286