1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1992 Linus Torvalds 7 * Copyright (C) 1994 - 2000 Ralf Baechle 8 */ 9 #include <linux/delay.h> 10 #include <linux/init.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/kernel.h> 14 #include <linux/spinlock.h> 15 16 #include <asm/i8259.h> 17 #include <asm/io.h> 18 #include <asm/sni.h> 19 20 DEFINE_SPINLOCK(pciasic_lock); 21 22 extern asmlinkage void sni_rm200_pci_handle_int(void); 23 24 static void enable_pciasic_irq(unsigned int irq) 25 { 26 unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2); 27 unsigned long flags; 28 29 spin_lock_irqsave(&pciasic_lock, flags); 30 *(volatile u8 *) PCIMT_IRQSEL |= mask; 31 spin_unlock_irqrestore(&pciasic_lock, flags); 32 } 33 34 static unsigned int startup_pciasic_irq(unsigned int irq) 35 { 36 enable_pciasic_irq(irq); 37 return 0; /* never anything pending */ 38 } 39 40 #define shutdown_pciasic_irq disable_pciasic_irq 41 42 void disable_pciasic_irq(unsigned int irq) 43 { 44 unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2)); 45 unsigned long flags; 46 47 spin_lock_irqsave(&pciasic_lock, flags); 48 *(volatile u8 *) PCIMT_IRQSEL &= mask; 49 spin_unlock_irqrestore(&pciasic_lock, flags); 50 } 51 52 #define mask_and_ack_pciasic_irq disable_pciasic_irq 53 54 static void end_pciasic_irq(unsigned int irq) 55 { 56 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 57 enable_pciasic_irq(irq); 58 } 59 60 static struct hw_interrupt_type pciasic_irq_type = { 61 .typename = "ASIC-PCI", 62 .startup = startup_pciasic_irq, 63 .shutdown = shutdown_pciasic_irq, 64 .enable = enable_pciasic_irq, 65 .disable = disable_pciasic_irq, 66 .ack = mask_and_ack_pciasic_irq, 67 .end = end_pciasic_irq, 68 }; 69 70 /* 71 * hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug 72 * button interrupts. Later ... 73 */ 74 void pciasic_hwint0(struct pt_regs *regs) 75 { 76 panic("Received int0 but no handler yet ..."); 77 } 78 79 /* This interrupt was used for the com1 console on the first prototypes. */ 80 void pciasic_hwint2(struct pt_regs *regs) 81 { 82 /* I think this shouldn't happen on production machines. */ 83 panic("hwint2 and no handler yet"); 84 } 85 86 /* hwint5 is the r4k count / compare interrupt */ 87 void pciasic_hwint5(struct pt_regs *regs) 88 { 89 panic("hwint5 and no handler yet"); 90 } 91 92 static unsigned int ls1bit8(unsigned int x) 93 { 94 int b = 7, s; 95 96 s = 4; if ((x & 0x0f) == 0) s = 0; b -= s; x <<= s; 97 s = 2; if ((x & 0x30) == 0) s = 0; b -= s; x <<= s; 98 s = 1; if ((x & 0x40) == 0) s = 0; b -= s; 99 100 return b; 101 } 102 103 /* 104 * hwint 1 deals with EISA and SCSI interrupts, 105 * 106 * The EISA_INT bit in CSITPEND is high active, all others are low active. 107 */ 108 void pciasic_hwint1(struct pt_regs *regs) 109 { 110 u8 pend = *(volatile char *)PCIMT_CSITPEND; 111 unsigned long flags; 112 113 if (pend & IT_EISA) { 114 int irq; 115 /* 116 * Note: ASIC PCI's builtin interrupt achknowledge feature is 117 * broken. Using it may result in loss of some or all i8259 118 * interupts, so don't use PCIMT_INT_ACKNOWLEDGE ... 119 */ 120 irq = i8259_irq(); 121 if (unlikely(irq < 0)) 122 return; 123 124 do_IRQ(irq, regs); 125 } 126 127 if (!(pend & IT_SCSI)) { 128 flags = read_c0_status(); 129 clear_c0_status(ST0_IM); 130 do_IRQ(PCIMT_IRQ_SCSI, regs); 131 write_c0_status(flags); 132 } 133 } 134 135 /* 136 * hwint 3 should deal with the PCI A - D interrupts, 137 */ 138 void pciasic_hwint3(struct pt_regs *regs) 139 { 140 u8 pend = *(volatile char *)PCIMT_CSITPEND; 141 int irq; 142 143 pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD); 144 clear_c0_status(IE_IRQ3); 145 irq = PCIMT_IRQ_INT2 + ls1bit8(pend); 146 do_IRQ(irq, regs); 147 set_c0_status(IE_IRQ3); 148 } 149 150 /* 151 * hwint 4 is used for only the onboard PCnet 32. 152 */ 153 void pciasic_hwint4(struct pt_regs *regs) 154 { 155 clear_c0_status(IE_IRQ4); 156 do_IRQ(PCIMT_IRQ_ETHERNET, regs); 157 set_c0_status(IE_IRQ4); 158 } 159 160 void __init init_pciasic(void) 161 { 162 unsigned long flags; 163 164 spin_lock_irqsave(&pciasic_lock, flags); 165 * (volatile u8 *) PCIMT_IRQSEL = 166 IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD; 167 spin_unlock_irqrestore(&pciasic_lock, flags); 168 } 169 170 /* 171 * On systems with i8259-style interrupt controllers we assume for 172 * driver compatibility reasons interrupts 0 - 15 to be the i8295 173 * interrupts even if the hardware uses a different interrupt numbering. 174 */ 175 void __init arch_init_irq(void) 176 { 177 int i; 178 179 set_except_vector(0, sni_rm200_pci_handle_int); 180 181 init_i8259_irqs(); /* Integrated i8259 */ 182 init_pciasic(); 183 184 /* Actually we've got more interrupts to handle ... */ 185 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) { 186 irq_desc[i].status = IRQ_DISABLED; 187 irq_desc[i].action = 0; 188 irq_desc[i].depth = 1; 189 irq_desc[i].handler = &pciasic_irq_type; 190 } 191 192 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4); 193 } 194