1 /* 2 * Copyright (C) 2000, 2001 Broadcom Corporation 3 * 4 * Copyright (C) 2002 MontaVista Software Inc. 5 * Author: jsun@mvista.com or jsun@junsun.net 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 */ 13 #include <linux/bcd.h> 14 #include <linux/types.h> 15 #include <linux/time.h> 16 17 #include <asm/time.h> 18 #include <asm/addrspace.h> 19 #include <asm/io.h> 20 21 #include <asm/sibyte/sb1250.h> 22 #include <asm/sibyte/sb1250_regs.h> 23 #include <asm/sibyte/sb1250_smbus.h> 24 25 26 /* M41T81 definitions */ 27 28 /* 29 * Register bits 30 */ 31 32 #define M41T81REG_SC_ST 0x80 /* stop bit */ 33 #define M41T81REG_HR_CB 0x40 /* century bit */ 34 #define M41T81REG_HR_CEB 0x80 /* century enable bit */ 35 #define M41T81REG_CTL_S 0x20 /* sign bit */ 36 #define M41T81REG_CTL_FT 0x40 /* frequency test bit */ 37 #define M41T81REG_CTL_OUT 0x80 /* output level */ 38 #define M41T81REG_WD_RB0 0x01 /* watchdog resolution bit 0 */ 39 #define M41T81REG_WD_RB1 0x02 /* watchdog resolution bit 1 */ 40 #define M41T81REG_WD_BMB0 0x04 /* watchdog multiplier bit 0 */ 41 #define M41T81REG_WD_BMB1 0x08 /* watchdog multiplier bit 1 */ 42 #define M41T81REG_WD_BMB2 0x10 /* watchdog multiplier bit 2 */ 43 #define M41T81REG_WD_BMB3 0x20 /* watchdog multiplier bit 3 */ 44 #define M41T81REG_WD_BMB4 0x40 /* watchdog multiplier bit 4 */ 45 #define M41T81REG_AMO_ABE 0x20 /* alarm in "battery back-up mode" enable bit */ 46 #define M41T81REG_AMO_SQWE 0x40 /* square wave enable */ 47 #define M41T81REG_AMO_AFE 0x80 /* alarm flag enable flag */ 48 #define M41T81REG_ADT_RPT5 0x40 /* alarm repeat mode bit 5 */ 49 #define M41T81REG_ADT_RPT4 0x80 /* alarm repeat mode bit 4 */ 50 #define M41T81REG_AHR_RPT3 0x80 /* alarm repeat mode bit 3 */ 51 #define M41T81REG_AHR_HT 0x40 /* halt update bit */ 52 #define M41T81REG_AMN_RPT2 0x80 /* alarm repeat mode bit 2 */ 53 #define M41T81REG_ASC_RPT1 0x80 /* alarm repeat mode bit 1 */ 54 #define M41T81REG_FLG_AF 0x40 /* alarm flag (read only) */ 55 #define M41T81REG_FLG_WDF 0x80 /* watchdog flag (read only) */ 56 #define M41T81REG_SQW_RS0 0x10 /* sqw frequency bit 0 */ 57 #define M41T81REG_SQW_RS1 0x20 /* sqw frequency bit 1 */ 58 #define M41T81REG_SQW_RS2 0x40 /* sqw frequency bit 2 */ 59 #define M41T81REG_SQW_RS3 0x80 /* sqw frequency bit 3 */ 60 61 62 /* 63 * Register numbers 64 */ 65 66 #define M41T81REG_TSC 0x00 /* tenths/hundredths of second */ 67 #define M41T81REG_SC 0x01 /* seconds */ 68 #define M41T81REG_MN 0x02 /* minute */ 69 #define M41T81REG_HR 0x03 /* hour/century */ 70 #define M41T81REG_DY 0x04 /* day of week */ 71 #define M41T81REG_DT 0x05 /* date of month */ 72 #define M41T81REG_MO 0x06 /* month */ 73 #define M41T81REG_YR 0x07 /* year */ 74 #define M41T81REG_CTL 0x08 /* control */ 75 #define M41T81REG_WD 0x09 /* watchdog */ 76 #define M41T81REG_AMO 0x0A /* alarm: month */ 77 #define M41T81REG_ADT 0x0B /* alarm: date */ 78 #define M41T81REG_AHR 0x0C /* alarm: hour */ 79 #define M41T81REG_AMN 0x0D /* alarm: minute */ 80 #define M41T81REG_ASC 0x0E /* alarm: second */ 81 #define M41T81REG_FLG 0x0F /* flags */ 82 #define M41T81REG_SQW 0x13 /* square wave register */ 83 84 #define M41T81_CCR_ADDRESS 0x68 85 #define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg)))) 86 87 static int m41t81_read(uint8_t addr) 88 { 89 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 90 ; 91 92 bus_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); 93 bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE), 94 SMB_CSR(R_SMB_START)); 95 96 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 97 ; 98 99 bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), 100 SMB_CSR(R_SMB_START)); 101 102 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 103 ; 104 105 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { 106 /* Clear error bit by writing a 1 */ 107 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 108 return -1; 109 } 110 111 return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); 112 } 113 114 static int m41t81_write(uint8_t addr, int b) 115 { 116 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 117 ; 118 119 bus_writeq((addr & 0xFF), SMB_CSR(R_SMB_CMD)); 120 bus_writeq((b & 0xff), SMB_CSR(R_SMB_DATA)); 121 bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, 122 SMB_CSR(R_SMB_START)); 123 124 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 125 ; 126 127 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { 128 /* Clear error bit by writing a 1 */ 129 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 130 return -1; 131 } 132 133 /* read the same byte again to make sure it is written */ 134 bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, 135 SMB_CSR(R_SMB_START)); 136 137 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 138 ; 139 140 return 0; 141 } 142 143 int m41t81_set_time(unsigned long t) 144 { 145 struct rtc_time tm; 146 147 to_tm(t, &tm); 148 149 /* 150 * Note the write order matters as it ensures the correctness. 151 * When we write sec, 10th sec is clear. It is reasonable to 152 * believe we should finish writing min within a second. 153 */ 154 155 tm.tm_sec = BIN2BCD(tm.tm_sec); 156 m41t81_write(M41T81REG_SC, tm.tm_sec); 157 158 tm.tm_min = BIN2BCD(tm.tm_min); 159 m41t81_write(M41T81REG_MN, tm.tm_min); 160 161 tm.tm_hour = BIN2BCD(tm.tm_hour); 162 tm.tm_hour = (tm.tm_hour & 0x3f) | (m41t81_read(M41T81REG_HR) & 0xc0); 163 m41t81_write(M41T81REG_HR, tm.tm_hour); 164 165 /* tm_wday starts from 0 to 6 */ 166 if (tm.tm_wday == 0) tm.tm_wday = 7; 167 tm.tm_wday = BIN2BCD(tm.tm_wday); 168 m41t81_write(M41T81REG_DY, tm.tm_wday); 169 170 tm.tm_mday = BIN2BCD(tm.tm_mday); 171 m41t81_write(M41T81REG_DT, tm.tm_mday); 172 173 /* tm_mon starts from 0, *ick* */ 174 tm.tm_mon ++; 175 tm.tm_mon = BIN2BCD(tm.tm_mon); 176 m41t81_write(M41T81REG_MO, tm.tm_mon); 177 178 /* we don't do century, everything is beyond 2000 */ 179 tm.tm_year %= 100; 180 tm.tm_year = BIN2BCD(tm.tm_year); 181 m41t81_write(M41T81REG_YR, tm.tm_year); 182 183 return 0; 184 } 185 186 unsigned long m41t81_get_time(void) 187 { 188 unsigned int year, mon, day, hour, min, sec; 189 190 /* 191 * min is valid if two reads of sec are the same. 192 */ 193 for (;;) { 194 sec = m41t81_read(M41T81REG_SC); 195 min = m41t81_read(M41T81REG_MN); 196 if (sec == m41t81_read(M41T81REG_SC)) break; 197 } 198 hour = m41t81_read(M41T81REG_HR) & 0x3f; 199 day = m41t81_read(M41T81REG_DT); 200 mon = m41t81_read(M41T81REG_MO); 201 year = m41t81_read(M41T81REG_YR); 202 203 sec = BCD2BIN(sec); 204 min = BCD2BIN(min); 205 hour = BCD2BIN(hour); 206 day = BCD2BIN(day); 207 mon = BCD2BIN(mon); 208 year = BCD2BIN(year); 209 210 year += 2000; 211 212 return mktime(year, mon, day, hour, min, sec); 213 } 214 215 int m41t81_probe(void) 216 { 217 unsigned int tmp; 218 219 /* enable chip if it is not enabled yet */ 220 tmp = m41t81_read(M41T81REG_SC); 221 m41t81_write(M41T81REG_SC, tmp & 0x7f); 222 223 return (m41t81_read(M41T81REG_SC) != -1); 224 } 225