1 /* 2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. 3 * All rights reserved. 4 * Authors: Carsten Langgaard <carstenl@mips.com> 5 * Maciej W. Rozycki <macro@mips.com> 6 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) 7 * 8 * This program is free software; you can distribute it and/or modify it 9 * under the terms of the GNU General Public License (Version 2) as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 20 * 21 * MIPS boards specific PCI support. 22 * 23 */ 24 #include <linux/config.h> 25 #include <linux/types.h> 26 #include <linux/pci.h> 27 #include <linux/kernel.h> 28 #include <linux/init.h> 29 30 #include <asm/mips-boards/msc01_pci.h> 31 32 #define PCI_ACCESS_READ 0 33 #define PCI_ACCESS_WRITE 1 34 35 /* 36 * PCI configuration cycle AD bus definition 37 */ 38 /* Type 0 */ 39 #define PCI_CFG_TYPE0_REG_SHF 0 40 #define PCI_CFG_TYPE0_FUNC_SHF 8 41 42 /* Type 1 */ 43 #define PCI_CFG_TYPE1_REG_SHF 0 44 #define PCI_CFG_TYPE1_FUNC_SHF 8 45 #define PCI_CFG_TYPE1_DEV_SHF 11 46 #define PCI_CFG_TYPE1_BUS_SHF 16 47 48 static int msc_pcibios_config_access(unsigned char access_type, 49 struct pci_bus *bus, unsigned int devfn, int where, u32 * data) 50 { 51 unsigned char busnum = bus->number; 52 unsigned char type; 53 u32 intr; 54 55 #ifdef CONFIG_MIPS_BOARDS_GEN 56 if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) { 57 /* MIPS Core boards have SOCit connected as device 17 */ 58 return -1; 59 } 60 #endif 61 62 /* Clear status register bits. */ 63 MSC_WRITE(MSC01_PCI_INTSTAT, 64 (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)); 65 66 /* Setup address */ 67 if (busnum == 0) 68 type = 0; /* Type 0 */ 69 else 70 type = 1; /* Type 1 */ 71 72 MSC_WRITE(MSC01_PCI_CFGADDR, 73 ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) | 74 (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) 75 | (PCI_FUNC(devfn) << 76 MSC01_PCI_CFGADDR_FNUM_SHF) | ((where / 77 4) << 78 MSC01_PCI_CFGADDR_RNUM_SHF) 79 | (type))); 80 81 /* Perform access */ 82 if (access_type == PCI_ACCESS_WRITE) 83 MSC_WRITE(MSC01_PCI_CFGDATA, *data); 84 else 85 MSC_READ(MSC01_PCI_CFGDATA, *data); 86 87 /* Detect Master/Target abort */ 88 MSC_READ(MSC01_PCI_INTSTAT, intr); 89 if (intr & (MSC01_PCI_INTCFG_MA_BIT | 90 MSC01_PCI_INTCFG_TA_BIT)) { 91 /* Error occurred */ 92 93 /* Clear bits */ 94 MSC_READ(MSC01_PCI_INTSTAT, intr); 95 MSC_WRITE(MSC01_PCI_INTSTAT, 96 (MSC01_PCI_INTCFG_MA_BIT | 97 MSC01_PCI_INTCFG_TA_BIT)); 98 99 return -1; 100 } 101 102 return 0; 103 } 104 105 106 /* 107 * We can't address 8 and 16 bit words directly. Instead we have to 108 * read/write a 32bit word and mask/modify the data we actually want. 109 */ 110 static int msc_pcibios_read(struct pci_bus *bus, unsigned int devfn, 111 int where, int size, u32 * val) 112 { 113 u32 data = 0; 114 115 if ((size == 2) && (where & 1)) 116 return PCIBIOS_BAD_REGISTER_NUMBER; 117 else if ((size == 4) && (where & 3)) 118 return PCIBIOS_BAD_REGISTER_NUMBER; 119 120 if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, 121 &data)) 122 return -1; 123 124 if (size == 1) 125 *val = (data >> ((where & 3) << 3)) & 0xff; 126 else if (size == 2) 127 *val = (data >> ((where & 3) << 3)) & 0xffff; 128 else 129 *val = data; 130 131 return PCIBIOS_SUCCESSFUL; 132 } 133 134 static int msc_pcibios_write(struct pci_bus *bus, unsigned int devfn, 135 int where, int size, u32 val) 136 { 137 u32 data = 0; 138 139 if ((size == 2) && (where & 1)) 140 return PCIBIOS_BAD_REGISTER_NUMBER; 141 else if ((size == 4) && (where & 3)) 142 return PCIBIOS_BAD_REGISTER_NUMBER; 143 144 if (size == 4) 145 data = val; 146 else { 147 if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, 148 where, &data)) 149 return -1; 150 151 if (size == 1) 152 data = (data & ~(0xff << ((where & 3) << 3))) | 153 (val << ((where & 3) << 3)); 154 else if (size == 2) 155 data = (data & ~(0xffff << ((where & 3) << 3))) | 156 (val << ((where & 3) << 3)); 157 } 158 159 if (msc_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where, 160 &data)) 161 return -1; 162 163 return PCIBIOS_SUCCESSFUL; 164 } 165 166 struct pci_ops msc_pci_ops = { 167 .read = msc_pcibios_read, 168 .write = msc_pcibios_write 169 }; 170