1a6a4834cSSteven J. Hill /* 2a6a4834cSSteven J. Hill * This file is subject to the terms and conditions of the GNU General Public 3a6a4834cSSteven J. Hill * License. See the file "COPYING" in the main directory of this archive 4a6a4834cSSteven J. Hill * for more details. 5a6a4834cSSteven J. Hill * 6a6a4834cSSteven J. Hill * A small micro-assembler. It is intentionally kept simple, does only 7a6a4834cSSteven J. Hill * support a subset of instructions, and does not try to hide pipeline 8a6a4834cSSteven J. Hill * effects like branch delay slots. 9a6a4834cSSteven J. Hill * 10a6a4834cSSteven J. Hill * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 11a6a4834cSSteven J. Hill * Copyright (C) 2005, 2007 Maciej W. Rozycki 12a6a4834cSSteven J. Hill * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 13a6a4834cSSteven J. Hill * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. 14a6a4834cSSteven J. Hill */ 15a6a4834cSSteven J. Hill 16a6a4834cSSteven J. Hill #include <linux/kernel.h> 17a6a4834cSSteven J. Hill #include <linux/types.h> 18a6a4834cSSteven J. Hill #include <linux/init.h> 19a6a4834cSSteven J. Hill 20a6a4834cSSteven J. Hill #include <asm/inst.h> 21a6a4834cSSteven J. Hill #include <asm/elf.h> 22a6a4834cSSteven J. Hill #include <asm/bugs.h> 23a6a4834cSSteven J. Hill #define UASM_ISA _UASM_ISA_MICROMIPS 24a6a4834cSSteven J. Hill #include <asm/uasm.h> 25a6a4834cSSteven J. Hill 26a6a4834cSSteven J. Hill #define RS_MASK 0x1f 27a6a4834cSSteven J. Hill #define RS_SH 16 28a6a4834cSSteven J. Hill #define RT_MASK 0x1f 29a6a4834cSSteven J. Hill #define RT_SH 21 30a6a4834cSSteven J. Hill #define SCIMM_MASK 0x3ff 31a6a4834cSSteven J. Hill #define SCIMM_SH 16 32a6a4834cSSteven J. Hill 33a6a4834cSSteven J. Hill /* This macro sets the non-variable bits of an instruction. */ 34a6a4834cSSteven J. Hill #define M(a, b, c, d, e, f) \ 35a6a4834cSSteven J. Hill ((a) << OP_SH \ 36a6a4834cSSteven J. Hill | (b) << RT_SH \ 37a6a4834cSSteven J. Hill | (c) << RS_SH \ 38a6a4834cSSteven J. Hill | (d) << RD_SH \ 39a6a4834cSSteven J. Hill | (e) << RE_SH \ 40a6a4834cSSteven J. Hill | (f) << FUNC_SH) 41a6a4834cSSteven J. Hill 42a6a4834cSSteven J. Hill /* Define these when we are not the ISA the kernel is being compiled with. */ 43a6a4834cSSteven J. Hill #ifndef CONFIG_CPU_MICROMIPS 44a6a4834cSSteven J. Hill #define MM_uasm_i_b(buf, off) ISAOPC(_beq)(buf, 0, 0, off) 45a6a4834cSSteven J. Hill #define MM_uasm_i_beqz(buf, rs, off) ISAOPC(_beq)(buf, rs, 0, off) 46a6a4834cSSteven J. Hill #define MM_uasm_i_beqzl(buf, rs, off) ISAOPC(_beql)(buf, rs, 0, off) 47a6a4834cSSteven J. Hill #define MM_uasm_i_bnez(buf, rs, off) ISAOPC(_bne)(buf, rs, 0, off) 48a6a4834cSSteven J. Hill #endif 49a6a4834cSSteven J. Hill 50a6a4834cSSteven J. Hill #include "uasm.c" 51a6a4834cSSteven J. Hill 52a6a4834cSSteven J. Hill static struct insn insn_table_MM[] __uasminitdata = { 53a6a4834cSSteven J. Hill { insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD }, 54a6a4834cSSteven J. Hill { insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, 55a6a4834cSSteven J. Hill { insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD }, 56a6a4834cSSteven J. Hill { insn_andi, M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, 57a6a4834cSSteven J. Hill { insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 58a6a4834cSSteven J. Hill { insn_beql, 0, 0 }, 59a6a4834cSSteven J. Hill { insn_bgez, M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM }, 60a6a4834cSSteven J. Hill { insn_bgezl, 0, 0 }, 61a6a4834cSSteven J. Hill { insn_bltz, M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM }, 62a6a4834cSSteven J. Hill { insn_bltzl, 0, 0 }, 63a6a4834cSSteven J. Hill { insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM }, 64a6a4834cSSteven J. Hill { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM }, 65a6a4834cSSteven J. Hill { insn_daddu, 0, 0 }, 66a6a4834cSSteven J. Hill { insn_daddiu, 0, 0 }, 67a6a4834cSSteven J. Hill { insn_dmfc0, 0, 0 }, 68a6a4834cSSteven J. Hill { insn_dmtc0, 0, 0 }, 69a6a4834cSSteven J. Hill { insn_dsll, 0, 0 }, 70a6a4834cSSteven J. Hill { insn_dsll32, 0, 0 }, 71a6a4834cSSteven J. Hill { insn_dsra, 0, 0 }, 72a6a4834cSSteven J. Hill { insn_dsrl, 0, 0 }, 73a6a4834cSSteven J. Hill { insn_dsrl32, 0, 0 }, 74a6a4834cSSteven J. Hill { insn_drotr, 0, 0 }, 75a6a4834cSSteven J. Hill { insn_drotr32, 0, 0 }, 76a6a4834cSSteven J. Hill { insn_dsubu, 0, 0 }, 77a6a4834cSSteven J. Hill { insn_eret, M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0 }, 78a6a4834cSSteven J. Hill { insn_ins, M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE }, 79a6a4834cSSteven J. Hill { insn_ext, M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE }, 80a6a4834cSSteven J. Hill { insn_j, M(mm_j32_op, 0, 0, 0, 0, 0), JIMM }, 81a6a4834cSSteven J. Hill { insn_jal, M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM }, 82a6a4834cSSteven J. Hill { insn_jr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS }, 83a6a4834cSSteven J. Hill { insn_ld, 0, 0 }, 84a6a4834cSSteven J. Hill { insn_ll, M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM }, 85a6a4834cSSteven J. Hill { insn_lld, 0, 0 }, 86a6a4834cSSteven J. Hill { insn_lui, M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM }, 87a6a4834cSSteven J. Hill { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, 88a6a4834cSSteven J. Hill { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD }, 89a6a4834cSSteven J. Hill { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD }, 90a6a4834cSSteven J. Hill { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD }, 91a6a4834cSSteven J. Hill { insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, 92a6a4834cSSteven J. Hill { insn_pref, M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM }, 93a6a4834cSSteven J. Hill { insn_rfe, 0, 0 }, 94a6a4834cSSteven J. Hill { insn_sc, M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM }, 95a6a4834cSSteven J. Hill { insn_scd, 0, 0 }, 96a6a4834cSSteven J. Hill { insn_sd, 0, 0 }, 97a6a4834cSSteven J. Hill { insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD }, 98a6a4834cSSteven J. Hill { insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD }, 99a6a4834cSSteven J. Hill { insn_srl, M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD }, 100a6a4834cSSteven J. Hill { insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD }, 101a6a4834cSSteven J. Hill { insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD }, 102a6a4834cSSteven J. Hill { insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, 103a6a4834cSSteven J. Hill { insn_tlbp, M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0 }, 104a6a4834cSSteven J. Hill { insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 }, 105a6a4834cSSteven J. Hill { insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 }, 106a6a4834cSSteven J. Hill { insn_tlbwr, M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0 }, 107a6a4834cSSteven J. Hill { insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD }, 108a6a4834cSSteven J. Hill { insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, 109a6a4834cSSteven J. Hill { insn_dins, 0, 0 }, 110a6a4834cSSteven J. Hill { insn_dinsm, 0, 0 }, 111a6a4834cSSteven J. Hill { insn_syscall, M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM}, 112a6a4834cSSteven J. Hill { insn_bbit0, 0, 0 }, 113a6a4834cSSteven J. Hill { insn_bbit1, 0, 0 }, 114a6a4834cSSteven J. Hill { insn_lwx, 0, 0 }, 115a6a4834cSSteven J. Hill { insn_ldx, 0, 0 }, 116a6a4834cSSteven J. Hill { insn_invalid, 0, 0 } 117a6a4834cSSteven J. Hill }; 118a6a4834cSSteven J. Hill 119a6a4834cSSteven J. Hill #undef M 120a6a4834cSSteven J. Hill 121a6a4834cSSteven J. Hill static inline __uasminit u32 build_bimm(s32 arg) 122a6a4834cSSteven J. Hill { 123a6a4834cSSteven J. Hill WARN(arg > 0xffff || arg < -0x10000, 124a6a4834cSSteven J. Hill KERN_WARNING "Micro-assembler field overflow\n"); 125a6a4834cSSteven J. Hill 126a6a4834cSSteven J. Hill WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n"); 127a6a4834cSSteven J. Hill 128a6a4834cSSteven J. Hill return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 1) & 0x7fff); 129a6a4834cSSteven J. Hill } 130a6a4834cSSteven J. Hill 131a6a4834cSSteven J. Hill static inline __uasminit u32 build_jimm(u32 arg) 132a6a4834cSSteven J. Hill { 133*8fe4bb98SSteven J. Hill 134*8fe4bb98SSteven J. Hill WARN(arg & ~((JIMM_MASK << 2) | 1), 135a6a4834cSSteven J. Hill KERN_WARNING "Micro-assembler field overflow\n"); 136a6a4834cSSteven J. Hill 137a6a4834cSSteven J. Hill return (arg >> 1) & JIMM_MASK; 138a6a4834cSSteven J. Hill } 139a6a4834cSSteven J. Hill 140a6a4834cSSteven J. Hill /* 141a6a4834cSSteven J. Hill * The order of opcode arguments is implicitly left to right, 142a6a4834cSSteven J. Hill * starting with RS and ending with FUNC or IMM. 143a6a4834cSSteven J. Hill */ 144a6a4834cSSteven J. Hill static void __uasminit build_insn(u32 **buf, enum opcode opc, ...) 145a6a4834cSSteven J. Hill { 146a6a4834cSSteven J. Hill struct insn *ip = NULL; 147a6a4834cSSteven J. Hill unsigned int i; 148a6a4834cSSteven J. Hill va_list ap; 149a6a4834cSSteven J. Hill u32 op; 150a6a4834cSSteven J. Hill 151a6a4834cSSteven J. Hill for (i = 0; insn_table_MM[i].opcode != insn_invalid; i++) 152a6a4834cSSteven J. Hill if (insn_table_MM[i].opcode == opc) { 153a6a4834cSSteven J. Hill ip = &insn_table_MM[i]; 154a6a4834cSSteven J. Hill break; 155a6a4834cSSteven J. Hill } 156a6a4834cSSteven J. Hill 157a6a4834cSSteven J. Hill if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) 158a6a4834cSSteven J. Hill panic("Unsupported Micro-assembler instruction %d", opc); 159a6a4834cSSteven J. Hill 160a6a4834cSSteven J. Hill op = ip->match; 161a6a4834cSSteven J. Hill va_start(ap, opc); 162a6a4834cSSteven J. Hill if (ip->fields & RS) { 163a6a4834cSSteven J. Hill if (opc == insn_mfc0 || opc == insn_mtc0) 164a6a4834cSSteven J. Hill op |= build_rt(va_arg(ap, u32)); 165a6a4834cSSteven J. Hill else 166a6a4834cSSteven J. Hill op |= build_rs(va_arg(ap, u32)); 167a6a4834cSSteven J. Hill } 168a6a4834cSSteven J. Hill if (ip->fields & RT) { 169a6a4834cSSteven J. Hill if (opc == insn_mfc0 || opc == insn_mtc0) 170a6a4834cSSteven J. Hill op |= build_rs(va_arg(ap, u32)); 171a6a4834cSSteven J. Hill else 172a6a4834cSSteven J. Hill op |= build_rt(va_arg(ap, u32)); 173a6a4834cSSteven J. Hill } 174a6a4834cSSteven J. Hill if (ip->fields & RD) 175a6a4834cSSteven J. Hill op |= build_rd(va_arg(ap, u32)); 176a6a4834cSSteven J. Hill if (ip->fields & RE) 177a6a4834cSSteven J. Hill op |= build_re(va_arg(ap, u32)); 178a6a4834cSSteven J. Hill if (ip->fields & SIMM) 179a6a4834cSSteven J. Hill op |= build_simm(va_arg(ap, s32)); 180a6a4834cSSteven J. Hill if (ip->fields & UIMM) 181a6a4834cSSteven J. Hill op |= build_uimm(va_arg(ap, u32)); 182a6a4834cSSteven J. Hill if (ip->fields & BIMM) 183a6a4834cSSteven J. Hill op |= build_bimm(va_arg(ap, s32)); 184a6a4834cSSteven J. Hill if (ip->fields & JIMM) 185a6a4834cSSteven J. Hill op |= build_jimm(va_arg(ap, u32)); 186a6a4834cSSteven J. Hill if (ip->fields & FUNC) 187a6a4834cSSteven J. Hill op |= build_func(va_arg(ap, u32)); 188a6a4834cSSteven J. Hill if (ip->fields & SET) 189a6a4834cSSteven J. Hill op |= build_set(va_arg(ap, u32)); 190a6a4834cSSteven J. Hill if (ip->fields & SCIMM) 191a6a4834cSSteven J. Hill op |= build_scimm(va_arg(ap, u32)); 192a6a4834cSSteven J. Hill va_end(ap); 193a6a4834cSSteven J. Hill 194a6a4834cSSteven J. Hill #ifdef CONFIG_CPU_LITTLE_ENDIAN 195a6a4834cSSteven J. Hill **buf = ((op & 0xffff) << 16) | (op >> 16); 196a6a4834cSSteven J. Hill #else 197a6a4834cSSteven J. Hill **buf = op; 198a6a4834cSSteven J. Hill #endif 199a6a4834cSSteven J. Hill (*buf)++; 200a6a4834cSSteven J. Hill } 201a6a4834cSSteven J. Hill 202a6a4834cSSteven J. Hill static inline void __uasminit 203a6a4834cSSteven J. Hill __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) 204a6a4834cSSteven J. Hill { 205a6a4834cSSteven J. Hill long laddr = (long)lab->addr; 206a6a4834cSSteven J. Hill long raddr = (long)rel->addr; 207a6a4834cSSteven J. Hill 208a6a4834cSSteven J. Hill switch (rel->type) { 209a6a4834cSSteven J. Hill case R_MIPS_PC16: 210a6a4834cSSteven J. Hill #ifdef CONFIG_CPU_LITTLE_ENDIAN 211a6a4834cSSteven J. Hill *rel->addr |= (build_bimm(laddr - (raddr + 4)) << 16); 212a6a4834cSSteven J. Hill #else 213a6a4834cSSteven J. Hill *rel->addr |= build_bimm(laddr - (raddr + 4)); 214a6a4834cSSteven J. Hill #endif 215a6a4834cSSteven J. Hill break; 216a6a4834cSSteven J. Hill 217a6a4834cSSteven J. Hill default: 218a6a4834cSSteven J. Hill panic("Unsupported Micro-assembler relocation %d", 219a6a4834cSSteven J. Hill rel->type); 220a6a4834cSSteven J. Hill } 221a6a4834cSSteven J. Hill } 222