1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Synthesize TLB refill handlers at runtime. 7 * 8 * Copyright (C) 2004,2005 by Thiemo Seufer 9 */ 10 11 #include <stdarg.h> 12 13 #include <linux/config.h> 14 #include <linux/mm.h> 15 #include <linux/kernel.h> 16 #include <linux/types.h> 17 #include <linux/string.h> 18 #include <linux/init.h> 19 20 #include <asm/pgtable.h> 21 #include <asm/cacheflush.h> 22 #include <asm/mmu_context.h> 23 #include <asm/inst.h> 24 #include <asm/elf.h> 25 #include <asm/smp.h> 26 #include <asm/war.h> 27 28 /* #define DEBUG_TLB */ 29 30 static __init int __attribute__((unused)) r45k_bvahwbug(void) 31 { 32 /* XXX: We should probe for the presence of this bug, but we don't. */ 33 return 0; 34 } 35 36 static __init int __attribute__((unused)) r4k_250MHZhwbug(void) 37 { 38 /* XXX: We should probe for the presence of this bug, but we don't. */ 39 return 0; 40 } 41 42 static __init int __attribute__((unused)) bcm1250_m3_war(void) 43 { 44 return BCM1250_M3_WAR; 45 } 46 47 static __init int __attribute__((unused)) r10000_llsc_war(void) 48 { 49 return R10000_LLSC_WAR; 50 } 51 52 /* 53 * A little micro-assembler, intended for TLB refill handler 54 * synthesizing. It is intentionally kept simple, does only support 55 * a subset of instructions, and does not try to hide pipeline effects 56 * like branch delay slots. 57 */ 58 59 enum fields 60 { 61 RS = 0x001, 62 RT = 0x002, 63 RD = 0x004, 64 RE = 0x008, 65 SIMM = 0x010, 66 UIMM = 0x020, 67 BIMM = 0x040, 68 JIMM = 0x080, 69 FUNC = 0x100, 70 }; 71 72 #define OP_MASK 0x2f 73 #define OP_SH 26 74 #define RS_MASK 0x1f 75 #define RS_SH 21 76 #define RT_MASK 0x1f 77 #define RT_SH 16 78 #define RD_MASK 0x1f 79 #define RD_SH 11 80 #define RE_MASK 0x1f 81 #define RE_SH 6 82 #define IMM_MASK 0xffff 83 #define IMM_SH 0 84 #define JIMM_MASK 0x3ffffff 85 #define JIMM_SH 0 86 #define FUNC_MASK 0x2f 87 #define FUNC_SH 0 88 89 enum opcode { 90 insn_invalid, 91 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, 92 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 93 insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, 94 insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, 95 insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld, 96 insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, 97 insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, 98 insn_sra, insn_srl, insn_subu, insn_sw, insn_tlbp, insn_tlbwi, 99 insn_tlbwr, insn_xor, insn_xori 100 }; 101 102 struct insn { 103 enum opcode opcode; 104 u32 match; 105 enum fields fields; 106 }; 107 108 /* This macro sets the non-variable bits of an instruction. */ 109 #define M(a, b, c, d, e, f) \ 110 ((a) << OP_SH \ 111 | (b) << RS_SH \ 112 | (c) << RT_SH \ 113 | (d) << RD_SH \ 114 | (e) << RE_SH \ 115 | (f) << FUNC_SH) 116 117 static __initdata struct insn insn_table[] = { 118 { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM }, 119 { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD }, 120 { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD }, 121 { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM }, 122 { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM }, 123 { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM }, 124 { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM }, 125 { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM }, 126 { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM }, 127 { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM }, 128 { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM }, 129 { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM }, 130 { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD }, 131 { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD }, 132 { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD }, 133 { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE }, 134 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE }, 135 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE }, 136 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE }, 137 { insn_dsrl32, M(spec_op,0,0,0,0,dsrl32_op), RT | RD | RE }, 138 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD }, 139 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 }, 140 { insn_j, M(j_op,0,0,0,0,0), JIMM }, 141 { insn_jal, M(jal_op,0,0,0,0,0), JIMM }, 142 { insn_jr, M(spec_op,0,0,0,0,jr_op), RS }, 143 { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM }, 144 { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM }, 145 { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM }, 146 { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM }, 147 { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM }, 148 { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD }, 149 { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD }, 150 { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM }, 151 { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 }, 152 { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM }, 153 { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM }, 154 { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM }, 155 { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE }, 156 { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE }, 157 { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE }, 158 { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD }, 159 { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM }, 160 { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 }, 161 { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 }, 162 { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 }, 163 { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD }, 164 { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM }, 165 { insn_invalid, 0, 0 } 166 }; 167 168 #undef M 169 170 static __init u32 build_rs(u32 arg) 171 { 172 if (arg & ~RS_MASK) 173 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 174 175 return (arg & RS_MASK) << RS_SH; 176 } 177 178 static __init u32 build_rt(u32 arg) 179 { 180 if (arg & ~RT_MASK) 181 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 182 183 return (arg & RT_MASK) << RT_SH; 184 } 185 186 static __init u32 build_rd(u32 arg) 187 { 188 if (arg & ~RD_MASK) 189 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 190 191 return (arg & RD_MASK) << RD_SH; 192 } 193 194 static __init u32 build_re(u32 arg) 195 { 196 if (arg & ~RE_MASK) 197 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 198 199 return (arg & RE_MASK) << RE_SH; 200 } 201 202 static __init u32 build_simm(s32 arg) 203 { 204 if (arg > 0x7fff || arg < -0x8000) 205 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 206 207 return arg & 0xffff; 208 } 209 210 static __init u32 build_uimm(u32 arg) 211 { 212 if (arg & ~IMM_MASK) 213 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 214 215 return arg & IMM_MASK; 216 } 217 218 static __init u32 build_bimm(s32 arg) 219 { 220 if (arg > 0x1ffff || arg < -0x20000) 221 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 222 223 if (arg & 0x3) 224 printk(KERN_WARNING "Invalid TLB synthesizer branch target\n"); 225 226 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); 227 } 228 229 static __init u32 build_jimm(u32 arg) 230 { 231 if (arg & ~((JIMM_MASK) << 2)) 232 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 233 234 return (arg >> 2) & JIMM_MASK; 235 } 236 237 static __init u32 build_func(u32 arg) 238 { 239 if (arg & ~FUNC_MASK) 240 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 241 242 return arg & FUNC_MASK; 243 } 244 245 /* 246 * The order of opcode arguments is implicitly left to right, 247 * starting with RS and ending with FUNC or IMM. 248 */ 249 static void __init build_insn(u32 **buf, enum opcode opc, ...) 250 { 251 struct insn *ip = NULL; 252 unsigned int i; 253 va_list ap; 254 u32 op; 255 256 for (i = 0; insn_table[i].opcode != insn_invalid; i++) 257 if (insn_table[i].opcode == opc) { 258 ip = &insn_table[i]; 259 break; 260 } 261 262 if (!ip) 263 panic("Unsupported TLB synthesizer instruction %d", opc); 264 265 op = ip->match; 266 va_start(ap, opc); 267 if (ip->fields & RS) op |= build_rs(va_arg(ap, u32)); 268 if (ip->fields & RT) op |= build_rt(va_arg(ap, u32)); 269 if (ip->fields & RD) op |= build_rd(va_arg(ap, u32)); 270 if (ip->fields & RE) op |= build_re(va_arg(ap, u32)); 271 if (ip->fields & SIMM) op |= build_simm(va_arg(ap, s32)); 272 if (ip->fields & UIMM) op |= build_uimm(va_arg(ap, u32)); 273 if (ip->fields & BIMM) op |= build_bimm(va_arg(ap, s32)); 274 if (ip->fields & JIMM) op |= build_jimm(va_arg(ap, u32)); 275 if (ip->fields & FUNC) op |= build_func(va_arg(ap, u32)); 276 va_end(ap); 277 278 **buf = op; 279 (*buf)++; 280 } 281 282 #define I_u1u2u3(op) \ 283 static inline void i##op(u32 **buf, unsigned int a, \ 284 unsigned int b, unsigned int c) \ 285 { \ 286 build_insn(buf, insn##op, a, b, c); \ 287 } 288 289 #define I_u2u1u3(op) \ 290 static inline void i##op(u32 **buf, unsigned int a, \ 291 unsigned int b, unsigned int c) \ 292 { \ 293 build_insn(buf, insn##op, b, a, c); \ 294 } 295 296 #define I_u3u1u2(op) \ 297 static inline void i##op(u32 **buf, unsigned int a, \ 298 unsigned int b, unsigned int c) \ 299 { \ 300 build_insn(buf, insn##op, b, c, a); \ 301 } 302 303 #define I_u1u2s3(op) \ 304 static inline void i##op(u32 **buf, unsigned int a, \ 305 unsigned int b, signed int c) \ 306 { \ 307 build_insn(buf, insn##op, a, b, c); \ 308 } 309 310 #define I_u2s3u1(op) \ 311 static inline void i##op(u32 **buf, unsigned int a, \ 312 signed int b, unsigned int c) \ 313 { \ 314 build_insn(buf, insn##op, c, a, b); \ 315 } 316 317 #define I_u2u1s3(op) \ 318 static inline void i##op(u32 **buf, unsigned int a, \ 319 unsigned int b, signed int c) \ 320 { \ 321 build_insn(buf, insn##op, b, a, c); \ 322 } 323 324 #define I_u1u2(op) \ 325 static inline void i##op(u32 **buf, unsigned int a, \ 326 unsigned int b) \ 327 { \ 328 build_insn(buf, insn##op, a, b); \ 329 } 330 331 #define I_u1s2(op) \ 332 static inline void i##op(u32 **buf, unsigned int a, \ 333 signed int b) \ 334 { \ 335 build_insn(buf, insn##op, a, b); \ 336 } 337 338 #define I_u1(op) \ 339 static inline void i##op(u32 **buf, unsigned int a) \ 340 { \ 341 build_insn(buf, insn##op, a); \ 342 } 343 344 #define I_0(op) \ 345 static inline void i##op(u32 **buf) \ 346 { \ 347 build_insn(buf, insn##op); \ 348 } 349 350 I_u2u1s3(_addiu); 351 I_u3u1u2(_addu); 352 I_u2u1u3(_andi); 353 I_u3u1u2(_and); 354 I_u1u2s3(_beq); 355 I_u1u2s3(_beql); 356 I_u1s2(_bgez); 357 I_u1s2(_bgezl); 358 I_u1s2(_bltz); 359 I_u1s2(_bltzl); 360 I_u1u2s3(_bne); 361 I_u1u2(_dmfc0); 362 I_u1u2(_dmtc0); 363 I_u2u1s3(_daddiu); 364 I_u3u1u2(_daddu); 365 I_u2u1u3(_dsll); 366 I_u2u1u3(_dsll32); 367 I_u2u1u3(_dsra); 368 I_u2u1u3(_dsrl); 369 I_u2u1u3(_dsrl32); 370 I_u3u1u2(_dsubu); 371 I_0(_eret); 372 I_u1(_j); 373 I_u1(_jal); 374 I_u1(_jr); 375 I_u2s3u1(_ld); 376 I_u2s3u1(_ll); 377 I_u2s3u1(_lld); 378 I_u1s2(_lui); 379 I_u2s3u1(_lw); 380 I_u1u2(_mfc0); 381 I_u1u2(_mtc0); 382 I_u2u1u3(_ori); 383 I_0(_rfe); 384 I_u2s3u1(_sc); 385 I_u2s3u1(_scd); 386 I_u2s3u1(_sd); 387 I_u2u1u3(_sll); 388 I_u2u1u3(_sra); 389 I_u2u1u3(_srl); 390 I_u3u1u2(_subu); 391 I_u2s3u1(_sw); 392 I_0(_tlbp); 393 I_0(_tlbwi); 394 I_0(_tlbwr); 395 I_u3u1u2(_xor) 396 I_u2u1u3(_xori); 397 398 /* 399 * handling labels 400 */ 401 402 enum label_id { 403 label_invalid, 404 label_second_part, 405 label_leave, 406 label_vmalloc, 407 label_vmalloc_done, 408 label_tlbw_hazard, 409 label_split, 410 label_nopage_tlbl, 411 label_nopage_tlbs, 412 label_nopage_tlbm, 413 label_smp_pgtable_change, 414 label_r3000_write_probe_fail, 415 label_r3000_write_probe_ok 416 }; 417 418 struct label { 419 u32 *addr; 420 enum label_id lab; 421 }; 422 423 static __init void build_label(struct label **lab, u32 *addr, 424 enum label_id l) 425 { 426 (*lab)->addr = addr; 427 (*lab)->lab = l; 428 (*lab)++; 429 } 430 431 #define L_LA(lb) \ 432 static inline void l##lb(struct label **lab, u32 *addr) \ 433 { \ 434 build_label(lab, addr, label##lb); \ 435 } 436 437 L_LA(_second_part) 438 L_LA(_leave) 439 L_LA(_vmalloc) 440 L_LA(_vmalloc_done) 441 L_LA(_tlbw_hazard) 442 L_LA(_split) 443 L_LA(_nopage_tlbl) 444 L_LA(_nopage_tlbs) 445 L_LA(_nopage_tlbm) 446 L_LA(_smp_pgtable_change) 447 L_LA(_r3000_write_probe_fail) 448 L_LA(_r3000_write_probe_ok) 449 450 /* convenience macros for instructions */ 451 #ifdef CONFIG_MIPS64 452 # define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off) 453 # define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off) 454 # define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh) 455 # define i_SRA(buf, rs, rt, sh) i_dsra(buf, rs, rt, sh) 456 # define i_SRL(buf, rs, rt, sh) i_dsrl(buf, rs, rt, sh) 457 # define i_MFC0(buf, rt, rd) i_dmfc0(buf, rt, rd) 458 # define i_MTC0(buf, rt, rd) i_dmtc0(buf, rt, rd) 459 # define i_ADDIU(buf, rs, rt, val) i_daddiu(buf, rs, rt, val) 460 # define i_ADDU(buf, rs, rt, rd) i_daddu(buf, rs, rt, rd) 461 # define i_SUBU(buf, rs, rt, rd) i_dsubu(buf, rs, rt, rd) 462 # define i_LL(buf, rs, rt, off) i_lld(buf, rs, rt, off) 463 # define i_SC(buf, rs, rt, off) i_scd(buf, rs, rt, off) 464 #else 465 # define i_LW(buf, rs, rt, off) i_lw(buf, rs, rt, off) 466 # define i_SW(buf, rs, rt, off) i_sw(buf, rs, rt, off) 467 # define i_SLL(buf, rs, rt, sh) i_sll(buf, rs, rt, sh) 468 # define i_SRA(buf, rs, rt, sh) i_sra(buf, rs, rt, sh) 469 # define i_SRL(buf, rs, rt, sh) i_srl(buf, rs, rt, sh) 470 # define i_MFC0(buf, rt, rd) i_mfc0(buf, rt, rd) 471 # define i_MTC0(buf, rt, rd) i_mtc0(buf, rt, rd) 472 # define i_ADDIU(buf, rs, rt, val) i_addiu(buf, rs, rt, val) 473 # define i_ADDU(buf, rs, rt, rd) i_addu(buf, rs, rt, rd) 474 # define i_SUBU(buf, rs, rt, rd) i_subu(buf, rs, rt, rd) 475 # define i_LL(buf, rs, rt, off) i_ll(buf, rs, rt, off) 476 # define i_SC(buf, rs, rt, off) i_sc(buf, rs, rt, off) 477 #endif 478 479 #define i_b(buf, off) i_beq(buf, 0, 0, off) 480 #define i_beqz(buf, rs, off) i_beq(buf, rs, 0, off) 481 #define i_beqzl(buf, rs, off) i_beql(buf, rs, 0, off) 482 #define i_bnez(buf, rs, off) i_bne(buf, rs, 0, off) 483 #define i_bnezl(buf, rs, off) i_bnel(buf, rs, 0, off) 484 #define i_move(buf, a, b) i_ADDU(buf, a, 0, b) 485 #define i_nop(buf) i_sll(buf, 0, 0, 0) 486 #define i_ssnop(buf) i_sll(buf, 0, 0, 1) 487 #define i_ehb(buf) i_sll(buf, 0, 0, 3) 488 489 #ifdef CONFIG_MIPS64 490 static __init int __attribute__((unused)) in_compat_space_p(long addr) 491 { 492 /* Is this address in 32bit compat space? */ 493 return (((addr) & 0xffffffff00000000) == 0xffffffff00000000); 494 } 495 496 static __init int __attribute__((unused)) rel_highest(long val) 497 { 498 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 499 } 500 501 static __init int __attribute__((unused)) rel_higher(long val) 502 { 503 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 504 } 505 #endif 506 507 static __init int rel_hi(long val) 508 { 509 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 510 } 511 512 static __init int rel_lo(long val) 513 { 514 return ((val & 0xffff) ^ 0x8000) - 0x8000; 515 } 516 517 static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) 518 { 519 #if CONFIG_MIPS64 520 if (!in_compat_space_p(addr)) { 521 i_lui(buf, rs, rel_highest(addr)); 522 if (rel_higher(addr)) 523 i_daddiu(buf, rs, rs, rel_higher(addr)); 524 if (rel_hi(addr)) { 525 i_dsll(buf, rs, rs, 16); 526 i_daddiu(buf, rs, rs, rel_hi(addr)); 527 i_dsll(buf, rs, rs, 16); 528 } else 529 i_dsll32(buf, rs, rs, 0); 530 } else 531 #endif 532 i_lui(buf, rs, rel_hi(addr)); 533 } 534 535 static __init void __attribute__((unused)) i_LA(u32 **buf, unsigned int rs, 536 long addr) 537 { 538 i_LA_mostly(buf, rs, addr); 539 if (rel_lo(addr)) 540 i_ADDIU(buf, rs, rs, rel_lo(addr)); 541 } 542 543 /* 544 * handle relocations 545 */ 546 547 struct reloc { 548 u32 *addr; 549 unsigned int type; 550 enum label_id lab; 551 }; 552 553 static __init void r_mips_pc16(struct reloc **rel, u32 *addr, 554 enum label_id l) 555 { 556 (*rel)->addr = addr; 557 (*rel)->type = R_MIPS_PC16; 558 (*rel)->lab = l; 559 (*rel)++; 560 } 561 562 static inline void __resolve_relocs(struct reloc *rel, struct label *lab) 563 { 564 long laddr = (long)lab->addr; 565 long raddr = (long)rel->addr; 566 567 switch (rel->type) { 568 case R_MIPS_PC16: 569 *rel->addr |= build_bimm(laddr - (raddr + 4)); 570 break; 571 572 default: 573 panic("Unsupported TLB synthesizer relocation %d", 574 rel->type); 575 } 576 } 577 578 static __init void resolve_relocs(struct reloc *rel, struct label *lab) 579 { 580 struct label *l; 581 582 for (; rel->lab != label_invalid; rel++) 583 for (l = lab; l->lab != label_invalid; l++) 584 if (rel->lab == l->lab) 585 __resolve_relocs(rel, l); 586 } 587 588 static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end, 589 long off) 590 { 591 for (; rel->lab != label_invalid; rel++) 592 if (rel->addr >= first && rel->addr < end) 593 rel->addr += off; 594 } 595 596 static __init void move_labels(struct label *lab, u32 *first, u32 *end, 597 long off) 598 { 599 for (; lab->lab != label_invalid; lab++) 600 if (lab->addr >= first && lab->addr < end) 601 lab->addr += off; 602 } 603 604 static __init void copy_handler(struct reloc *rel, struct label *lab, 605 u32 *first, u32 *end, u32 *target) 606 { 607 long off = (long)(target - first); 608 609 memcpy(target, first, (end - first) * sizeof(u32)); 610 611 move_relocs(rel, first, end, off); 612 move_labels(lab, first, end, off); 613 } 614 615 static __init int __attribute__((unused)) insn_has_bdelay(struct reloc *rel, 616 u32 *addr) 617 { 618 for (; rel->lab != label_invalid; rel++) { 619 if (rel->addr == addr 620 && (rel->type == R_MIPS_PC16 621 || rel->type == R_MIPS_26)) 622 return 1; 623 } 624 625 return 0; 626 } 627 628 /* convenience functions for labeled branches */ 629 static void __attribute__((unused)) il_bltz(u32 **p, struct reloc **r, 630 unsigned int reg, enum label_id l) 631 { 632 r_mips_pc16(r, *p, l); 633 i_bltz(p, reg, 0); 634 } 635 636 static void __attribute__((unused)) il_b(u32 **p, struct reloc **r, 637 enum label_id l) 638 { 639 r_mips_pc16(r, *p, l); 640 i_b(p, 0); 641 } 642 643 static void il_beqz(u32 **p, struct reloc **r, unsigned int reg, 644 enum label_id l) 645 { 646 r_mips_pc16(r, *p, l); 647 i_beqz(p, reg, 0); 648 } 649 650 static void __attribute__((unused)) 651 il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) 652 { 653 r_mips_pc16(r, *p, l); 654 i_beqzl(p, reg, 0); 655 } 656 657 static void il_bnez(u32 **p, struct reloc **r, unsigned int reg, 658 enum label_id l) 659 { 660 r_mips_pc16(r, *p, l); 661 i_bnez(p, reg, 0); 662 } 663 664 static void il_bgezl(u32 **p, struct reloc **r, unsigned int reg, 665 enum label_id l) 666 { 667 r_mips_pc16(r, *p, l); 668 i_bgezl(p, reg, 0); 669 } 670 671 /* The only general purpose registers allowed in TLB handlers. */ 672 #define K0 26 673 #define K1 27 674 675 /* Some CP0 registers */ 676 #define C0_INDEX 0 677 #define C0_ENTRYLO0 2 678 #define C0_ENTRYLO1 3 679 #define C0_CONTEXT 4 680 #define C0_BADVADDR 8 681 #define C0_ENTRYHI 10 682 #define C0_EPC 14 683 #define C0_XCONTEXT 20 684 685 #ifdef CONFIG_MIPS64 686 # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT) 687 #else 688 # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT) 689 #endif 690 691 /* The worst case length of the handler is around 18 instructions for 692 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. 693 * Maximum space available is 32 instructions for R3000 and 64 694 * instructions for R4000. 695 * 696 * We deliberately chose a buffer size of 128, so we won't scribble 697 * over anything important on overflow before we panic. 698 */ 699 static __initdata u32 tlb_handler[128]; 700 701 /* simply assume worst case size for labels and relocs */ 702 static __initdata struct label labels[128]; 703 static __initdata struct reloc relocs[128]; 704 705 /* 706 * The R3000 TLB handler is simple. 707 */ 708 static void __init build_r3000_tlb_refill_handler(void) 709 { 710 long pgdc = (long)pgd_current; 711 u32 *p; 712 713 memset(tlb_handler, 0, sizeof(tlb_handler)); 714 p = tlb_handler; 715 716 i_mfc0(&p, K0, C0_BADVADDR); 717 i_lui(&p, K1, rel_hi(pgdc)); /* cp0 delay */ 718 i_lw(&p, K1, rel_lo(pgdc), K1); 719 i_srl(&p, K0, K0, 22); /* load delay */ 720 i_sll(&p, K0, K0, 2); 721 i_addu(&p, K1, K1, K0); 722 i_mfc0(&p, K0, C0_CONTEXT); 723 i_lw(&p, K1, 0, K1); /* cp0 delay */ 724 i_andi(&p, K0, K0, 0xffc); /* load delay */ 725 i_addu(&p, K1, K1, K0); 726 i_lw(&p, K0, 0, K1); 727 i_nop(&p); /* load delay */ 728 i_mtc0(&p, K0, C0_ENTRYLO0); 729 i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ 730 i_tlbwr(&p); /* cp0 delay */ 731 i_jr(&p, K1); 732 i_rfe(&p); /* branch delay */ 733 734 if (p > tlb_handler + 32) 735 panic("TLB refill handler space exceeded"); 736 737 printk("Synthesized TLB handler (%u instructions).\n", 738 (unsigned int)(p - tlb_handler)); 739 #ifdef DEBUG_TLB 740 { 741 int i; 742 743 for (i = 0; i < (p - tlb_handler); i++) 744 printk("%08x\n", tlb_handler[i]); 745 } 746 #endif 747 748 memcpy((void *)CAC_BASE, tlb_handler, 0x80); 749 flush_icache_range(CAC_BASE, CAC_BASE + 0x80); 750 } 751 752 /* 753 * The R4000 TLB handler is much more complicated. We have two 754 * consecutive handler areas with 32 instructions space each. 755 * Since they aren't used at the same time, we can overflow in the 756 * other one.To keep things simple, we first assume linear space, 757 * then we relocate it to the final handler layout as needed. 758 */ 759 static __initdata u32 final_handler[64]; 760 761 /* 762 * Hazards 763 * 764 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: 765 * 2. A timing hazard exists for the TLBP instruction. 766 * 767 * stalling_instruction 768 * TLBP 769 * 770 * The JTLB is being read for the TLBP throughout the stall generated by the 771 * previous instruction. This is not really correct as the stalling instruction 772 * can modify the address used to access the JTLB. The failure symptom is that 773 * the TLBP instruction will use an address created for the stalling instruction 774 * and not the address held in C0_ENHI and thus report the wrong results. 775 * 776 * The software work-around is to not allow the instruction preceding the TLBP 777 * to stall - make it an NOP or some other instruction guaranteed not to stall. 778 * 779 * Errata 2 will not be fixed. This errata is also on the R5000. 780 * 781 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 782 */ 783 static __init void __attribute__((unused)) build_tlb_probe_entry(u32 **p) 784 { 785 switch (current_cpu_data.cputype) { 786 case CPU_R5000: 787 case CPU_R5000A: 788 case CPU_NEVADA: 789 i_nop(p); 790 i_tlbp(p); 791 break; 792 793 default: 794 i_tlbp(p); 795 break; 796 } 797 } 798 799 /* 800 * Write random or indexed TLB entry, and care about the hazards from 801 * the preceeding mtc0 and for the following eret. 802 */ 803 enum tlb_write_entry { tlb_random, tlb_indexed }; 804 805 static __init void build_tlb_write_entry(u32 **p, struct label **l, 806 struct reloc **r, 807 enum tlb_write_entry wmode) 808 { 809 void(*tlbw)(u32 **) = NULL; 810 811 switch (wmode) { 812 case tlb_random: tlbw = i_tlbwr; break; 813 case tlb_indexed: tlbw = i_tlbwi; break; 814 } 815 816 switch (current_cpu_data.cputype) { 817 case CPU_R4000PC: 818 case CPU_R4000SC: 819 case CPU_R4000MC: 820 case CPU_R4400PC: 821 case CPU_R4400SC: 822 case CPU_R4400MC: 823 /* 824 * This branch uses up a mtc0 hazard nop slot and saves 825 * two nops after the tlbw instruction. 826 */ 827 il_bgezl(p, r, 0, label_tlbw_hazard); 828 tlbw(p); 829 l_tlbw_hazard(l, *p); 830 i_nop(p); 831 break; 832 833 case CPU_R4600: 834 case CPU_R4700: 835 case CPU_R5000: 836 case CPU_R5000A: 837 case CPU_5KC: 838 case CPU_TX49XX: 839 case CPU_AU1000: 840 case CPU_AU1100: 841 case CPU_AU1500: 842 case CPU_AU1550: 843 i_nop(p); 844 tlbw(p); 845 break; 846 847 case CPU_R10000: 848 case CPU_R12000: 849 case CPU_4KC: 850 case CPU_SB1: 851 case CPU_4KSC: 852 case CPU_20KC: 853 case CPU_25KF: 854 tlbw(p); 855 break; 856 857 case CPU_NEVADA: 858 i_nop(p); /* QED specifies 2 nops hazard */ 859 /* 860 * This branch uses up a mtc0 hazard nop slot and saves 861 * a nop after the tlbw instruction. 862 */ 863 il_bgezl(p, r, 0, label_tlbw_hazard); 864 tlbw(p); 865 l_tlbw_hazard(l, *p); 866 break; 867 868 case CPU_RM7000: 869 i_nop(p); 870 i_nop(p); 871 i_nop(p); 872 i_nop(p); 873 tlbw(p); 874 break; 875 876 case CPU_4KEC: 877 case CPU_24K: 878 i_ehb(p); 879 tlbw(p); 880 break; 881 882 case CPU_RM9000: 883 /* 884 * When the JTLB is updated by tlbwi or tlbwr, a subsequent 885 * use of the JTLB for instructions should not occur for 4 886 * cpu cycles and use for data translations should not occur 887 * for 3 cpu cycles. 888 */ 889 i_ssnop(p); 890 i_ssnop(p); 891 i_ssnop(p); 892 i_ssnop(p); 893 tlbw(p); 894 i_ssnop(p); 895 i_ssnop(p); 896 i_ssnop(p); 897 i_ssnop(p); 898 break; 899 900 case CPU_VR4111: 901 case CPU_VR4121: 902 case CPU_VR4122: 903 case CPU_VR4181: 904 case CPU_VR4181A: 905 i_nop(p); 906 i_nop(p); 907 tlbw(p); 908 i_nop(p); 909 i_nop(p); 910 break; 911 912 case CPU_VR4131: 913 case CPU_VR4133: 914 i_nop(p); 915 i_nop(p); 916 tlbw(p); 917 break; 918 919 default: 920 panic("No TLB refill handler yet (CPU type: %d)", 921 current_cpu_data.cputype); 922 break; 923 } 924 } 925 926 #ifdef CONFIG_MIPS64 927 /* 928 * TMP and PTR are scratch. 929 * TMP will be clobbered, PTR will hold the pmd entry. 930 */ 931 static __init void 932 build_get_pmde64(u32 **p, struct label **l, struct reloc **r, 933 unsigned int tmp, unsigned int ptr) 934 { 935 long pgdc = (long)pgd_current; 936 937 /* 938 * The vmalloc handling is not in the hotpath. 939 */ 940 i_dmfc0(p, tmp, C0_BADVADDR); 941 il_bltz(p, r, tmp, label_vmalloc); 942 /* No i_nop needed here, since the next insn doesn't touch TMP. */ 943 944 #ifdef CONFIG_SMP 945 /* 946 * 64 bit SMP has the lower part of &pgd_current[smp_processor_id()] 947 * stored in CONTEXT. 948 */ 949 if (in_compat_space_p(pgdc)) { 950 i_dmfc0(p, ptr, C0_CONTEXT); 951 i_dsra(p, ptr, ptr, 23); 952 i_ld(p, ptr, 0, ptr); 953 } else { 954 #ifdef CONFIG_BUILD_ELF64 955 i_dmfc0(p, ptr, C0_CONTEXT); 956 i_dsrl(p, ptr, ptr, 23); 957 i_dsll(p, ptr, ptr, 3); 958 i_LA_mostly(p, tmp, pgdc); 959 i_daddu(p, ptr, ptr, tmp); 960 i_dmfc0(p, tmp, C0_BADVADDR); 961 i_ld(p, ptr, rel_lo(pgdc), ptr); 962 #else 963 i_dmfc0(p, ptr, C0_CONTEXT); 964 i_lui(p, tmp, rel_highest(pgdc)); 965 i_dsll(p, ptr, ptr, 9); 966 i_daddiu(p, tmp, tmp, rel_higher(pgdc)); 967 i_dsrl32(p, ptr, ptr, 0); 968 i_and(p, ptr, ptr, tmp); 969 i_dmfc0(p, tmp, C0_BADVADDR); 970 i_ld(p, ptr, 0, ptr); 971 #endif 972 } 973 #else 974 i_LA_mostly(p, ptr, pgdc); 975 i_ld(p, ptr, rel_lo(pgdc), ptr); 976 #endif 977 978 l_vmalloc_done(l, *p); 979 i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); /* get pgd offset in bytes */ 980 i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 981 i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 982 i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 983 i_ld(p, ptr, 0, ptr); /* get pmd pointer */ 984 i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ 985 i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); 986 i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ 987 } 988 989 /* 990 * BVADDR is the faulting address, PTR is scratch. 991 * PTR will hold the pgd for vmalloc. 992 */ 993 static __init void 994 build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, 995 unsigned int bvaddr, unsigned int ptr) 996 { 997 long swpd = (long)swapper_pg_dir; 998 999 l_vmalloc(l, *p); 1000 i_LA(p, ptr, VMALLOC_START); 1001 i_dsubu(p, bvaddr, bvaddr, ptr); 1002 1003 if (in_compat_space_p(swpd) && !rel_lo(swpd)) { 1004 il_b(p, r, label_vmalloc_done); 1005 i_lui(p, ptr, rel_hi(swpd)); 1006 } else { 1007 i_LA_mostly(p, ptr, swpd); 1008 il_b(p, r, label_vmalloc_done); 1009 i_daddiu(p, ptr, ptr, rel_lo(swpd)); 1010 } 1011 } 1012 1013 #else /* !CONFIG_MIPS64 */ 1014 1015 /* 1016 * TMP and PTR are scratch. 1017 * TMP will be clobbered, PTR will hold the pgd entry. 1018 */ 1019 static __init void __attribute__((unused)) 1020 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 1021 { 1022 long pgdc = (long)pgd_current; 1023 1024 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ 1025 #ifdef CONFIG_SMP 1026 i_mfc0(p, ptr, C0_CONTEXT); 1027 i_LA_mostly(p, tmp, pgdc); 1028 i_srl(p, ptr, ptr, 23); 1029 i_sll(p, ptr, ptr, 2); 1030 i_addu(p, ptr, tmp, ptr); 1031 #else 1032 i_LA_mostly(p, ptr, pgdc); 1033 #endif 1034 i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 1035 i_lw(p, ptr, rel_lo(pgdc), ptr); 1036 i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ 1037 i_sll(p, tmp, tmp, PGD_T_LOG2); 1038 i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 1039 } 1040 1041 #endif /* !CONFIG_MIPS64 */ 1042 1043 static __init void build_adjust_context(u32 **p, unsigned int ctx) 1044 { 1045 unsigned int shift = 4 - (PTE_T_LOG2 + 1); 1046 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 1047 1048 switch (current_cpu_data.cputype) { 1049 case CPU_VR41XX: 1050 case CPU_VR4111: 1051 case CPU_VR4121: 1052 case CPU_VR4122: 1053 case CPU_VR4131: 1054 case CPU_VR4181: 1055 case CPU_VR4181A: 1056 case CPU_VR4133: 1057 shift += 2; 1058 break; 1059 1060 default: 1061 break; 1062 } 1063 1064 if (shift) 1065 i_SRL(p, ctx, ctx, shift); 1066 i_andi(p, ctx, ctx, mask); 1067 } 1068 1069 static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 1070 { 1071 /* 1072 * Bug workaround for the Nevada. It seems as if under certain 1073 * circumstances the move from cp0_context might produce a 1074 * bogus result when the mfc0 instruction and its consumer are 1075 * in a different cacheline or a load instruction, probably any 1076 * memory reference, is between them. 1077 */ 1078 switch (current_cpu_data.cputype) { 1079 case CPU_NEVADA: 1080 i_LW(p, ptr, 0, ptr); 1081 GET_CONTEXT(p, tmp); /* get context reg */ 1082 break; 1083 1084 default: 1085 GET_CONTEXT(p, tmp); /* get context reg */ 1086 i_LW(p, ptr, 0, ptr); 1087 break; 1088 } 1089 1090 build_adjust_context(p, tmp); 1091 i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1092 } 1093 1094 static __init void build_update_entries(u32 **p, unsigned int tmp, 1095 unsigned int ptep) 1096 { 1097 /* 1098 * 64bit address support (36bit on a 32bit CPU) in a 32bit 1099 * Kernel is a special case. Only a few CPUs use it. 1100 */ 1101 #ifdef CONFIG_64BIT_PHYS_ADDR 1102 if (cpu_has_64bits) { 1103 i_ld(p, tmp, 0, ptep); /* get even pte */ 1104 i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ 1105 i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ 1106 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 1107 i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ 1108 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 1109 } else { 1110 int pte_off_even = sizeof(pte_t) / 2; 1111 int pte_off_odd = pte_off_even + sizeof(pte_t); 1112 1113 /* The pte entries are pre-shifted */ 1114 i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ 1115 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 1116 i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ 1117 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 1118 } 1119 #else 1120 i_LW(p, tmp, 0, ptep); /* get even pte */ 1121 i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ 1122 if (r45k_bvahwbug()) 1123 build_tlb_probe_entry(p); 1124 i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ 1125 if (r4k_250MHZhwbug()) 1126 i_mtc0(p, 0, C0_ENTRYLO0); 1127 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 1128 i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ 1129 if (r45k_bvahwbug()) 1130 i_mfc0(p, tmp, C0_INDEX); 1131 if (r4k_250MHZhwbug()) 1132 i_mtc0(p, 0, C0_ENTRYLO1); 1133 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 1134 #endif 1135 } 1136 1137 static void __init build_r4000_tlb_refill_handler(void) 1138 { 1139 u32 *p = tlb_handler; 1140 struct label *l = labels; 1141 struct reloc *r = relocs; 1142 u32 *f; 1143 unsigned int final_len; 1144 1145 memset(tlb_handler, 0, sizeof(tlb_handler)); 1146 memset(labels, 0, sizeof(labels)); 1147 memset(relocs, 0, sizeof(relocs)); 1148 memset(final_handler, 0, sizeof(final_handler)); 1149 1150 /* 1151 * create the plain linear handler 1152 */ 1153 if (bcm1250_m3_war()) { 1154 i_MFC0(&p, K0, C0_BADVADDR); 1155 i_MFC0(&p, K1, C0_ENTRYHI); 1156 i_xor(&p, K0, K0, K1); 1157 i_SRL(&p, K0, K0, PAGE_SHIFT + 1); 1158 il_bnez(&p, &r, K0, label_leave); 1159 /* No need for i_nop */ 1160 } 1161 1162 #ifdef CONFIG_MIPS64 1163 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 1164 #else 1165 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 1166 #endif 1167 1168 build_get_ptep(&p, K0, K1); 1169 build_update_entries(&p, K0, K1); 1170 build_tlb_write_entry(&p, &l, &r, tlb_random); 1171 l_leave(&l, p); 1172 i_eret(&p); /* return from trap */ 1173 1174 #ifdef CONFIG_MIPS64 1175 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); 1176 #endif 1177 1178 /* 1179 * Overflow check: For the 64bit handler, we need at least one 1180 * free instruction slot for the wrap-around branch. In worst 1181 * case, if the intended insertion point is a delay slot, we 1182 * need three, with the the second nop'ed and the third being 1183 * unused. 1184 */ 1185 #ifdef CONFIG_MIPS32 1186 if ((p - tlb_handler) > 64) 1187 panic("TLB refill handler space exceeded"); 1188 #else 1189 if (((p - tlb_handler) > 63) 1190 || (((p - tlb_handler) > 61) 1191 && insn_has_bdelay(relocs, tlb_handler + 29))) 1192 panic("TLB refill handler space exceeded"); 1193 #endif 1194 1195 /* 1196 * Now fold the handler in the TLB refill handler space. 1197 */ 1198 #ifdef CONFIG_MIPS32 1199 f = final_handler; 1200 /* Simplest case, just copy the handler. */ 1201 copy_handler(relocs, labels, tlb_handler, p, f); 1202 final_len = p - tlb_handler; 1203 #else /* CONFIG_MIPS64 */ 1204 f = final_handler + 32; 1205 if ((p - tlb_handler) <= 32) { 1206 /* Just copy the handler. */ 1207 copy_handler(relocs, labels, tlb_handler, p, f); 1208 final_len = p - tlb_handler; 1209 } else { 1210 u32 *split = tlb_handler + 30; 1211 1212 /* 1213 * Find the split point. 1214 */ 1215 if (insn_has_bdelay(relocs, split - 1)) 1216 split--; 1217 1218 /* Copy first part of the handler. */ 1219 copy_handler(relocs, labels, tlb_handler, split, f); 1220 f += split - tlb_handler; 1221 1222 /* Insert branch. */ 1223 l_split(&l, final_handler); 1224 il_b(&f, &r, label_split); 1225 if (insn_has_bdelay(relocs, split)) 1226 i_nop(&f); 1227 else { 1228 copy_handler(relocs, labels, split, split + 1, f); 1229 move_labels(labels, f, f + 1, -1); 1230 f++; 1231 split++; 1232 } 1233 1234 /* Copy the rest of the handler. */ 1235 copy_handler(relocs, labels, split, p, final_handler); 1236 final_len = (f - (final_handler + 32)) + (p - split); 1237 } 1238 #endif /* CONFIG_MIPS64 */ 1239 1240 resolve_relocs(relocs, labels); 1241 printk("Synthesized TLB refill handler (%u instructions).\n", 1242 final_len); 1243 1244 #ifdef DEBUG_TLB 1245 { 1246 int i; 1247 1248 for (i = 0; i < 64; i++) 1249 printk("%08x\n", final_handler[i]); 1250 } 1251 #endif 1252 1253 memcpy((void *)CAC_BASE, final_handler, 0x100); 1254 flush_icache_range(CAC_BASE, CAC_BASE + 0x100); 1255 } 1256 1257 /* 1258 * TLB load/store/modify handlers. 1259 * 1260 * Only the fastpath gets synthesized at runtime, the slowpath for 1261 * do_page_fault remains normal asm. 1262 */ 1263 extern void tlb_do_page_fault_0(void); 1264 extern void tlb_do_page_fault_1(void); 1265 1266 #define __tlb_handler_align \ 1267 __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT))) 1268 1269 /* 1270 * 128 instructions for the fastpath handler is generous and should 1271 * never be exceeded. 1272 */ 1273 #define FASTPATH_SIZE 128 1274 1275 u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE]; 1276 u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE]; 1277 u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE]; 1278 1279 static void __init 1280 iPTE_LW(u32 **p, struct label **l, unsigned int pte, int offset, 1281 unsigned int ptr) 1282 { 1283 #ifdef CONFIG_SMP 1284 # ifdef CONFIG_64BIT_PHYS_ADDR 1285 if (cpu_has_64bits) 1286 i_lld(p, pte, offset, ptr); 1287 else 1288 # endif 1289 i_LL(p, pte, offset, ptr); 1290 #else 1291 # ifdef CONFIG_64BIT_PHYS_ADDR 1292 if (cpu_has_64bits) 1293 i_ld(p, pte, offset, ptr); 1294 else 1295 # endif 1296 i_LW(p, pte, offset, ptr); 1297 #endif 1298 } 1299 1300 static void __init 1301 iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, int offset, 1302 unsigned int ptr) 1303 { 1304 #ifdef CONFIG_SMP 1305 # ifdef CONFIG_64BIT_PHYS_ADDR 1306 if (cpu_has_64bits) 1307 i_scd(p, pte, offset, ptr); 1308 else 1309 # endif 1310 i_SC(p, pte, offset, ptr); 1311 1312 if (r10000_llsc_war()) 1313 il_beqzl(p, r, pte, label_smp_pgtable_change); 1314 else 1315 il_beqz(p, r, pte, label_smp_pgtable_change); 1316 1317 # ifdef CONFIG_64BIT_PHYS_ADDR 1318 if (!cpu_has_64bits) { 1319 /* no i_nop needed */ 1320 i_ll(p, pte, sizeof(pte_t) / 2, ptr); 1321 i_ori(p, pte, pte, _PAGE_VALID); 1322 i_sc(p, pte, sizeof(pte_t) / 2, ptr); 1323 il_beqz(p, r, pte, label_smp_pgtable_change); 1324 /* no i_nop needed */ 1325 i_lw(p, pte, 0, ptr); 1326 } else 1327 i_nop(p); 1328 # else 1329 i_nop(p); 1330 # endif 1331 #else 1332 # ifdef CONFIG_64BIT_PHYS_ADDR 1333 if (cpu_has_64bits) 1334 i_sd(p, pte, offset, ptr); 1335 else 1336 # endif 1337 i_SW(p, pte, offset, ptr); 1338 1339 # ifdef CONFIG_64BIT_PHYS_ADDR 1340 if (!cpu_has_64bits) { 1341 i_lw(p, pte, sizeof(pte_t) / 2, ptr); 1342 i_ori(p, pte, pte, _PAGE_VALID); 1343 i_sw(p, pte, sizeof(pte_t) / 2, ptr); 1344 i_lw(p, pte, 0, ptr); 1345 } 1346 # endif 1347 #endif 1348 } 1349 1350 /* 1351 * Check if PTE is present, if not then jump to LABEL. PTR points to 1352 * the page table where this PTE is located, PTE will be re-loaded 1353 * with it's original value. 1354 */ 1355 static void __init 1356 build_pte_present(u32 **p, struct label **l, struct reloc **r, 1357 unsigned int pte, unsigned int ptr, enum label_id lid) 1358 { 1359 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 1360 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 1361 il_bnez(p, r, pte, lid); 1362 iPTE_LW(p, l, pte, 0, ptr); 1363 } 1364 1365 /* Make PTE valid, store result in PTR. */ 1366 static void __init 1367 build_make_valid(u32 **p, struct reloc **r, unsigned int pte, 1368 unsigned int ptr) 1369 { 1370 i_ori(p, pte, pte, _PAGE_VALID | _PAGE_ACCESSED); 1371 iPTE_SW(p, r, pte, 0, ptr); 1372 } 1373 1374 /* 1375 * Check if PTE can be written to, if not branch to LABEL. Regardless 1376 * restore PTE with value from PTR when done. 1377 */ 1378 static void __init 1379 build_pte_writable(u32 **p, struct label **l, struct reloc **r, 1380 unsigned int pte, unsigned int ptr, enum label_id lid) 1381 { 1382 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 1383 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 1384 il_bnez(p, r, pte, lid); 1385 iPTE_LW(p, l, pte, 0, ptr); 1386 } 1387 1388 /* Make PTE writable, update software status bits as well, then store 1389 * at PTR. 1390 */ 1391 static void __init 1392 build_make_write(u32 **p, struct reloc **r, unsigned int pte, 1393 unsigned int ptr) 1394 { 1395 i_ori(p, pte, pte, 1396 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 1397 iPTE_SW(p, r, pte, 0, ptr); 1398 } 1399 1400 /* 1401 * Check if PTE can be modified, if not branch to LABEL. Regardless 1402 * restore PTE with value from PTR when done. 1403 */ 1404 static void __init 1405 build_pte_modifiable(u32 **p, struct label **l, struct reloc **r, 1406 unsigned int pte, unsigned int ptr, enum label_id lid) 1407 { 1408 i_andi(p, pte, pte, _PAGE_WRITE); 1409 il_beqz(p, r, pte, lid); 1410 iPTE_LW(p, l, pte, 0, ptr); 1411 } 1412 1413 /* 1414 * R3000 style TLB load/store/modify handlers. 1415 */ 1416 1417 /* This places the pte in the page table at PTR into ENTRYLO0. */ 1418 static void __init 1419 build_r3000_pte_reload(u32 **p, unsigned int ptr) 1420 { 1421 i_lw(p, ptr, 0, ptr); 1422 i_nop(p); /* load delay */ 1423 i_mtc0(p, ptr, C0_ENTRYLO0); 1424 i_nop(p); /* cp0 delay */ 1425 } 1426 1427 /* 1428 * The index register may have the probe fail bit set, 1429 * because we would trap on access kseg2, i.e. without refill. 1430 */ 1431 static void __init 1432 build_r3000_tlb_write(u32 **p, struct label **l, struct reloc **r, 1433 unsigned int tmp) 1434 { 1435 i_mfc0(p, tmp, C0_INDEX); 1436 i_nop(p); /* cp0 delay */ 1437 il_bltz(p, r, tmp, label_r3000_write_probe_fail); 1438 i_nop(p); /* branch delay */ 1439 i_tlbwi(p); 1440 il_b(p, r, label_r3000_write_probe_ok); 1441 i_nop(p); /* branch delay */ 1442 l_r3000_write_probe_fail(l, *p); 1443 i_tlbwr(p); 1444 l_r3000_write_probe_ok(l, *p); 1445 } 1446 1447 static void __init 1448 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, 1449 unsigned int ptr) 1450 { 1451 long pgdc = (long)pgd_current; 1452 1453 i_mfc0(p, pte, C0_BADVADDR); 1454 i_lui(p, ptr, rel_hi(pgdc)); /* cp0 delay */ 1455 i_lw(p, ptr, rel_lo(pgdc), ptr); 1456 i_srl(p, pte, pte, 22); /* load delay */ 1457 i_sll(p, pte, pte, 2); 1458 i_addu(p, ptr, ptr, pte); 1459 i_mfc0(p, pte, C0_CONTEXT); 1460 i_lw(p, ptr, 0, ptr); /* cp0 delay */ 1461 i_andi(p, pte, pte, 0xffc); /* load delay */ 1462 i_addu(p, ptr, ptr, pte); 1463 i_lw(p, pte, 0, ptr); 1464 i_nop(p); /* load delay */ 1465 i_tlbp(p); 1466 } 1467 1468 static void __init 1469 build_r3000_tlbchange_handler_tail(u32 **p, unsigned int tmp) 1470 { 1471 i_mfc0(p, tmp, C0_EPC); 1472 i_nop(p); /* cp0 delay */ 1473 i_jr(p, tmp); 1474 i_rfe(p); /* branch delay */ 1475 } 1476 1477 static void __init build_r3000_tlb_load_handler(void) 1478 { 1479 u32 *p = handle_tlbl; 1480 struct label *l = labels; 1481 struct reloc *r = relocs; 1482 1483 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1484 memset(labels, 0, sizeof(labels)); 1485 memset(relocs, 0, sizeof(relocs)); 1486 1487 build_r3000_tlbchange_handler_head(&p, K0, K1); 1488 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); 1489 build_make_valid(&p, &r, K0, K1); 1490 build_r3000_pte_reload(&p, K1); 1491 build_r3000_tlb_write(&p, &l, &r, K0); 1492 build_r3000_tlbchange_handler_tail(&p, K0); 1493 1494 l_nopage_tlbl(&l, p); 1495 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1496 i_nop(&p); 1497 1498 if ((p - handle_tlbl) > FASTPATH_SIZE) 1499 panic("TLB load handler fastpath space exceeded"); 1500 1501 resolve_relocs(relocs, labels); 1502 printk("Synthesized TLB load handler fastpath (%u instructions).\n", 1503 (unsigned int)(p - handle_tlbl)); 1504 1505 #ifdef DEBUG_TLB 1506 { 1507 int i; 1508 1509 for (i = 0; i < FASTPATH_SIZE; i++) 1510 printk("%08x\n", handle_tlbl[i]); 1511 } 1512 #endif 1513 1514 flush_icache_range((unsigned long)handle_tlbl, 1515 (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32)); 1516 } 1517 1518 static void __init build_r3000_tlb_store_handler(void) 1519 { 1520 u32 *p = handle_tlbs; 1521 struct label *l = labels; 1522 struct reloc *r = relocs; 1523 1524 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1525 memset(labels, 0, sizeof(labels)); 1526 memset(relocs, 0, sizeof(relocs)); 1527 1528 build_r3000_tlbchange_handler_head(&p, K0, K1); 1529 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); 1530 build_make_write(&p, &r, K0, K1); 1531 build_r3000_pte_reload(&p, K1); 1532 build_r3000_tlb_write(&p, &l, &r, K0); 1533 build_r3000_tlbchange_handler_tail(&p, K0); 1534 1535 l_nopage_tlbs(&l, p); 1536 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1537 i_nop(&p); 1538 1539 if ((p - handle_tlbs) > FASTPATH_SIZE) 1540 panic("TLB store handler fastpath space exceeded"); 1541 1542 resolve_relocs(relocs, labels); 1543 printk("Synthesized TLB store handler fastpath (%u instructions).\n", 1544 (unsigned int)(p - handle_tlbs)); 1545 1546 #ifdef DEBUG_TLB 1547 { 1548 int i; 1549 1550 for (i = 0; i < FASTPATH_SIZE; i++) 1551 printk("%08x\n", handle_tlbs[i]); 1552 } 1553 #endif 1554 1555 flush_icache_range((unsigned long)handle_tlbs, 1556 (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32)); 1557 } 1558 1559 static void __init build_r3000_tlb_modify_handler(void) 1560 { 1561 u32 *p = handle_tlbm; 1562 struct label *l = labels; 1563 struct reloc *r = relocs; 1564 1565 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1566 memset(labels, 0, sizeof(labels)); 1567 memset(relocs, 0, sizeof(relocs)); 1568 1569 build_r3000_tlbchange_handler_head(&p, K0, K1); 1570 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); 1571 build_make_write(&p, &r, K0, K1); 1572 build_r3000_pte_reload(&p, K1); 1573 i_tlbwi(&p); 1574 build_r3000_tlbchange_handler_tail(&p, K0); 1575 1576 l_nopage_tlbm(&l, p); 1577 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1578 i_nop(&p); 1579 1580 if ((p - handle_tlbm) > FASTPATH_SIZE) 1581 panic("TLB modify handler fastpath space exceeded"); 1582 1583 resolve_relocs(relocs, labels); 1584 printk("Synthesized TLB modify handler fastpath (%u instructions).\n", 1585 (unsigned int)(p - handle_tlbm)); 1586 1587 #ifdef DEBUG_TLB 1588 { 1589 int i; 1590 1591 for (i = 0; i < FASTPATH_SIZE; i++) 1592 printk("%08x\n", handle_tlbm[i]); 1593 } 1594 #endif 1595 1596 flush_icache_range((unsigned long)handle_tlbm, 1597 (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32)); 1598 } 1599 1600 /* 1601 * R4000 style TLB load/store/modify handlers. 1602 */ 1603 static void __init 1604 build_r4000_tlbchange_handler_head(u32 **p, struct label **l, 1605 struct reloc **r, unsigned int pte, 1606 unsigned int ptr) 1607 { 1608 #ifdef CONFIG_MIPS64 1609 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ 1610 #else 1611 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ 1612 #endif 1613 1614 i_MFC0(p, pte, C0_BADVADDR); 1615 i_LW(p, ptr, 0, ptr); 1616 i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); 1617 i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2); 1618 i_ADDU(p, ptr, ptr, pte); 1619 1620 #ifdef CONFIG_SMP 1621 l_smp_pgtable_change(l, *p); 1622 # endif 1623 iPTE_LW(p, l, pte, 0, ptr); /* get even pte */ 1624 build_tlb_probe_entry(p); 1625 } 1626 1627 static void __init 1628 build_r4000_tlbchange_handler_tail(u32 **p, struct label **l, 1629 struct reloc **r, unsigned int tmp, 1630 unsigned int ptr) 1631 { 1632 i_ori(p, ptr, ptr, sizeof(pte_t)); 1633 i_xori(p, ptr, ptr, sizeof(pte_t)); 1634 build_update_entries(p, tmp, ptr); 1635 build_tlb_write_entry(p, l, r, tlb_indexed); 1636 l_leave(l, *p); 1637 i_eret(p); /* return from trap */ 1638 1639 #ifdef CONFIG_MIPS64 1640 build_get_pgd_vmalloc64(p, l, r, tmp, ptr); 1641 #endif 1642 } 1643 1644 static void __init build_r4000_tlb_load_handler(void) 1645 { 1646 u32 *p = handle_tlbl; 1647 struct label *l = labels; 1648 struct reloc *r = relocs; 1649 1650 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1651 memset(labels, 0, sizeof(labels)); 1652 memset(relocs, 0, sizeof(relocs)); 1653 1654 if (bcm1250_m3_war()) { 1655 i_MFC0(&p, K0, C0_BADVADDR); 1656 i_MFC0(&p, K1, C0_ENTRYHI); 1657 i_xor(&p, K0, K0, K1); 1658 i_SRL(&p, K0, K0, PAGE_SHIFT + 1); 1659 il_bnez(&p, &r, K0, label_leave); 1660 /* No need for i_nop */ 1661 } 1662 1663 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1664 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); 1665 build_make_valid(&p, &r, K0, K1); 1666 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1667 1668 l_nopage_tlbl(&l, p); 1669 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1670 i_nop(&p); 1671 1672 if ((p - handle_tlbl) > FASTPATH_SIZE) 1673 panic("TLB load handler fastpath space exceeded"); 1674 1675 resolve_relocs(relocs, labels); 1676 printk("Synthesized TLB load handler fastpath (%u instructions).\n", 1677 (unsigned int)(p - handle_tlbl)); 1678 1679 #ifdef DEBUG_TLB 1680 { 1681 int i; 1682 1683 for (i = 0; i < FASTPATH_SIZE; i++) 1684 printk("%08x\n", handle_tlbl[i]); 1685 } 1686 #endif 1687 1688 flush_icache_range((unsigned long)handle_tlbl, 1689 (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32)); 1690 } 1691 1692 static void __init build_r4000_tlb_store_handler(void) 1693 { 1694 u32 *p = handle_tlbs; 1695 struct label *l = labels; 1696 struct reloc *r = relocs; 1697 1698 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1699 memset(labels, 0, sizeof(labels)); 1700 memset(relocs, 0, sizeof(relocs)); 1701 1702 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1703 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); 1704 build_make_write(&p, &r, K0, K1); 1705 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1706 1707 l_nopage_tlbs(&l, p); 1708 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1709 i_nop(&p); 1710 1711 if ((p - handle_tlbs) > FASTPATH_SIZE) 1712 panic("TLB store handler fastpath space exceeded"); 1713 1714 resolve_relocs(relocs, labels); 1715 printk("Synthesized TLB store handler fastpath (%u instructions).\n", 1716 (unsigned int)(p - handle_tlbs)); 1717 1718 #ifdef DEBUG_TLB 1719 { 1720 int i; 1721 1722 for (i = 0; i < FASTPATH_SIZE; i++) 1723 printk("%08x\n", handle_tlbs[i]); 1724 } 1725 #endif 1726 1727 flush_icache_range((unsigned long)handle_tlbs, 1728 (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32)); 1729 } 1730 1731 static void __init build_r4000_tlb_modify_handler(void) 1732 { 1733 u32 *p = handle_tlbm; 1734 struct label *l = labels; 1735 struct reloc *r = relocs; 1736 1737 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1738 memset(labels, 0, sizeof(labels)); 1739 memset(relocs, 0, sizeof(relocs)); 1740 1741 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1742 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); 1743 /* Present and writable bits set, set accessed and dirty bits. */ 1744 build_make_write(&p, &r, K0, K1); 1745 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1746 1747 l_nopage_tlbm(&l, p); 1748 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1749 i_nop(&p); 1750 1751 if ((p - handle_tlbm) > FASTPATH_SIZE) 1752 panic("TLB modify handler fastpath space exceeded"); 1753 1754 resolve_relocs(relocs, labels); 1755 printk("Synthesized TLB modify handler fastpath (%u instructions).\n", 1756 (unsigned int)(p - handle_tlbm)); 1757 1758 #ifdef DEBUG_TLB 1759 { 1760 int i; 1761 1762 for (i = 0; i < FASTPATH_SIZE; i++) 1763 printk("%08x\n", handle_tlbm[i]); 1764 } 1765 #endif 1766 1767 flush_icache_range((unsigned long)handle_tlbm, 1768 (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32)); 1769 } 1770 1771 void __init build_tlb_refill_handler(void) 1772 { 1773 /* 1774 * The refill handler is generated per-CPU, multi-node systems 1775 * may have local storage for it. The other handlers are only 1776 * needed once. 1777 */ 1778 static int run_once = 0; 1779 1780 switch (current_cpu_data.cputype) { 1781 case CPU_R2000: 1782 case CPU_R3000: 1783 case CPU_R3000A: 1784 case CPU_R3081E: 1785 case CPU_TX3912: 1786 case CPU_TX3922: 1787 case CPU_TX3927: 1788 build_r3000_tlb_refill_handler(); 1789 if (!run_once) { 1790 build_r3000_tlb_load_handler(); 1791 build_r3000_tlb_store_handler(); 1792 build_r3000_tlb_modify_handler(); 1793 run_once++; 1794 } 1795 break; 1796 1797 case CPU_R6000: 1798 case CPU_R6000A: 1799 panic("No R6000 TLB refill handler yet"); 1800 break; 1801 1802 case CPU_R8000: 1803 panic("No R8000 TLB refill handler yet"); 1804 break; 1805 1806 default: 1807 build_r4000_tlb_refill_handler(); 1808 if (!run_once) { 1809 build_r4000_tlb_load_handler(); 1810 build_r4000_tlb_store_handler(); 1811 build_r4000_tlb_modify_handler(); 1812 run_once++; 1813 } 1814 } 1815 } 1816