1 #include <linux/compiler.h> 2 #include <linux/mm.h> 3 #include <linux/signal.h> 4 #include <linux/smp.h> 5 #include <linux/smp_lock.h> 6 7 #include <asm/asm.h> 8 #include <asm/bootinfo.h> 9 #include <asm/byteorder.h> 10 #include <asm/cpu.h> 11 #include <asm/inst.h> 12 #include <asm/processor.h> 13 #include <asm/uaccess.h> 14 #include <asm/branch.h> 15 #include <asm/mipsregs.h> 16 #include <asm/system.h> 17 #include <asm/cacheflush.h> 18 19 #include <asm/fpu_emulator.h> 20 21 #include "ieee754.h" 22 #include "dsemul.h" 23 24 /* Strap kernel emulator for full MIPS IV emulation */ 25 26 #ifdef __mips 27 #undef __mips 28 #endif 29 #define __mips 4 30 31 extern struct mips_fpu_emulator_private fpuemuprivate; 32 33 34 /* 35 * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when 36 * we have to emulate the instruction in a COP1 branch delay slot. Do 37 * not change cp0_epc due to the instruction 38 * 39 * According to the spec: 40 * 1) it shouldnt be a branch :-) 41 * 2) it can be a COP instruction :-( 42 * 3) if we are tring to run a protected memory space we must take 43 * special care on memory access instructions :-( 44 */ 45 46 /* 47 * "Trampoline" return routine to catch exception following 48 * execution of delay-slot instruction execution. 49 */ 50 51 struct emuframe { 52 mips_instruction emul; 53 mips_instruction badinst; 54 mips_instruction cookie; 55 gpreg_t epc; 56 }; 57 58 int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc) 59 { 60 extern asmlinkage void handle_dsemulret(void); 61 mips_instruction *dsemul_insns; 62 struct emuframe *fr; 63 int err; 64 65 if (ir == 0) { /* a nop is easy */ 66 regs->cp0_epc = cpc; 67 regs->cp0_cause &= ~CAUSEF_BD; 68 return 0; 69 } 70 #ifdef DSEMUL_TRACE 71 printk("dsemul %lx %lx\n", regs->cp0_epc, cpc); 72 73 #endif 74 75 /* 76 * The strategy is to push the instruction onto the user stack 77 * and put a trap after it which we can catch and jump to 78 * the required address any alternative apart from full 79 * instruction emulation!!. 80 * 81 * Algorithmics used a system call instruction, and 82 * borrowed that vector. MIPS/Linux version is a bit 83 * more heavyweight in the interests of portability and 84 * multiprocessor support. For Linux we generate a 85 * an unaligned access and force an address error exception. 86 * 87 * For embedded systems (stand-alone) we prefer to use a 88 * non-existing CP1 instruction. This prevents us from emulating 89 * branches, but gives us a cleaner interface to the exception 90 * handler (single entry point). 91 */ 92 93 /* Ensure that the two instructions are in the same cache line */ 94 dsemul_insns = (mips_instruction *) REG_TO_VA ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7); 95 fr = (struct emuframe *) dsemul_insns; 96 97 /* Verify that the stack pointer is not competely insane */ 98 if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe)))) 99 return SIGBUS; 100 101 err = __put_user(ir, &fr->emul); 102 err |= __put_user((mips_instruction)BADINST, &fr->badinst); 103 err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie); 104 err |= __put_user(cpc, &fr->epc); 105 106 if (unlikely(err)) { 107 fpuemuprivate.stats.errors++; 108 return SIGBUS; 109 } 110 111 regs->cp0_epc = VA_TO_REG & fr->emul; 112 113 flush_cache_sigtramp((unsigned long)&fr->badinst); 114 115 return SIGILL; /* force out of emulation loop */ 116 } 117 118 int do_dsemulret(struct pt_regs *xcp) 119 { 120 struct emuframe *fr; 121 gpreg_t epc; 122 u32 insn, cookie; 123 int err = 0; 124 125 fr = (struct emuframe *) (xcp->cp0_epc - sizeof(mips_instruction)); 126 127 /* 128 * If we can't even access the area, something is very wrong, but we'll 129 * leave that to the default handling 130 */ 131 if (!access_ok(VERIFY_READ, fr, sizeof(struct emuframe))) 132 return 0; 133 134 /* 135 * Do some sanity checking on the stackframe: 136 * 137 * - Is the instruction pointed to by the EPC an BADINST? 138 * - Is the following memory word the BD_COOKIE? 139 */ 140 err = __get_user(insn, &fr->badinst); 141 err |= __get_user(cookie, &fr->cookie); 142 143 if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) { 144 fpuemuprivate.stats.errors++; 145 return 0; 146 } 147 148 /* 149 * At this point, we are satisfied that it's a BD emulation trap. Yes, 150 * a user might have deliberately put two malformed and useless 151 * instructions in a row in his program, in which case he's in for a 152 * nasty surprise - the next instruction will be treated as a 153 * continuation address! Alas, this seems to be the only way that we 154 * can handle signals, recursion, and longjmps() in the context of 155 * emulating the branch delay instruction. 156 */ 157 158 #ifdef DSEMUL_TRACE 159 printk("dsemulret\n"); 160 #endif 161 if (__get_user(epc, &fr->epc)) { /* Saved EPC */ 162 /* This is not a good situation to be in */ 163 force_sig(SIGBUS, current); 164 165 return 0; 166 } 167 168 /* Set EPC to return to post-branch instruction */ 169 xcp->cp0_epc = epc; 170 171 return 1; 172 } 173