1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Copyright (C) 2010 John Crispin <john@phrozen.org> 7 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com> 8 */ 9 10 #include <linux/interrupt.h> 11 #include <linux/ioport.h> 12 #include <linux/sched.h> 13 #include <linux/irqdomain.h> 14 #include <linux/of_platform.h> 15 #include <linux/of_address.h> 16 #include <linux/of_irq.h> 17 18 #include <asm/bootinfo.h> 19 #include <asm/irq_cpu.h> 20 21 #include <lantiq_soc.h> 22 #include <irq.h> 23 24 /* register definitions - internal irqs */ 25 #define LTQ_ICU_IM0_ISR 0x0000 26 #define LTQ_ICU_IM0_IER 0x0008 27 #define LTQ_ICU_IM0_IOSR 0x0010 28 #define LTQ_ICU_IM0_IRSR 0x0018 29 #define LTQ_ICU_IM0_IMR 0x0020 30 #define LTQ_ICU_IM1_ISR 0x0028 31 #define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR) 32 33 /* register definitions - external irqs */ 34 #define LTQ_EIU_EXIN_C 0x0000 35 #define LTQ_EIU_EXIN_INIC 0x0004 36 #define LTQ_EIU_EXIN_INC 0x0008 37 #define LTQ_EIU_EXIN_INEN 0x000C 38 39 /* number of external interrupts */ 40 #define MAX_EIU 6 41 42 /* the performance counter */ 43 #define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31) 44 45 /* 46 * irqs generated by devices attached to the EBU need to be acked in 47 * a special manner 48 */ 49 #define LTQ_ICU_EBU_IRQ 22 50 51 #define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y)) 52 #define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x)) 53 54 #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y)) 55 #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x)) 56 57 /* we have a cascade of 8 irqs */ 58 #define MIPS_CPU_IRQ_CASCADE 8 59 60 static int exin_avail; 61 static u32 ltq_eiu_irq[MAX_EIU]; 62 static void __iomem *ltq_icu_membase[MAX_IM]; 63 static void __iomem *ltq_eiu_membase; 64 static struct irq_domain *ltq_domain; 65 static int ltq_perfcount_irq; 66 67 int ltq_eiu_get_irq(int exin) 68 { 69 if (exin < exin_avail) 70 return ltq_eiu_irq[exin]; 71 return -1; 72 } 73 74 void ltq_disable_irq(struct irq_data *d) 75 { 76 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; 77 unsigned long im = offset / INT_NUM_IM_OFFSET; 78 79 offset %= INT_NUM_IM_OFFSET; 80 ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) & ~BIT(offset), 81 LTQ_ICU_IM0_IER); 82 } 83 84 void ltq_mask_and_ack_irq(struct irq_data *d) 85 { 86 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; 87 unsigned long im = offset / INT_NUM_IM_OFFSET; 88 89 offset %= INT_NUM_IM_OFFSET; 90 ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) & ~BIT(offset), 91 LTQ_ICU_IM0_IER); 92 ltq_icu_w32(im, BIT(offset), LTQ_ICU_IM0_ISR); 93 } 94 95 static void ltq_ack_irq(struct irq_data *d) 96 { 97 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; 98 unsigned long im = offset / INT_NUM_IM_OFFSET; 99 100 offset %= INT_NUM_IM_OFFSET; 101 ltq_icu_w32(im, BIT(offset), LTQ_ICU_IM0_ISR); 102 } 103 104 void ltq_enable_irq(struct irq_data *d) 105 { 106 unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; 107 unsigned long im = offset / INT_NUM_IM_OFFSET; 108 109 offset %= INT_NUM_IM_OFFSET; 110 ltq_icu_w32(im, ltq_icu_r32(im, LTQ_ICU_IM0_IER) | BIT(offset), 111 LTQ_ICU_IM0_IER); 112 } 113 114 static int ltq_eiu_settype(struct irq_data *d, unsigned int type) 115 { 116 int i; 117 118 for (i = 0; i < exin_avail; i++) { 119 if (d->hwirq == ltq_eiu_irq[i]) { 120 int val = 0; 121 int edge = 0; 122 123 switch (type) { 124 case IRQF_TRIGGER_NONE: 125 break; 126 case IRQF_TRIGGER_RISING: 127 val = 1; 128 edge = 1; 129 break; 130 case IRQF_TRIGGER_FALLING: 131 val = 2; 132 edge = 1; 133 break; 134 case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING: 135 val = 3; 136 edge = 1; 137 break; 138 case IRQF_TRIGGER_HIGH: 139 val = 5; 140 break; 141 case IRQF_TRIGGER_LOW: 142 val = 6; 143 break; 144 default: 145 pr_err("invalid type %d for irq %ld\n", 146 type, d->hwirq); 147 return -EINVAL; 148 } 149 150 if (edge) 151 irq_set_handler(d->hwirq, handle_edge_irq); 152 153 ltq_eiu_w32((ltq_eiu_r32(LTQ_EIU_EXIN_C) & 154 (~(7 << (i * 4)))) | (val << (i * 4)), 155 LTQ_EIU_EXIN_C); 156 } 157 } 158 159 return 0; 160 } 161 162 static unsigned int ltq_startup_eiu_irq(struct irq_data *d) 163 { 164 int i; 165 166 ltq_enable_irq(d); 167 for (i = 0; i < exin_avail; i++) { 168 if (d->hwirq == ltq_eiu_irq[i]) { 169 /* by default we are low level triggered */ 170 ltq_eiu_settype(d, IRQF_TRIGGER_LOW); 171 /* clear all pending */ 172 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i), 173 LTQ_EIU_EXIN_INC); 174 /* enable */ 175 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i), 176 LTQ_EIU_EXIN_INEN); 177 break; 178 } 179 } 180 181 return 0; 182 } 183 184 static void ltq_shutdown_eiu_irq(struct irq_data *d) 185 { 186 int i; 187 188 ltq_disable_irq(d); 189 for (i = 0; i < exin_avail; i++) { 190 if (d->hwirq == ltq_eiu_irq[i]) { 191 /* disable */ 192 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i), 193 LTQ_EIU_EXIN_INEN); 194 break; 195 } 196 } 197 } 198 199 static struct irq_chip ltq_irq_type = { 200 .name = "icu", 201 .irq_enable = ltq_enable_irq, 202 .irq_disable = ltq_disable_irq, 203 .irq_unmask = ltq_enable_irq, 204 .irq_ack = ltq_ack_irq, 205 .irq_mask = ltq_disable_irq, 206 .irq_mask_ack = ltq_mask_and_ack_irq, 207 }; 208 209 static struct irq_chip ltq_eiu_type = { 210 .name = "eiu", 211 .irq_startup = ltq_startup_eiu_irq, 212 .irq_shutdown = ltq_shutdown_eiu_irq, 213 .irq_enable = ltq_enable_irq, 214 .irq_disable = ltq_disable_irq, 215 .irq_unmask = ltq_enable_irq, 216 .irq_ack = ltq_ack_irq, 217 .irq_mask = ltq_disable_irq, 218 .irq_mask_ack = ltq_mask_and_ack_irq, 219 .irq_set_type = ltq_eiu_settype, 220 }; 221 222 static void ltq_hw_irq_handler(struct irq_desc *desc) 223 { 224 unsigned int module = irq_desc_get_irq(desc) - 2; 225 u32 irq; 226 irq_hw_number_t hwirq; 227 228 irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR); 229 if (irq == 0) 230 return; 231 232 /* 233 * silicon bug causes only the msb set to 1 to be valid. all 234 * other bits might be bogus 235 */ 236 irq = __fls(irq); 237 hwirq = irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module); 238 generic_handle_irq(irq_linear_revmap(ltq_domain, hwirq)); 239 240 /* if this is a EBU irq, we need to ack it or get a deadlock */ 241 if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT) 242 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, 243 LTQ_EBU_PCC_ISTAT); 244 } 245 246 static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) 247 { 248 struct irq_chip *chip = <q_irq_type; 249 int i; 250 251 if (hw < MIPS_CPU_IRQ_CASCADE) 252 return 0; 253 254 for (i = 0; i < exin_avail; i++) 255 if (hw == ltq_eiu_irq[i]) 256 chip = <q_eiu_type; 257 258 irq_set_chip_and_handler(irq, chip, handle_level_irq); 259 260 return 0; 261 } 262 263 static const struct irq_domain_ops irq_domain_ops = { 264 .xlate = irq_domain_xlate_onetwocell, 265 .map = icu_map, 266 }; 267 268 int __init icu_of_init(struct device_node *node, struct device_node *parent) 269 { 270 struct device_node *eiu_node; 271 struct resource res; 272 int i, ret; 273 274 for (i = 0; i < MAX_IM; i++) { 275 if (of_address_to_resource(node, i, &res)) 276 panic("Failed to get icu memory range"); 277 278 if (!request_mem_region(res.start, resource_size(&res), 279 res.name)) 280 pr_err("Failed to request icu memory"); 281 282 ltq_icu_membase[i] = ioremap_nocache(res.start, 283 resource_size(&res)); 284 if (!ltq_icu_membase[i]) 285 panic("Failed to remap icu memory"); 286 } 287 288 /* turn off all irqs by default */ 289 for (i = 0; i < MAX_IM; i++) { 290 /* make sure all irqs are turned off by default */ 291 ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER); 292 /* clear all possibly pending interrupts */ 293 ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR); 294 } 295 296 mips_cpu_irq_init(); 297 298 for (i = 0; i < MAX_IM; i++) 299 irq_set_chained_handler(i + 2, ltq_hw_irq_handler); 300 301 ltq_domain = irq_domain_add_linear(node, 302 (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE, 303 &irq_domain_ops, 0); 304 305 /* tell oprofile which irq to use */ 306 ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ); 307 308 /* the external interrupts are optional and xway only */ 309 eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway"); 310 if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) { 311 /* find out how many external irq sources we have */ 312 exin_avail = of_property_count_u32_elems(eiu_node, 313 "lantiq,eiu-irqs"); 314 315 if (exin_avail > MAX_EIU) 316 exin_avail = MAX_EIU; 317 318 ret = of_property_read_u32_array(eiu_node, "lantiq,eiu-irqs", 319 ltq_eiu_irq, exin_avail); 320 if (ret) 321 panic("failed to load external irq resources"); 322 323 if (!request_mem_region(res.start, resource_size(&res), 324 res.name)) 325 pr_err("Failed to request eiu memory"); 326 327 ltq_eiu_membase = ioremap_nocache(res.start, 328 resource_size(&res)); 329 if (!ltq_eiu_membase) 330 panic("Failed to remap eiu memory"); 331 } 332 333 return 0; 334 } 335 336 int get_c0_perfcount_int(void) 337 { 338 return ltq_perfcount_irq; 339 } 340 EXPORT_SYMBOL_GPL(get_c0_perfcount_int); 341 342 unsigned int get_c0_compare_int(void) 343 { 344 return CP0_LEGACY_COMPARE_IRQ; 345 } 346 347 static const struct of_device_id of_irq_ids[] __initconst = { 348 { .compatible = "lantiq,icu", .data = icu_of_init }, 349 {}, 350 }; 351 352 void __init arch_init_irq(void) 353 { 354 of_irq_init(of_irq_ids); 355 } 356