1*d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2d41ced01SJohn Crispin /* 3d41ced01SJohn Crispin * 4d41ced01SJohn Crispin * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com> 597b92108SJohn Crispin * Copyright (C) 2012 John Crispin <john@phrozen.org> 6d41ced01SJohn Crispin */ 7d41ced01SJohn Crispin 8d41ced01SJohn Crispin #include <linux/init.h> 9d41ced01SJohn Crispin #include <linux/io.h> 10d41ced01SJohn Crispin #include <linux/pm.h> 11d41ced01SJohn Crispin #include <asm/reboot.h> 12d41ced01SJohn Crispin #include <linux/export.h> 13d41ced01SJohn Crispin 14d41ced01SJohn Crispin #include <lantiq_soc.h> 15d41ced01SJohn Crispin 164dcfadb1SRalf Baechle /* 174dcfadb1SRalf Baechle * Dummy implementation. Used to allow platform code to find out what 184dcfadb1SRalf Baechle * source was booted from 194dcfadb1SRalf Baechle */ ltq_boot_select(void)20d41ced01SJohn Crispinunsigned char ltq_boot_select(void) 21d41ced01SJohn Crispin { 224dcfadb1SRalf Baechle return BS_SPI; 23d41ced01SJohn Crispin } 24d41ced01SJohn Crispin 25d41ced01SJohn Crispin #define BOOT_REG_BASE (KSEG1 | 0x1F200000) 26d41ced01SJohn Crispin #define BOOT_PW1_REG (BOOT_REG_BASE | 0x20) 27d41ced01SJohn Crispin #define BOOT_PW2_REG (BOOT_REG_BASE | 0x24) 28d41ced01SJohn Crispin #define BOOT_PW1 0x4C545100 29d41ced01SJohn Crispin #define BOOT_PW2 0x0051544C 30d41ced01SJohn Crispin 31d41ced01SJohn Crispin #define WDT_REG_BASE (KSEG1 | 0x1F8803F0) 32d41ced01SJohn Crispin #define WDT_PW1 0x00BE0000 33d41ced01SJohn Crispin #define WDT_PW2 0x00DC0000 34d41ced01SJohn Crispin machine_restart(char * command)35d41ced01SJohn Crispinstatic void machine_restart(char *command) 36d41ced01SJohn Crispin { 37d41ced01SJohn Crispin local_irq_disable(); 38d41ced01SJohn Crispin 39d41ced01SJohn Crispin /* reboot magic */ 40d41ced01SJohn Crispin ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */ 41d41ced01SJohn Crispin ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */ 42d41ced01SJohn Crispin ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */ 43d41ced01SJohn Crispin 44d41ced01SJohn Crispin /* watchdog magic */ 45d41ced01SJohn Crispin ltq_w32(WDT_PW1, (void *)WDT_REG_BASE); 46d41ced01SJohn Crispin ltq_w32(WDT_PW2 | 47d41ced01SJohn Crispin (0x3 << 26) | /* PWL */ 48d41ced01SJohn Crispin (0x2 << 24) | /* CLKDIV */ 49d41ced01SJohn Crispin (0x1 << 31) | /* enable */ 50d41ced01SJohn Crispin (1), /* reload */ 51d41ced01SJohn Crispin (void *)WDT_REG_BASE); 52d41ced01SJohn Crispin unreachable(); 53d41ced01SJohn Crispin } 54d41ced01SJohn Crispin machine_halt(void)55d41ced01SJohn Crispinstatic void machine_halt(void) 56d41ced01SJohn Crispin { 57d41ced01SJohn Crispin local_irq_disable(); 58d41ced01SJohn Crispin unreachable(); 59d41ced01SJohn Crispin } 60d41ced01SJohn Crispin machine_power_off(void)61d41ced01SJohn Crispinstatic void machine_power_off(void) 62d41ced01SJohn Crispin { 63d41ced01SJohn Crispin local_irq_disable(); 64d41ced01SJohn Crispin unreachable(); 65d41ced01SJohn Crispin } 66d41ced01SJohn Crispin mips_reboot_setup(void)67d41ced01SJohn Crispinstatic int __init mips_reboot_setup(void) 68d41ced01SJohn Crispin { 69d41ced01SJohn Crispin _machine_restart = machine_restart; 70d41ced01SJohn Crispin _machine_halt = machine_halt; 71d41ced01SJohn Crispin pm_power_off = machine_power_off; 72d41ced01SJohn Crispin return 0; 73d41ced01SJohn Crispin } 74d41ced01SJohn Crispin 75d41ced01SJohn Crispin arch_initcall(mips_reboot_setup); 76