1*d7d5b05fSDeng-Cheng Zhu /* 2*d7d5b05fSDeng-Cheng Zhu * This file is subject to the terms and conditions of the GNU General Public 3*d7d5b05fSDeng-Cheng Zhu * License. See the file "COPYING" in the main directory of this archive 4*d7d5b05fSDeng-Cheng Zhu * for more details. 5*d7d5b05fSDeng-Cheng Zhu * 6*d7d5b05fSDeng-Cheng Zhu * KVM/MIPS: COP0 access histogram 7*d7d5b05fSDeng-Cheng Zhu * 8*d7d5b05fSDeng-Cheng Zhu * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 9*d7d5b05fSDeng-Cheng Zhu * Authors: Sanjay Lal <sanjayl@kymasys.com> 10*d7d5b05fSDeng-Cheng Zhu */ 11*d7d5b05fSDeng-Cheng Zhu 12*d7d5b05fSDeng-Cheng Zhu #include <linux/kvm_host.h> 13*d7d5b05fSDeng-Cheng Zhu 14*d7d5b05fSDeng-Cheng Zhu char *kvm_mips_exit_types_str[MAX_KVM_MIPS_EXIT_TYPES] = { 15*d7d5b05fSDeng-Cheng Zhu "WAIT", 16*d7d5b05fSDeng-Cheng Zhu "CACHE", 17*d7d5b05fSDeng-Cheng Zhu "Signal", 18*d7d5b05fSDeng-Cheng Zhu "Interrupt", 19*d7d5b05fSDeng-Cheng Zhu "COP0/1 Unusable", 20*d7d5b05fSDeng-Cheng Zhu "TLB Mod", 21*d7d5b05fSDeng-Cheng Zhu "TLB Miss (LD)", 22*d7d5b05fSDeng-Cheng Zhu "TLB Miss (ST)", 23*d7d5b05fSDeng-Cheng Zhu "Address Err (ST)", 24*d7d5b05fSDeng-Cheng Zhu "Address Error (LD)", 25*d7d5b05fSDeng-Cheng Zhu "System Call", 26*d7d5b05fSDeng-Cheng Zhu "Reserved Inst", 27*d7d5b05fSDeng-Cheng Zhu "Break Inst", 28*d7d5b05fSDeng-Cheng Zhu "D-Cache Flushes", 29*d7d5b05fSDeng-Cheng Zhu }; 30*d7d5b05fSDeng-Cheng Zhu 31*d7d5b05fSDeng-Cheng Zhu char *kvm_cop0_str[N_MIPS_COPROC_REGS] = { 32*d7d5b05fSDeng-Cheng Zhu "Index", 33*d7d5b05fSDeng-Cheng Zhu "Random", 34*d7d5b05fSDeng-Cheng Zhu "EntryLo0", 35*d7d5b05fSDeng-Cheng Zhu "EntryLo1", 36*d7d5b05fSDeng-Cheng Zhu "Context", 37*d7d5b05fSDeng-Cheng Zhu "PG Mask", 38*d7d5b05fSDeng-Cheng Zhu "Wired", 39*d7d5b05fSDeng-Cheng Zhu "HWREna", 40*d7d5b05fSDeng-Cheng Zhu "BadVAddr", 41*d7d5b05fSDeng-Cheng Zhu "Count", 42*d7d5b05fSDeng-Cheng Zhu "EntryHI", 43*d7d5b05fSDeng-Cheng Zhu "Compare", 44*d7d5b05fSDeng-Cheng Zhu "Status", 45*d7d5b05fSDeng-Cheng Zhu "Cause", 46*d7d5b05fSDeng-Cheng Zhu "EXC PC", 47*d7d5b05fSDeng-Cheng Zhu "PRID", 48*d7d5b05fSDeng-Cheng Zhu "Config", 49*d7d5b05fSDeng-Cheng Zhu "LLAddr", 50*d7d5b05fSDeng-Cheng Zhu "Watch Lo", 51*d7d5b05fSDeng-Cheng Zhu "Watch Hi", 52*d7d5b05fSDeng-Cheng Zhu "X Context", 53*d7d5b05fSDeng-Cheng Zhu "Reserved", 54*d7d5b05fSDeng-Cheng Zhu "Impl Dep", 55*d7d5b05fSDeng-Cheng Zhu "Debug", 56*d7d5b05fSDeng-Cheng Zhu "DEPC", 57*d7d5b05fSDeng-Cheng Zhu "PerfCnt", 58*d7d5b05fSDeng-Cheng Zhu "ErrCtl", 59*d7d5b05fSDeng-Cheng Zhu "CacheErr", 60*d7d5b05fSDeng-Cheng Zhu "TagLo", 61*d7d5b05fSDeng-Cheng Zhu "TagHi", 62*d7d5b05fSDeng-Cheng Zhu "ErrorEPC", 63*d7d5b05fSDeng-Cheng Zhu "DESAVE" 64*d7d5b05fSDeng-Cheng Zhu }; 65*d7d5b05fSDeng-Cheng Zhu 66*d7d5b05fSDeng-Cheng Zhu void kvm_mips_dump_stats(struct kvm_vcpu *vcpu) 67*d7d5b05fSDeng-Cheng Zhu { 68*d7d5b05fSDeng-Cheng Zhu #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS 69*d7d5b05fSDeng-Cheng Zhu int i, j; 70*d7d5b05fSDeng-Cheng Zhu 71*d7d5b05fSDeng-Cheng Zhu kvm_info("\nKVM VCPU[%d] COP0 Access Profile:\n", vcpu->vcpu_id); 72*d7d5b05fSDeng-Cheng Zhu for (i = 0; i < N_MIPS_COPROC_REGS; i++) { 73*d7d5b05fSDeng-Cheng Zhu for (j = 0; j < N_MIPS_COPROC_SEL; j++) { 74*d7d5b05fSDeng-Cheng Zhu if (vcpu->arch.cop0->stat[i][j]) 75*d7d5b05fSDeng-Cheng Zhu kvm_info("%s[%d]: %lu\n", kvm_cop0_str[i], j, 76*d7d5b05fSDeng-Cheng Zhu vcpu->arch.cop0->stat[i][j]); 77*d7d5b05fSDeng-Cheng Zhu } 78*d7d5b05fSDeng-Cheng Zhu } 79*d7d5b05fSDeng-Cheng Zhu #endif 80*d7d5b05fSDeng-Cheng Zhu } 81