1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * KVM/MIPS: MIPS specific KVM APIs 7 * 8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 9 * Authors: Sanjay Lal <sanjayl@kymasys.com> 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/errno.h> 14 #include <linux/err.h> 15 #include <linux/kdebug.h> 16 #include <linux/module.h> 17 #include <linux/uaccess.h> 18 #include <linux/vmalloc.h> 19 #include <linux/sched/signal.h> 20 #include <linux/fs.h> 21 #include <linux/memblock.h> 22 #include <linux/pgtable.h> 23 24 #include <asm/fpu.h> 25 #include <asm/page.h> 26 #include <asm/cacheflush.h> 27 #include <asm/mmu_context.h> 28 #include <asm/pgalloc.h> 29 30 #include <linux/kvm_host.h> 31 32 #include "interrupt.h" 33 34 #define CREATE_TRACE_POINTS 35 #include "trace.h" 36 37 #ifndef VECTORSPACING 38 #define VECTORSPACING 0x100 /* for EI/VI mode */ 39 #endif 40 41 const struct _kvm_stats_desc kvm_vm_stats_desc[] = { 42 KVM_GENERIC_VM_STATS() 43 }; 44 45 const struct kvm_stats_header kvm_vm_stats_header = { 46 .name_size = KVM_STATS_NAME_SIZE, 47 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), 48 .id_offset = sizeof(struct kvm_stats_header), 49 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 50 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 51 sizeof(kvm_vm_stats_desc), 52 }; 53 54 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 55 KVM_GENERIC_VCPU_STATS(), 56 STATS_DESC_COUNTER(VCPU, wait_exits), 57 STATS_DESC_COUNTER(VCPU, cache_exits), 58 STATS_DESC_COUNTER(VCPU, signal_exits), 59 STATS_DESC_COUNTER(VCPU, int_exits), 60 STATS_DESC_COUNTER(VCPU, cop_unusable_exits), 61 STATS_DESC_COUNTER(VCPU, tlbmod_exits), 62 STATS_DESC_COUNTER(VCPU, tlbmiss_ld_exits), 63 STATS_DESC_COUNTER(VCPU, tlbmiss_st_exits), 64 STATS_DESC_COUNTER(VCPU, addrerr_st_exits), 65 STATS_DESC_COUNTER(VCPU, addrerr_ld_exits), 66 STATS_DESC_COUNTER(VCPU, syscall_exits), 67 STATS_DESC_COUNTER(VCPU, resvd_inst_exits), 68 STATS_DESC_COUNTER(VCPU, break_inst_exits), 69 STATS_DESC_COUNTER(VCPU, trap_inst_exits), 70 STATS_DESC_COUNTER(VCPU, msa_fpe_exits), 71 STATS_DESC_COUNTER(VCPU, fpe_exits), 72 STATS_DESC_COUNTER(VCPU, msa_disabled_exits), 73 STATS_DESC_COUNTER(VCPU, flush_dcache_exits), 74 STATS_DESC_COUNTER(VCPU, vz_gpsi_exits), 75 STATS_DESC_COUNTER(VCPU, vz_gsfc_exits), 76 STATS_DESC_COUNTER(VCPU, vz_hc_exits), 77 STATS_DESC_COUNTER(VCPU, vz_grr_exits), 78 STATS_DESC_COUNTER(VCPU, vz_gva_exits), 79 STATS_DESC_COUNTER(VCPU, vz_ghfc_exits), 80 STATS_DESC_COUNTER(VCPU, vz_gpa_exits), 81 STATS_DESC_COUNTER(VCPU, vz_resvd_exits), 82 #ifdef CONFIG_CPU_LOONGSON64 83 STATS_DESC_COUNTER(VCPU, vz_cpucfg_exits), 84 #endif 85 }; 86 87 const struct kvm_stats_header kvm_vcpu_stats_header = { 88 .name_size = KVM_STATS_NAME_SIZE, 89 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 90 .id_offset = sizeof(struct kvm_stats_header), 91 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 92 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 93 sizeof(kvm_vcpu_stats_desc), 94 }; 95 96 bool kvm_trace_guest_mode_change; 97 98 int kvm_guest_mode_change_trace_reg(void) 99 { 100 kvm_trace_guest_mode_change = true; 101 return 0; 102 } 103 104 void kvm_guest_mode_change_trace_unreg(void) 105 { 106 kvm_trace_guest_mode_change = false; 107 } 108 109 /* 110 * XXXKYMA: We are simulatoring a processor that has the WII bit set in 111 * Config7, so we are "runnable" if interrupts are pending 112 */ 113 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 114 { 115 return !!(vcpu->arch.pending_exceptions); 116 } 117 118 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 119 { 120 return false; 121 } 122 123 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 124 { 125 return 1; 126 } 127 128 int kvm_arch_hardware_enable(void) 129 { 130 return kvm_mips_callbacks->hardware_enable(); 131 } 132 133 void kvm_arch_hardware_disable(void) 134 { 135 kvm_mips_callbacks->hardware_disable(); 136 } 137 138 int kvm_arch_check_processor_compat(void *opaque) 139 { 140 return 0; 141 } 142 143 extern void kvm_init_loongson_ipi(struct kvm *kvm); 144 145 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 146 { 147 switch (type) { 148 case KVM_VM_MIPS_AUTO: 149 break; 150 case KVM_VM_MIPS_VZ: 151 break; 152 default: 153 /* Unsupported KVM type */ 154 return -EINVAL; 155 } 156 157 /* Allocate page table to map GPA -> RPA */ 158 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc(); 159 if (!kvm->arch.gpa_mm.pgd) 160 return -ENOMEM; 161 162 #ifdef CONFIG_CPU_LOONGSON64 163 kvm_init_loongson_ipi(kvm); 164 #endif 165 166 return 0; 167 } 168 169 static void kvm_mips_free_gpa_pt(struct kvm *kvm) 170 { 171 /* It should always be safe to remove after flushing the whole range */ 172 WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0)); 173 pgd_free(NULL, kvm->arch.gpa_mm.pgd); 174 } 175 176 void kvm_arch_destroy_vm(struct kvm *kvm) 177 { 178 kvm_destroy_vcpus(kvm); 179 kvm_mips_free_gpa_pt(kvm); 180 } 181 182 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, 183 unsigned long arg) 184 { 185 return -ENOIOCTLCMD; 186 } 187 188 void kvm_arch_flush_shadow_all(struct kvm *kvm) 189 { 190 /* Flush whole GPA */ 191 kvm_mips_flush_gpa_pt(kvm, 0, ~0); 192 kvm_flush_remote_tlbs(kvm); 193 } 194 195 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 196 struct kvm_memory_slot *slot) 197 { 198 /* 199 * The slot has been made invalid (ready for moving or deletion), so we 200 * need to ensure that it can no longer be accessed by any guest VCPUs. 201 */ 202 203 spin_lock(&kvm->mmu_lock); 204 /* Flush slot from GPA */ 205 kvm_mips_flush_gpa_pt(kvm, slot->base_gfn, 206 slot->base_gfn + slot->npages - 1); 207 kvm_arch_flush_remote_tlbs_memslot(kvm, slot); 208 spin_unlock(&kvm->mmu_lock); 209 } 210 211 int kvm_arch_prepare_memory_region(struct kvm *kvm, 212 const struct kvm_memory_slot *old, 213 struct kvm_memory_slot *new, 214 enum kvm_mr_change change) 215 { 216 return 0; 217 } 218 219 void kvm_arch_commit_memory_region(struct kvm *kvm, 220 struct kvm_memory_slot *old, 221 const struct kvm_memory_slot *new, 222 enum kvm_mr_change change) 223 { 224 int needs_flush; 225 226 /* 227 * If dirty page logging is enabled, write protect all pages in the slot 228 * ready for dirty logging. 229 * 230 * There is no need to do this in any of the following cases: 231 * CREATE: No dirty mappings will already exist. 232 * MOVE/DELETE: The old mappings will already have been cleaned up by 233 * kvm_arch_flush_shadow_memslot() 234 */ 235 if (change == KVM_MR_FLAGS_ONLY && 236 (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 237 new->flags & KVM_MEM_LOG_DIRTY_PAGES)) { 238 spin_lock(&kvm->mmu_lock); 239 /* Write protect GPA page table entries */ 240 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn, 241 new->base_gfn + new->npages - 1); 242 if (needs_flush) 243 kvm_arch_flush_remote_tlbs_memslot(kvm, new); 244 spin_unlock(&kvm->mmu_lock); 245 } 246 } 247 248 static inline void dump_handler(const char *symbol, void *start, void *end) 249 { 250 u32 *p; 251 252 pr_debug("LEAF(%s)\n", symbol); 253 254 pr_debug("\t.set push\n"); 255 pr_debug("\t.set noreorder\n"); 256 257 for (p = start; p < (u32 *)end; ++p) 258 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p); 259 260 pr_debug("\t.set\tpop\n"); 261 262 pr_debug("\tEND(%s)\n", symbol); 263 } 264 265 /* low level hrtimer wake routine */ 266 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer) 267 { 268 struct kvm_vcpu *vcpu; 269 270 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer); 271 272 kvm_mips_callbacks->queue_timer_int(vcpu); 273 274 vcpu->arch.wait = 0; 275 rcuwait_wake_up(&vcpu->wait); 276 277 return kvm_mips_count_timeout(vcpu); 278 } 279 280 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 281 { 282 return 0; 283 } 284 285 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 286 { 287 int err, size; 288 void *gebase, *p, *handler, *refill_start, *refill_end; 289 int i; 290 291 kvm_debug("kvm @ %p: create cpu %d at %p\n", 292 vcpu->kvm, vcpu->vcpu_id, vcpu); 293 294 err = kvm_mips_callbacks->vcpu_init(vcpu); 295 if (err) 296 return err; 297 298 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC, 299 HRTIMER_MODE_REL); 300 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup; 301 302 /* 303 * Allocate space for host mode exception handlers that handle 304 * guest mode exits 305 */ 306 if (cpu_has_veic || cpu_has_vint) 307 size = 0x200 + VECTORSPACING * 64; 308 else 309 size = 0x4000; 310 311 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL); 312 313 if (!gebase) { 314 err = -ENOMEM; 315 goto out_uninit_vcpu; 316 } 317 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n", 318 ALIGN(size, PAGE_SIZE), gebase); 319 320 /* 321 * Check new ebase actually fits in CP0_EBase. The lack of a write gate 322 * limits us to the low 512MB of physical address space. If the memory 323 * we allocate is out of range, just give up now. 324 */ 325 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) { 326 kvm_err("CP0_EBase.WG required for guest exception base %pK\n", 327 gebase); 328 err = -ENOMEM; 329 goto out_free_gebase; 330 } 331 332 /* Save new ebase */ 333 vcpu->arch.guest_ebase = gebase; 334 335 /* Build guest exception vectors dynamically in unmapped memory */ 336 handler = gebase + 0x2000; 337 338 /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */ 339 refill_start = gebase; 340 if (IS_ENABLED(CONFIG_64BIT)) 341 refill_start += 0x080; 342 refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler); 343 344 /* General Exception Entry point */ 345 kvm_mips_build_exception(gebase + 0x180, handler); 346 347 /* For vectored interrupts poke the exception code @ all offsets 0-7 */ 348 for (i = 0; i < 8; i++) { 349 kvm_debug("L1 Vectored handler @ %p\n", 350 gebase + 0x200 + (i * VECTORSPACING)); 351 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING, 352 handler); 353 } 354 355 /* General exit handler */ 356 p = handler; 357 p = kvm_mips_build_exit(p); 358 359 /* Guest entry routine */ 360 vcpu->arch.vcpu_run = p; 361 p = kvm_mips_build_vcpu_run(p); 362 363 /* Dump the generated code */ 364 pr_debug("#include <asm/asm.h>\n"); 365 pr_debug("#include <asm/regdef.h>\n"); 366 pr_debug("\n"); 367 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p); 368 dump_handler("kvm_tlb_refill", refill_start, refill_end); 369 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200); 370 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run); 371 372 /* Invalidate the icache for these ranges */ 373 flush_icache_range((unsigned long)gebase, 374 (unsigned long)gebase + ALIGN(size, PAGE_SIZE)); 375 376 /* Init */ 377 vcpu->arch.last_sched_cpu = -1; 378 vcpu->arch.last_exec_cpu = -1; 379 380 /* Initial guest state */ 381 err = kvm_mips_callbacks->vcpu_setup(vcpu); 382 if (err) 383 goto out_free_gebase; 384 385 return 0; 386 387 out_free_gebase: 388 kfree(gebase); 389 out_uninit_vcpu: 390 kvm_mips_callbacks->vcpu_uninit(vcpu); 391 return err; 392 } 393 394 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 395 { 396 hrtimer_cancel(&vcpu->arch.comparecount_timer); 397 398 kvm_mips_dump_stats(vcpu); 399 400 kvm_mmu_free_memory_caches(vcpu); 401 kfree(vcpu->arch.guest_ebase); 402 403 kvm_mips_callbacks->vcpu_uninit(vcpu); 404 } 405 406 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 407 struct kvm_guest_debug *dbg) 408 { 409 return -ENOIOCTLCMD; 410 } 411 412 /* 413 * Actually run the vCPU, entering an RCU extended quiescent state (EQS) while 414 * the vCPU is running. 415 * 416 * This must be noinstr as instrumentation may make use of RCU, and this is not 417 * safe during the EQS. 418 */ 419 static int noinstr kvm_mips_vcpu_enter_exit(struct kvm_vcpu *vcpu) 420 { 421 int ret; 422 423 guest_state_enter_irqoff(); 424 ret = kvm_mips_callbacks->vcpu_run(vcpu); 425 guest_state_exit_irqoff(); 426 427 return ret; 428 } 429 430 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 431 { 432 int r = -EINTR; 433 434 vcpu_load(vcpu); 435 436 kvm_sigset_activate(vcpu); 437 438 if (vcpu->mmio_needed) { 439 if (!vcpu->mmio_is_write) 440 kvm_mips_complete_mmio_load(vcpu); 441 vcpu->mmio_needed = 0; 442 } 443 444 if (vcpu->run->immediate_exit) 445 goto out; 446 447 lose_fpu(1); 448 449 local_irq_disable(); 450 guest_timing_enter_irqoff(); 451 trace_kvm_enter(vcpu); 452 453 /* 454 * Make sure the read of VCPU requests in vcpu_run() callback is not 455 * reordered ahead of the write to vcpu->mode, or we could miss a TLB 456 * flush request while the requester sees the VCPU as outside of guest 457 * mode and not needing an IPI. 458 */ 459 smp_store_mb(vcpu->mode, IN_GUEST_MODE); 460 461 r = kvm_mips_vcpu_enter_exit(vcpu); 462 463 /* 464 * We must ensure that any pending interrupts are taken before 465 * we exit guest timing so that timer ticks are accounted as 466 * guest time. Transiently unmask interrupts so that any 467 * pending interrupts are taken. 468 * 469 * TODO: is there a barrier which ensures that pending interrupts are 470 * recognised? Currently this just hopes that the CPU takes any pending 471 * interrupts between the enable and disable. 472 */ 473 local_irq_enable(); 474 local_irq_disable(); 475 476 trace_kvm_out(vcpu); 477 guest_timing_exit_irqoff(); 478 local_irq_enable(); 479 480 out: 481 kvm_sigset_deactivate(vcpu); 482 483 vcpu_put(vcpu); 484 return r; 485 } 486 487 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 488 struct kvm_mips_interrupt *irq) 489 { 490 int intr = (int)irq->irq; 491 struct kvm_vcpu *dvcpu = NULL; 492 493 if (intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_1] || 494 intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_2] || 495 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_1]) || 496 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_2])) 497 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu, 498 (int)intr); 499 500 if (irq->cpu == -1) 501 dvcpu = vcpu; 502 else 503 dvcpu = kvm_get_vcpu(vcpu->kvm, irq->cpu); 504 505 if (intr == 2 || intr == 3 || intr == 4 || intr == 6) { 506 kvm_mips_callbacks->queue_io_int(dvcpu, irq); 507 508 } else if (intr == -2 || intr == -3 || intr == -4 || intr == -6) { 509 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq); 510 } else { 511 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__, 512 irq->cpu, irq->irq); 513 return -EINVAL; 514 } 515 516 dvcpu->arch.wait = 0; 517 518 rcuwait_wake_up(&dvcpu->wait); 519 520 return 0; 521 } 522 523 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 524 struct kvm_mp_state *mp_state) 525 { 526 return -ENOIOCTLCMD; 527 } 528 529 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 530 struct kvm_mp_state *mp_state) 531 { 532 return -ENOIOCTLCMD; 533 } 534 535 static u64 kvm_mips_get_one_regs[] = { 536 KVM_REG_MIPS_R0, 537 KVM_REG_MIPS_R1, 538 KVM_REG_MIPS_R2, 539 KVM_REG_MIPS_R3, 540 KVM_REG_MIPS_R4, 541 KVM_REG_MIPS_R5, 542 KVM_REG_MIPS_R6, 543 KVM_REG_MIPS_R7, 544 KVM_REG_MIPS_R8, 545 KVM_REG_MIPS_R9, 546 KVM_REG_MIPS_R10, 547 KVM_REG_MIPS_R11, 548 KVM_REG_MIPS_R12, 549 KVM_REG_MIPS_R13, 550 KVM_REG_MIPS_R14, 551 KVM_REG_MIPS_R15, 552 KVM_REG_MIPS_R16, 553 KVM_REG_MIPS_R17, 554 KVM_REG_MIPS_R18, 555 KVM_REG_MIPS_R19, 556 KVM_REG_MIPS_R20, 557 KVM_REG_MIPS_R21, 558 KVM_REG_MIPS_R22, 559 KVM_REG_MIPS_R23, 560 KVM_REG_MIPS_R24, 561 KVM_REG_MIPS_R25, 562 KVM_REG_MIPS_R26, 563 KVM_REG_MIPS_R27, 564 KVM_REG_MIPS_R28, 565 KVM_REG_MIPS_R29, 566 KVM_REG_MIPS_R30, 567 KVM_REG_MIPS_R31, 568 569 #ifndef CONFIG_CPU_MIPSR6 570 KVM_REG_MIPS_HI, 571 KVM_REG_MIPS_LO, 572 #endif 573 KVM_REG_MIPS_PC, 574 }; 575 576 static u64 kvm_mips_get_one_regs_fpu[] = { 577 KVM_REG_MIPS_FCR_IR, 578 KVM_REG_MIPS_FCR_CSR, 579 }; 580 581 static u64 kvm_mips_get_one_regs_msa[] = { 582 KVM_REG_MIPS_MSA_IR, 583 KVM_REG_MIPS_MSA_CSR, 584 }; 585 586 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu) 587 { 588 unsigned long ret; 589 590 ret = ARRAY_SIZE(kvm_mips_get_one_regs); 591 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { 592 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48; 593 /* odd doubles */ 594 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64) 595 ret += 16; 596 } 597 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) 598 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32; 599 ret += kvm_mips_callbacks->num_regs(vcpu); 600 601 return ret; 602 } 603 604 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices) 605 { 606 u64 index; 607 unsigned int i; 608 609 if (copy_to_user(indices, kvm_mips_get_one_regs, 610 sizeof(kvm_mips_get_one_regs))) 611 return -EFAULT; 612 indices += ARRAY_SIZE(kvm_mips_get_one_regs); 613 614 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { 615 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu, 616 sizeof(kvm_mips_get_one_regs_fpu))) 617 return -EFAULT; 618 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu); 619 620 for (i = 0; i < 32; ++i) { 621 index = KVM_REG_MIPS_FPR_32(i); 622 if (copy_to_user(indices, &index, sizeof(index))) 623 return -EFAULT; 624 ++indices; 625 626 /* skip odd doubles if no F64 */ 627 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64)) 628 continue; 629 630 index = KVM_REG_MIPS_FPR_64(i); 631 if (copy_to_user(indices, &index, sizeof(index))) 632 return -EFAULT; 633 ++indices; 634 } 635 } 636 637 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) { 638 if (copy_to_user(indices, kvm_mips_get_one_regs_msa, 639 sizeof(kvm_mips_get_one_regs_msa))) 640 return -EFAULT; 641 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa); 642 643 for (i = 0; i < 32; ++i) { 644 index = KVM_REG_MIPS_VEC_128(i); 645 if (copy_to_user(indices, &index, sizeof(index))) 646 return -EFAULT; 647 ++indices; 648 } 649 } 650 651 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices); 652 } 653 654 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu, 655 const struct kvm_one_reg *reg) 656 { 657 struct mips_coproc *cop0 = vcpu->arch.cop0; 658 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 659 int ret; 660 s64 v; 661 s64 vs[2]; 662 unsigned int idx; 663 664 switch (reg->id) { 665 /* General purpose registers */ 666 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31: 667 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0]; 668 break; 669 #ifndef CONFIG_CPU_MIPSR6 670 case KVM_REG_MIPS_HI: 671 v = (long)vcpu->arch.hi; 672 break; 673 case KVM_REG_MIPS_LO: 674 v = (long)vcpu->arch.lo; 675 break; 676 #endif 677 case KVM_REG_MIPS_PC: 678 v = (long)vcpu->arch.pc; 679 break; 680 681 /* Floating point registers */ 682 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 683 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 684 return -EINVAL; 685 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 686 /* Odd singles in top of even double when FR=0 */ 687 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 688 v = get_fpr32(&fpu->fpr[idx], 0); 689 else 690 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1); 691 break; 692 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 693 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 694 return -EINVAL; 695 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 696 /* Can't access odd doubles in FR=0 mode */ 697 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 698 return -EINVAL; 699 v = get_fpr64(&fpu->fpr[idx], 0); 700 break; 701 case KVM_REG_MIPS_FCR_IR: 702 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 703 return -EINVAL; 704 v = boot_cpu_data.fpu_id; 705 break; 706 case KVM_REG_MIPS_FCR_CSR: 707 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 708 return -EINVAL; 709 v = fpu->fcr31; 710 break; 711 712 /* MIPS SIMD Architecture (MSA) registers */ 713 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 714 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 715 return -EINVAL; 716 /* Can't access MSA registers in FR=0 mode */ 717 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR)) 718 return -EINVAL; 719 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 720 #ifdef CONFIG_CPU_LITTLE_ENDIAN 721 /* least significant byte first */ 722 vs[0] = get_fpr64(&fpu->fpr[idx], 0); 723 vs[1] = get_fpr64(&fpu->fpr[idx], 1); 724 #else 725 /* most significant byte first */ 726 vs[0] = get_fpr64(&fpu->fpr[idx], 1); 727 vs[1] = get_fpr64(&fpu->fpr[idx], 0); 728 #endif 729 break; 730 case KVM_REG_MIPS_MSA_IR: 731 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 732 return -EINVAL; 733 v = boot_cpu_data.msa_id; 734 break; 735 case KVM_REG_MIPS_MSA_CSR: 736 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 737 return -EINVAL; 738 v = fpu->msacsr; 739 break; 740 741 /* registers to be handled specially */ 742 default: 743 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v); 744 if (ret) 745 return ret; 746 break; 747 } 748 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 749 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 750 751 return put_user(v, uaddr64); 752 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 753 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 754 u32 v32 = (u32)v; 755 756 return put_user(v32, uaddr32); 757 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 758 void __user *uaddr = (void __user *)(long)reg->addr; 759 760 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0; 761 } else { 762 return -EINVAL; 763 } 764 } 765 766 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu, 767 const struct kvm_one_reg *reg) 768 { 769 struct mips_coproc *cop0 = vcpu->arch.cop0; 770 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 771 s64 v; 772 s64 vs[2]; 773 unsigned int idx; 774 775 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 776 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 777 778 if (get_user(v, uaddr64) != 0) 779 return -EFAULT; 780 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 781 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 782 s32 v32; 783 784 if (get_user(v32, uaddr32) != 0) 785 return -EFAULT; 786 v = (s64)v32; 787 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 788 void __user *uaddr = (void __user *)(long)reg->addr; 789 790 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0; 791 } else { 792 return -EINVAL; 793 } 794 795 switch (reg->id) { 796 /* General purpose registers */ 797 case KVM_REG_MIPS_R0: 798 /* Silently ignore requests to set $0 */ 799 break; 800 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31: 801 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v; 802 break; 803 #ifndef CONFIG_CPU_MIPSR6 804 case KVM_REG_MIPS_HI: 805 vcpu->arch.hi = v; 806 break; 807 case KVM_REG_MIPS_LO: 808 vcpu->arch.lo = v; 809 break; 810 #endif 811 case KVM_REG_MIPS_PC: 812 vcpu->arch.pc = v; 813 break; 814 815 /* Floating point registers */ 816 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 817 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 818 return -EINVAL; 819 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 820 /* Odd singles in top of even double when FR=0 */ 821 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 822 set_fpr32(&fpu->fpr[idx], 0, v); 823 else 824 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v); 825 break; 826 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 827 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 828 return -EINVAL; 829 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 830 /* Can't access odd doubles in FR=0 mode */ 831 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 832 return -EINVAL; 833 set_fpr64(&fpu->fpr[idx], 0, v); 834 break; 835 case KVM_REG_MIPS_FCR_IR: 836 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 837 return -EINVAL; 838 /* Read-only */ 839 break; 840 case KVM_REG_MIPS_FCR_CSR: 841 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 842 return -EINVAL; 843 fpu->fcr31 = v; 844 break; 845 846 /* MIPS SIMD Architecture (MSA) registers */ 847 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 848 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 849 return -EINVAL; 850 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 851 #ifdef CONFIG_CPU_LITTLE_ENDIAN 852 /* least significant byte first */ 853 set_fpr64(&fpu->fpr[idx], 0, vs[0]); 854 set_fpr64(&fpu->fpr[idx], 1, vs[1]); 855 #else 856 /* most significant byte first */ 857 set_fpr64(&fpu->fpr[idx], 1, vs[0]); 858 set_fpr64(&fpu->fpr[idx], 0, vs[1]); 859 #endif 860 break; 861 case KVM_REG_MIPS_MSA_IR: 862 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 863 return -EINVAL; 864 /* Read-only */ 865 break; 866 case KVM_REG_MIPS_MSA_CSR: 867 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 868 return -EINVAL; 869 fpu->msacsr = v; 870 break; 871 872 /* registers to be handled specially */ 873 default: 874 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v); 875 } 876 return 0; 877 } 878 879 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 880 struct kvm_enable_cap *cap) 881 { 882 int r = 0; 883 884 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap)) 885 return -EINVAL; 886 if (cap->flags) 887 return -EINVAL; 888 if (cap->args[0]) 889 return -EINVAL; 890 891 switch (cap->cap) { 892 case KVM_CAP_MIPS_FPU: 893 vcpu->arch.fpu_enabled = true; 894 break; 895 case KVM_CAP_MIPS_MSA: 896 vcpu->arch.msa_enabled = true; 897 break; 898 default: 899 r = -EINVAL; 900 break; 901 } 902 903 return r; 904 } 905 906 long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl, 907 unsigned long arg) 908 { 909 struct kvm_vcpu *vcpu = filp->private_data; 910 void __user *argp = (void __user *)arg; 911 912 if (ioctl == KVM_INTERRUPT) { 913 struct kvm_mips_interrupt irq; 914 915 if (copy_from_user(&irq, argp, sizeof(irq))) 916 return -EFAULT; 917 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__, 918 irq.irq); 919 920 return kvm_vcpu_ioctl_interrupt(vcpu, &irq); 921 } 922 923 return -ENOIOCTLCMD; 924 } 925 926 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, 927 unsigned long arg) 928 { 929 struct kvm_vcpu *vcpu = filp->private_data; 930 void __user *argp = (void __user *)arg; 931 long r; 932 933 vcpu_load(vcpu); 934 935 switch (ioctl) { 936 case KVM_SET_ONE_REG: 937 case KVM_GET_ONE_REG: { 938 struct kvm_one_reg reg; 939 940 r = -EFAULT; 941 if (copy_from_user(®, argp, sizeof(reg))) 942 break; 943 if (ioctl == KVM_SET_ONE_REG) 944 r = kvm_mips_set_reg(vcpu, ®); 945 else 946 r = kvm_mips_get_reg(vcpu, ®); 947 break; 948 } 949 case KVM_GET_REG_LIST: { 950 struct kvm_reg_list __user *user_list = argp; 951 struct kvm_reg_list reg_list; 952 unsigned n; 953 954 r = -EFAULT; 955 if (copy_from_user(®_list, user_list, sizeof(reg_list))) 956 break; 957 n = reg_list.n; 958 reg_list.n = kvm_mips_num_regs(vcpu); 959 if (copy_to_user(user_list, ®_list, sizeof(reg_list))) 960 break; 961 r = -E2BIG; 962 if (n < reg_list.n) 963 break; 964 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg); 965 break; 966 } 967 case KVM_ENABLE_CAP: { 968 struct kvm_enable_cap cap; 969 970 r = -EFAULT; 971 if (copy_from_user(&cap, argp, sizeof(cap))) 972 break; 973 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 974 break; 975 } 976 default: 977 r = -ENOIOCTLCMD; 978 } 979 980 vcpu_put(vcpu); 981 return r; 982 } 983 984 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 985 { 986 987 } 988 989 int kvm_arch_flush_remote_tlb(struct kvm *kvm) 990 { 991 kvm_mips_callbacks->prepare_flush_shadow(kvm); 992 return 1; 993 } 994 995 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm, 996 const struct kvm_memory_slot *memslot) 997 { 998 kvm_flush_remote_tlbs(kvm); 999 } 1000 1001 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) 1002 { 1003 long r; 1004 1005 switch (ioctl) { 1006 default: 1007 r = -ENOIOCTLCMD; 1008 } 1009 1010 return r; 1011 } 1012 1013 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 1014 struct kvm_sregs *sregs) 1015 { 1016 return -ENOIOCTLCMD; 1017 } 1018 1019 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 1020 struct kvm_sregs *sregs) 1021 { 1022 return -ENOIOCTLCMD; 1023 } 1024 1025 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 1026 { 1027 } 1028 1029 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1030 { 1031 return -ENOIOCTLCMD; 1032 } 1033 1034 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1035 { 1036 return -ENOIOCTLCMD; 1037 } 1038 1039 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 1040 { 1041 return VM_FAULT_SIGBUS; 1042 } 1043 1044 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 1045 { 1046 int r; 1047 1048 switch (ext) { 1049 case KVM_CAP_ONE_REG: 1050 case KVM_CAP_ENABLE_CAP: 1051 case KVM_CAP_READONLY_MEM: 1052 case KVM_CAP_SYNC_MMU: 1053 case KVM_CAP_IMMEDIATE_EXIT: 1054 r = 1; 1055 break; 1056 case KVM_CAP_NR_VCPUS: 1057 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS); 1058 break; 1059 case KVM_CAP_MAX_VCPUS: 1060 r = KVM_MAX_VCPUS; 1061 break; 1062 case KVM_CAP_MAX_VCPU_ID: 1063 r = KVM_MAX_VCPU_IDS; 1064 break; 1065 case KVM_CAP_MIPS_FPU: 1066 /* We don't handle systems with inconsistent cpu_has_fpu */ 1067 r = !!raw_cpu_has_fpu; 1068 break; 1069 case KVM_CAP_MIPS_MSA: 1070 /* 1071 * We don't support MSA vector partitioning yet: 1072 * 1) It would require explicit support which can't be tested 1073 * yet due to lack of support in current hardware. 1074 * 2) It extends the state that would need to be saved/restored 1075 * by e.g. QEMU for migration. 1076 * 1077 * When vector partitioning hardware becomes available, support 1078 * could be added by requiring a flag when enabling 1079 * KVM_CAP_MIPS_MSA capability to indicate that userland knows 1080 * to save/restore the appropriate extra state. 1081 */ 1082 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF); 1083 break; 1084 default: 1085 r = kvm_mips_callbacks->check_extension(kvm, ext); 1086 break; 1087 } 1088 return r; 1089 } 1090 1091 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 1092 { 1093 return kvm_mips_pending_timer(vcpu) || 1094 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI; 1095 } 1096 1097 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu) 1098 { 1099 int i; 1100 struct mips_coproc *cop0; 1101 1102 if (!vcpu) 1103 return -1; 1104 1105 kvm_debug("VCPU Register Dump:\n"); 1106 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc); 1107 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions); 1108 1109 for (i = 0; i < 32; i += 4) { 1110 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i, 1111 vcpu->arch.gprs[i], 1112 vcpu->arch.gprs[i + 1], 1113 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]); 1114 } 1115 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi); 1116 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo); 1117 1118 cop0 = vcpu->arch.cop0; 1119 kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n", 1120 kvm_read_c0_guest_status(cop0), 1121 kvm_read_c0_guest_cause(cop0)); 1122 1123 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0)); 1124 1125 return 0; 1126 } 1127 1128 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1129 { 1130 int i; 1131 1132 vcpu_load(vcpu); 1133 1134 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1135 vcpu->arch.gprs[i] = regs->gpr[i]; 1136 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */ 1137 vcpu->arch.hi = regs->hi; 1138 vcpu->arch.lo = regs->lo; 1139 vcpu->arch.pc = regs->pc; 1140 1141 vcpu_put(vcpu); 1142 return 0; 1143 } 1144 1145 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1146 { 1147 int i; 1148 1149 vcpu_load(vcpu); 1150 1151 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1152 regs->gpr[i] = vcpu->arch.gprs[i]; 1153 1154 regs->hi = vcpu->arch.hi; 1155 regs->lo = vcpu->arch.lo; 1156 regs->pc = vcpu->arch.pc; 1157 1158 vcpu_put(vcpu); 1159 return 0; 1160 } 1161 1162 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 1163 struct kvm_translation *tr) 1164 { 1165 return 0; 1166 } 1167 1168 static void kvm_mips_set_c0_status(void) 1169 { 1170 u32 status = read_c0_status(); 1171 1172 if (cpu_has_dsp) 1173 status |= (ST0_MX); 1174 1175 write_c0_status(status); 1176 ehb(); 1177 } 1178 1179 /* 1180 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) 1181 */ 1182 static int __kvm_mips_handle_exit(struct kvm_vcpu *vcpu) 1183 { 1184 struct kvm_run *run = vcpu->run; 1185 u32 cause = vcpu->arch.host_cp0_cause; 1186 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; 1187 u32 __user *opc = (u32 __user *) vcpu->arch.pc; 1188 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr; 1189 enum emulation_result er = EMULATE_DONE; 1190 u32 inst; 1191 int ret = RESUME_GUEST; 1192 1193 vcpu->mode = OUTSIDE_GUEST_MODE; 1194 1195 /* Set a default exit reason */ 1196 run->exit_reason = KVM_EXIT_UNKNOWN; 1197 run->ready_for_interrupt_injection = 1; 1198 1199 /* 1200 * Set the appropriate status bits based on host CPU features, 1201 * before we hit the scheduler 1202 */ 1203 kvm_mips_set_c0_status(); 1204 1205 local_irq_enable(); 1206 1207 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n", 1208 cause, opc, run, vcpu); 1209 trace_kvm_exit(vcpu, exccode); 1210 1211 switch (exccode) { 1212 case EXCCODE_INT: 1213 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc); 1214 1215 ++vcpu->stat.int_exits; 1216 1217 if (need_resched()) 1218 cond_resched(); 1219 1220 ret = RESUME_GUEST; 1221 break; 1222 1223 case EXCCODE_CPU: 1224 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc); 1225 1226 ++vcpu->stat.cop_unusable_exits; 1227 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu); 1228 /* XXXKYMA: Might need to return to user space */ 1229 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN) 1230 ret = RESUME_HOST; 1231 break; 1232 1233 case EXCCODE_MOD: 1234 ++vcpu->stat.tlbmod_exits; 1235 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu); 1236 break; 1237 1238 case EXCCODE_TLBS: 1239 kvm_debug("TLB ST fault: cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n", 1240 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc, 1241 badvaddr); 1242 1243 ++vcpu->stat.tlbmiss_st_exits; 1244 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu); 1245 break; 1246 1247 case EXCCODE_TLBL: 1248 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n", 1249 cause, opc, badvaddr); 1250 1251 ++vcpu->stat.tlbmiss_ld_exits; 1252 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu); 1253 break; 1254 1255 case EXCCODE_ADES: 1256 ++vcpu->stat.addrerr_st_exits; 1257 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu); 1258 break; 1259 1260 case EXCCODE_ADEL: 1261 ++vcpu->stat.addrerr_ld_exits; 1262 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu); 1263 break; 1264 1265 case EXCCODE_SYS: 1266 ++vcpu->stat.syscall_exits; 1267 ret = kvm_mips_callbacks->handle_syscall(vcpu); 1268 break; 1269 1270 case EXCCODE_RI: 1271 ++vcpu->stat.resvd_inst_exits; 1272 ret = kvm_mips_callbacks->handle_res_inst(vcpu); 1273 break; 1274 1275 case EXCCODE_BP: 1276 ++vcpu->stat.break_inst_exits; 1277 ret = kvm_mips_callbacks->handle_break(vcpu); 1278 break; 1279 1280 case EXCCODE_TR: 1281 ++vcpu->stat.trap_inst_exits; 1282 ret = kvm_mips_callbacks->handle_trap(vcpu); 1283 break; 1284 1285 case EXCCODE_MSAFPE: 1286 ++vcpu->stat.msa_fpe_exits; 1287 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu); 1288 break; 1289 1290 case EXCCODE_FPE: 1291 ++vcpu->stat.fpe_exits; 1292 ret = kvm_mips_callbacks->handle_fpe(vcpu); 1293 break; 1294 1295 case EXCCODE_MSADIS: 1296 ++vcpu->stat.msa_disabled_exits; 1297 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu); 1298 break; 1299 1300 case EXCCODE_GE: 1301 /* defer exit accounting to handler */ 1302 ret = kvm_mips_callbacks->handle_guest_exit(vcpu); 1303 break; 1304 1305 default: 1306 if (cause & CAUSEF_BD) 1307 opc += 1; 1308 inst = 0; 1309 kvm_get_badinstr(opc, vcpu, &inst); 1310 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n", 1311 exccode, opc, inst, badvaddr, 1312 kvm_read_c0_guest_status(vcpu->arch.cop0)); 1313 kvm_arch_vcpu_dump_regs(vcpu); 1314 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1315 ret = RESUME_HOST; 1316 break; 1317 1318 } 1319 1320 local_irq_disable(); 1321 1322 if (ret == RESUME_GUEST) 1323 kvm_vz_acquire_htimer(vcpu); 1324 1325 if (er == EMULATE_DONE && !(ret & RESUME_HOST)) 1326 kvm_mips_deliver_interrupts(vcpu, cause); 1327 1328 if (!(ret & RESUME_HOST)) { 1329 /* Only check for signals if not already exiting to userspace */ 1330 if (signal_pending(current)) { 1331 run->exit_reason = KVM_EXIT_INTR; 1332 ret = (-EINTR << 2) | RESUME_HOST; 1333 ++vcpu->stat.signal_exits; 1334 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL); 1335 } 1336 } 1337 1338 if (ret == RESUME_GUEST) { 1339 trace_kvm_reenter(vcpu); 1340 1341 /* 1342 * Make sure the read of VCPU requests in vcpu_reenter() 1343 * callback is not reordered ahead of the write to vcpu->mode, 1344 * or we could miss a TLB flush request while the requester sees 1345 * the VCPU as outside of guest mode and not needing an IPI. 1346 */ 1347 smp_store_mb(vcpu->mode, IN_GUEST_MODE); 1348 1349 kvm_mips_callbacks->vcpu_reenter(vcpu); 1350 1351 /* 1352 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context 1353 * is live), restore FCR31 / MSACSR. 1354 * 1355 * This should be before returning to the guest exception 1356 * vector, as it may well cause an [MSA] FP exception if there 1357 * are pending exception bits unmasked. (see 1358 * kvm_mips_csr_die_notifier() for how that is handled). 1359 */ 1360 if (kvm_mips_guest_has_fpu(&vcpu->arch) && 1361 read_c0_status() & ST0_CU1) 1362 __kvm_restore_fcsr(&vcpu->arch); 1363 1364 if (kvm_mips_guest_has_msa(&vcpu->arch) && 1365 read_c0_config5() & MIPS_CONF5_MSAEN) 1366 __kvm_restore_msacsr(&vcpu->arch); 1367 } 1368 return ret; 1369 } 1370 1371 int noinstr kvm_mips_handle_exit(struct kvm_vcpu *vcpu) 1372 { 1373 int ret; 1374 1375 guest_state_exit_irqoff(); 1376 ret = __kvm_mips_handle_exit(vcpu); 1377 guest_state_enter_irqoff(); 1378 1379 return ret; 1380 } 1381 1382 /* Enable FPU for guest and restore context */ 1383 void kvm_own_fpu(struct kvm_vcpu *vcpu) 1384 { 1385 struct mips_coproc *cop0 = vcpu->arch.cop0; 1386 unsigned int sr, cfg5; 1387 1388 preempt_disable(); 1389 1390 sr = kvm_read_c0_guest_status(cop0); 1391 1392 /* 1393 * If MSA state is already live, it is undefined how it interacts with 1394 * FR=0 FPU state, and we don't want to hit reserved instruction 1395 * exceptions trying to save the MSA state later when CU=1 && FR=1, so 1396 * play it safe and save it first. 1397 */ 1398 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) && 1399 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) 1400 kvm_lose_fpu(vcpu); 1401 1402 /* 1403 * Enable FPU for guest 1404 * We set FR and FRE according to guest context 1405 */ 1406 change_c0_status(ST0_CU1 | ST0_FR, sr); 1407 if (cpu_has_fre) { 1408 cfg5 = kvm_read_c0_guest_config5(cop0); 1409 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1410 } 1411 enable_fpu_hazard(); 1412 1413 /* If guest FPU state not active, restore it now */ 1414 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) { 1415 __kvm_restore_fpu(&vcpu->arch); 1416 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; 1417 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU); 1418 } else { 1419 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU); 1420 } 1421 1422 preempt_enable(); 1423 } 1424 1425 #ifdef CONFIG_CPU_HAS_MSA 1426 /* Enable MSA for guest and restore context */ 1427 void kvm_own_msa(struct kvm_vcpu *vcpu) 1428 { 1429 struct mips_coproc *cop0 = vcpu->arch.cop0; 1430 unsigned int sr, cfg5; 1431 1432 preempt_disable(); 1433 1434 /* 1435 * Enable FPU if enabled in guest, since we're restoring FPU context 1436 * anyway. We set FR and FRE according to guest context. 1437 */ 1438 if (kvm_mips_guest_has_fpu(&vcpu->arch)) { 1439 sr = kvm_read_c0_guest_status(cop0); 1440 1441 /* 1442 * If FR=0 FPU state is already live, it is undefined how it 1443 * interacts with MSA state, so play it safe and save it first. 1444 */ 1445 if (!(sr & ST0_FR) && 1446 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | 1447 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU) 1448 kvm_lose_fpu(vcpu); 1449 1450 change_c0_status(ST0_CU1 | ST0_FR, sr); 1451 if (sr & ST0_CU1 && cpu_has_fre) { 1452 cfg5 = kvm_read_c0_guest_config5(cop0); 1453 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1454 } 1455 } 1456 1457 /* Enable MSA for guest */ 1458 set_c0_config5(MIPS_CONF5_MSAEN); 1459 enable_fpu_hazard(); 1460 1461 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) { 1462 case KVM_MIPS_AUX_FPU: 1463 /* 1464 * Guest FPU state already loaded, only restore upper MSA state 1465 */ 1466 __kvm_restore_msa_upper(&vcpu->arch); 1467 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; 1468 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA); 1469 break; 1470 case 0: 1471 /* Neither FPU or MSA already active, restore full MSA state */ 1472 __kvm_restore_msa(&vcpu->arch); 1473 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; 1474 if (kvm_mips_guest_has_fpu(&vcpu->arch)) 1475 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; 1476 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, 1477 KVM_TRACE_AUX_FPU_MSA); 1478 break; 1479 default: 1480 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA); 1481 break; 1482 } 1483 1484 preempt_enable(); 1485 } 1486 #endif 1487 1488 /* Drop FPU & MSA without saving it */ 1489 void kvm_drop_fpu(struct kvm_vcpu *vcpu) 1490 { 1491 preempt_disable(); 1492 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { 1493 disable_msa(); 1494 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA); 1495 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA; 1496 } 1497 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1498 clear_c0_status(ST0_CU1 | ST0_FR); 1499 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU); 1500 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; 1501 } 1502 preempt_enable(); 1503 } 1504 1505 /* Save and disable FPU & MSA */ 1506 void kvm_lose_fpu(struct kvm_vcpu *vcpu) 1507 { 1508 /* 1509 * With T&E, FPU & MSA get disabled in root context (hardware) when it 1510 * is disabled in guest context (software), but the register state in 1511 * the hardware may still be in use. 1512 * This is why we explicitly re-enable the hardware before saving. 1513 */ 1514 1515 preempt_disable(); 1516 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { 1517 __kvm_save_msa(&vcpu->arch); 1518 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA); 1519 1520 /* Disable MSA & FPU */ 1521 disable_msa(); 1522 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1523 clear_c0_status(ST0_CU1 | ST0_FR); 1524 disable_fpu_hazard(); 1525 } 1526 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA); 1527 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1528 __kvm_save_fpu(&vcpu->arch); 1529 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; 1530 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU); 1531 1532 /* Disable FPU */ 1533 clear_c0_status(ST0_CU1 | ST0_FR); 1534 disable_fpu_hazard(); 1535 } 1536 preempt_enable(); 1537 } 1538 1539 /* 1540 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are 1541 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP 1542 * exception if cause bits are set in the value being written. 1543 */ 1544 static int kvm_mips_csr_die_notify(struct notifier_block *self, 1545 unsigned long cmd, void *ptr) 1546 { 1547 struct die_args *args = (struct die_args *)ptr; 1548 struct pt_regs *regs = args->regs; 1549 unsigned long pc; 1550 1551 /* Only interested in FPE and MSAFPE */ 1552 if (cmd != DIE_FP && cmd != DIE_MSAFP) 1553 return NOTIFY_DONE; 1554 1555 /* Return immediately if guest context isn't active */ 1556 if (!(current->flags & PF_VCPU)) 1557 return NOTIFY_DONE; 1558 1559 /* Should never get here from user mode */ 1560 BUG_ON(user_mode(regs)); 1561 1562 pc = instruction_pointer(regs); 1563 switch (cmd) { 1564 case DIE_FP: 1565 /* match 2nd instruction in __kvm_restore_fcsr */ 1566 if (pc != (unsigned long)&__kvm_restore_fcsr + 4) 1567 return NOTIFY_DONE; 1568 break; 1569 case DIE_MSAFP: 1570 /* match 2nd/3rd instruction in __kvm_restore_msacsr */ 1571 if (!cpu_has_msa || 1572 pc < (unsigned long)&__kvm_restore_msacsr + 4 || 1573 pc > (unsigned long)&__kvm_restore_msacsr + 8) 1574 return NOTIFY_DONE; 1575 break; 1576 } 1577 1578 /* Move PC forward a little and continue executing */ 1579 instruction_pointer(regs) += 4; 1580 1581 return NOTIFY_STOP; 1582 } 1583 1584 static struct notifier_block kvm_mips_csr_die_notifier = { 1585 .notifier_call = kvm_mips_csr_die_notify, 1586 }; 1587 1588 static u32 kvm_default_priority_to_irq[MIPS_EXC_MAX] = { 1589 [MIPS_EXC_INT_TIMER] = C_IRQ5, 1590 [MIPS_EXC_INT_IO_1] = C_IRQ0, 1591 [MIPS_EXC_INT_IPI_1] = C_IRQ1, 1592 [MIPS_EXC_INT_IPI_2] = C_IRQ2, 1593 }; 1594 1595 static u32 kvm_loongson3_priority_to_irq[MIPS_EXC_MAX] = { 1596 [MIPS_EXC_INT_TIMER] = C_IRQ5, 1597 [MIPS_EXC_INT_IO_1] = C_IRQ0, 1598 [MIPS_EXC_INT_IO_2] = C_IRQ1, 1599 [MIPS_EXC_INT_IPI_1] = C_IRQ4, 1600 }; 1601 1602 u32 *kvm_priority_to_irq = kvm_default_priority_to_irq; 1603 1604 u32 kvm_irq_to_priority(u32 irq) 1605 { 1606 int i; 1607 1608 for (i = MIPS_EXC_INT_TIMER; i < MIPS_EXC_MAX; i++) { 1609 if (kvm_priority_to_irq[i] == (1 << (irq + 8))) 1610 return i; 1611 } 1612 1613 return MIPS_EXC_MAX; 1614 } 1615 1616 static int __init kvm_mips_init(void) 1617 { 1618 int ret; 1619 1620 if (cpu_has_mmid) { 1621 pr_warn("KVM does not yet support MMIDs. KVM Disabled\n"); 1622 return -EOPNOTSUPP; 1623 } 1624 1625 ret = kvm_mips_entry_setup(); 1626 if (ret) 1627 return ret; 1628 1629 ret = kvm_mips_emulation_init(); 1630 if (ret) 1631 return ret; 1632 1633 1634 if (boot_cpu_type() == CPU_LOONGSON64) 1635 kvm_priority_to_irq = kvm_loongson3_priority_to_irq; 1636 1637 register_die_notifier(&kvm_mips_csr_die_notifier); 1638 1639 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE); 1640 if (ret) { 1641 unregister_die_notifier(&kvm_mips_csr_die_notifier); 1642 return ret; 1643 } 1644 return 0; 1645 } 1646 1647 static void __exit kvm_mips_exit(void) 1648 { 1649 kvm_exit(); 1650 1651 unregister_die_notifier(&kvm_mips_csr_die_notifier); 1652 } 1653 1654 module_init(kvm_mips_init); 1655 module_exit(kvm_mips_exit); 1656 1657 EXPORT_TRACEPOINT_SYMBOL(kvm_exit); 1658