1 /* 2 * Format of an instruction in memory. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 2000 by Ralf Baechle 9 * Copyright (C) 2006 by Thiemo Seufer 10 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 11 * Copyright (C) 2014 Imagination Technologies Ltd. 12 */ 13 #ifndef _UAPI_ASM_INST_H 14 #define _UAPI_ASM_INST_H 15 16 #include <asm/bitfield.h> 17 18 /* 19 * Major opcodes; before MIPS IV cop1x was called cop3. 20 */ 21 enum major_op { 22 spec_op, bcond_op, j_op, jal_op, 23 beq_op, bne_op, blez_op, bgtz_op, 24 addi_op, addiu_op, slti_op, sltiu_op, 25 andi_op, ori_op, xori_op, lui_op, 26 cop0_op, cop1_op, cop2_op, cop1x_op, 27 beql_op, bnel_op, blezl_op, bgtzl_op, 28 daddi_op, daddiu_op, ldl_op, ldr_op, 29 spec2_op, jalx_op, mdmx_op, spec3_op, 30 lb_op, lh_op, lwl_op, lw_op, 31 lbu_op, lhu_op, lwr_op, lwu_op, 32 sb_op, sh_op, swl_op, sw_op, 33 sdl_op, sdr_op, swr_op, cache_op, 34 ll_op, lwc1_op, lwc2_op, pref_op, 35 lld_op, ldc1_op, ldc2_op, ld_op, 36 sc_op, swc1_op, swc2_op, major_3b_op, 37 scd_op, sdc1_op, sdc2_op, sd_op 38 }; 39 40 /* 41 * func field of spec opcode. 42 */ 43 enum spec_op { 44 sll_op, movc_op, srl_op, sra_op, 45 sllv_op, pmon_op, srlv_op, srav_op, 46 jr_op, jalr_op, movz_op, movn_op, 47 syscall_op, break_op, spim_op, sync_op, 48 mfhi_op, mthi_op, mflo_op, mtlo_op, 49 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, 50 mult_op, multu_op, div_op, divu_op, 51 dmult_op, dmultu_op, ddiv_op, ddivu_op, 52 add_op, addu_op, sub_op, subu_op, 53 and_op, or_op, xor_op, nor_op, 54 spec3_unused_op, spec4_unused_op, slt_op, sltu_op, 55 dadd_op, daddu_op, dsub_op, dsubu_op, 56 tge_op, tgeu_op, tlt_op, tltu_op, 57 teq_op, spec5_unused_op, tne_op, spec6_unused_op, 58 dsll_op, spec7_unused_op, dsrl_op, dsra_op, 59 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op 60 }; 61 62 /* 63 * func field of spec2 opcode. 64 */ 65 enum spec2_op { 66 madd_op, maddu_op, mul_op, spec2_3_unused_op, 67 msub_op, msubu_op, /* more unused ops */ 68 clz_op = 0x20, clo_op, 69 dclz_op = 0x24, dclo_op, 70 sdbpp_op = 0x3f 71 }; 72 73 /* 74 * func field of spec3 opcode. 75 */ 76 enum spec3_op { 77 ext_op, dextm_op, dextu_op, dext_op, 78 ins_op, dinsm_op, dinsu_op, dins_op, 79 yield_op = 0x09, lx_op = 0x0a, 80 lwle_op = 0x19, lwre_op = 0x1a, 81 cachee_op = 0x1b, sbe_op = 0x1c, 82 she_op = 0x1d, sce_op = 0x1e, 83 swe_op = 0x1f, bshfl_op = 0x20, 84 swle_op = 0x21, swre_op = 0x22, 85 prefe_op = 0x23, dbshfl_op = 0x24, 86 lbue_op = 0x28, lhue_op = 0x29, 87 lbe_op = 0x2c, lhe_op = 0x2d, 88 lle_op = 0x2e, lwe_op = 0x2f, 89 rdhwr_op = 0x3b 90 }; 91 92 /* 93 * rt field of bcond opcodes. 94 */ 95 enum rt_op { 96 bltz_op, bgez_op, bltzl_op, bgezl_op, 97 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, 98 tgei_op, tgeiu_op, tlti_op, tltiu_op, 99 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, 100 bltzal_op, bgezal_op, bltzall_op, bgezall_op, 101 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17, 102 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b, 103 bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f 104 }; 105 106 /* 107 * rs field of cop opcodes. 108 */ 109 enum cop_op { 110 mfc_op = 0x00, dmfc_op = 0x01, 111 cfc_op = 0x02, mfhc_op = 0x03, 112 mtc_op = 0x04, dmtc_op = 0x05, 113 ctc_op = 0x06, mthc_op = 0x07, 114 bc_op = 0x08, cop_op = 0x10, 115 copm_op = 0x18 116 }; 117 118 /* 119 * rt field of cop.bc_op opcodes 120 */ 121 enum bcop_op { 122 bcf_op, bct_op, bcfl_op, bctl_op 123 }; 124 125 /* 126 * func field of cop0 coi opcodes. 127 */ 128 enum cop0_coi_func { 129 tlbr_op = 0x01, tlbwi_op = 0x02, 130 tlbwr_op = 0x06, tlbp_op = 0x08, 131 rfe_op = 0x10, eret_op = 0x18, 132 wait_op = 0x20, 133 }; 134 135 /* 136 * func field of cop0 com opcodes. 137 */ 138 enum cop0_com_func { 139 tlbr1_op = 0x01, tlbw_op = 0x02, 140 tlbp1_op = 0x08, dctr_op = 0x09, 141 dctw_op = 0x0a 142 }; 143 144 /* 145 * fmt field of cop1 opcodes. 146 */ 147 enum cop1_fmt { 148 s_fmt, d_fmt, e_fmt, q_fmt, 149 w_fmt, l_fmt 150 }; 151 152 /* 153 * func field of cop1 instructions using d, s or w format. 154 */ 155 enum cop1_sdw_func { 156 fadd_op = 0x00, fsub_op = 0x01, 157 fmul_op = 0x02, fdiv_op = 0x03, 158 fsqrt_op = 0x04, fabs_op = 0x05, 159 fmov_op = 0x06, fneg_op = 0x07, 160 froundl_op = 0x08, ftruncl_op = 0x09, 161 fceill_op = 0x0a, ffloorl_op = 0x0b, 162 fround_op = 0x0c, ftrunc_op = 0x0d, 163 fceil_op = 0x0e, ffloor_op = 0x0f, 164 fmovc_op = 0x11, fmovz_op = 0x12, 165 fmovn_op = 0x13, frecip_op = 0x15, 166 frsqrt_op = 0x16, fcvts_op = 0x20, 167 fcvtd_op = 0x21, fcvte_op = 0x22, 168 fcvtw_op = 0x24, fcvtl_op = 0x25, 169 fcmp_op = 0x30 170 }; 171 172 /* 173 * func field of cop1x opcodes (MIPS IV). 174 */ 175 enum cop1x_func { 176 lwxc1_op = 0x00, ldxc1_op = 0x01, 177 swxc1_op = 0x08, sdxc1_op = 0x09, 178 pfetch_op = 0x0f, madd_s_op = 0x20, 179 madd_d_op = 0x21, madd_e_op = 0x22, 180 msub_s_op = 0x28, msub_d_op = 0x29, 181 msub_e_op = 0x2a, nmadd_s_op = 0x30, 182 nmadd_d_op = 0x31, nmadd_e_op = 0x32, 183 nmsub_s_op = 0x38, nmsub_d_op = 0x39, 184 nmsub_e_op = 0x3a 185 }; 186 187 /* 188 * func field for mad opcodes (MIPS IV). 189 */ 190 enum mad_func { 191 madd_fp_op = 0x08, msub_fp_op = 0x0a, 192 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e 193 }; 194 195 /* 196 * func field for special3 lx opcodes (Cavium Octeon). 197 */ 198 enum lx_func { 199 lwx_op = 0x00, 200 lhx_op = 0x04, 201 lbux_op = 0x06, 202 ldx_op = 0x08, 203 lwux_op = 0x10, 204 lhux_op = 0x14, 205 lbx_op = 0x16, 206 }; 207 208 /* 209 * BSHFL opcodes 210 */ 211 enum bshfl_func { 212 wsbh_op = 0x2, 213 dshd_op = 0x5, 214 seb_op = 0x10, 215 seh_op = 0x18, 216 }; 217 218 /* 219 * (microMIPS) Major opcodes. 220 */ 221 enum mm_major_op { 222 mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op, 223 mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op, 224 mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op, 225 mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op, 226 mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op, 227 mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op, 228 mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op, 229 mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op, 230 mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op, 231 mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op, 232 mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op, 233 mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op, 234 mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op, 235 mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op, 236 mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op, 237 mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op, 238 }; 239 240 /* 241 * (microMIPS) POOL32I minor opcodes. 242 */ 243 enum mm_32i_minor_op { 244 mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op, 245 mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op, 246 mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op, 247 mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op, 248 mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op, 249 mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op, 250 mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op, 251 mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op, 252 mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op, 253 }; 254 255 /* 256 * (microMIPS) POOL32A minor opcodes. 257 */ 258 enum mm_32a_minor_op { 259 mm_sll32_op = 0x000, 260 mm_ins_op = 0x00c, 261 mm_sllv32_op = 0x010, 262 mm_ext_op = 0x02c, 263 mm_pool32axf_op = 0x03c, 264 mm_srl32_op = 0x040, 265 mm_sra_op = 0x080, 266 mm_srlv32_op = 0x090, 267 mm_rotr_op = 0x0c0, 268 mm_lwxs_op = 0x118, 269 mm_addu32_op = 0x150, 270 mm_subu32_op = 0x1d0, 271 mm_wsbh_op = 0x1ec, 272 mm_mul_op = 0x210, 273 mm_and_op = 0x250, 274 mm_or32_op = 0x290, 275 mm_xor32_op = 0x310, 276 mm_sltu_op = 0x390, 277 }; 278 279 /* 280 * (microMIPS) POOL32B functions. 281 */ 282 enum mm_32b_func { 283 mm_lwc2_func = 0x0, 284 mm_lwp_func = 0x1, 285 mm_ldc2_func = 0x2, 286 mm_ldp_func = 0x4, 287 mm_lwm32_func = 0x5, 288 mm_cache_func = 0x6, 289 mm_ldm_func = 0x7, 290 mm_swc2_func = 0x8, 291 mm_swp_func = 0x9, 292 mm_sdc2_func = 0xa, 293 mm_sdp_func = 0xc, 294 mm_swm32_func = 0xd, 295 mm_sdm_func = 0xf, 296 }; 297 298 /* 299 * (microMIPS) POOL32C functions. 300 */ 301 enum mm_32c_func { 302 mm_pref_func = 0x2, 303 mm_ll_func = 0x3, 304 mm_swr_func = 0x9, 305 mm_sc_func = 0xb, 306 mm_lwu_func = 0xe, 307 }; 308 309 /* 310 * (microMIPS) POOL32AXF minor opcodes. 311 */ 312 enum mm_32axf_minor_op { 313 mm_mfc0_op = 0x003, 314 mm_mtc0_op = 0x00b, 315 mm_tlbp_op = 0x00d, 316 mm_mfhi32_op = 0x035, 317 mm_jalr_op = 0x03c, 318 mm_tlbr_op = 0x04d, 319 mm_jalrhb_op = 0x07c, 320 mm_tlbwi_op = 0x08d, 321 mm_tlbwr_op = 0x0cd, 322 mm_jalrs_op = 0x13c, 323 mm_jalrshb_op = 0x17c, 324 mm_sync_op = 0x1ad, 325 mm_syscall_op = 0x22d, 326 mm_wait_op = 0x24d, 327 mm_eret_op = 0x3cd, 328 mm_divu_op = 0x5dc, 329 }; 330 331 /* 332 * (microMIPS) POOL32F minor opcodes. 333 */ 334 enum mm_32f_minor_op { 335 mm_32f_00_op = 0x00, 336 mm_32f_01_op = 0x01, 337 mm_32f_02_op = 0x02, 338 mm_32f_10_op = 0x08, 339 mm_32f_11_op = 0x09, 340 mm_32f_12_op = 0x0a, 341 mm_32f_20_op = 0x10, 342 mm_32f_30_op = 0x18, 343 mm_32f_40_op = 0x20, 344 mm_32f_41_op = 0x21, 345 mm_32f_42_op = 0x22, 346 mm_32f_50_op = 0x28, 347 mm_32f_51_op = 0x29, 348 mm_32f_52_op = 0x2a, 349 mm_32f_60_op = 0x30, 350 mm_32f_70_op = 0x38, 351 mm_32f_73_op = 0x3b, 352 mm_32f_74_op = 0x3c, 353 }; 354 355 /* 356 * (microMIPS) POOL32F secondary minor opcodes. 357 */ 358 enum mm_32f_10_minor_op { 359 mm_lwxc1_op = 0x1, 360 mm_swxc1_op, 361 mm_ldxc1_op, 362 mm_sdxc1_op, 363 mm_luxc1_op, 364 mm_suxc1_op, 365 }; 366 367 enum mm_32f_func { 368 mm_lwxc1_func = 0x048, 369 mm_swxc1_func = 0x088, 370 mm_ldxc1_func = 0x0c8, 371 mm_sdxc1_func = 0x108, 372 }; 373 374 /* 375 * (microMIPS) POOL32F secondary minor opcodes. 376 */ 377 enum mm_32f_40_minor_op { 378 mm_fmovf_op, 379 mm_fmovt_op, 380 }; 381 382 /* 383 * (microMIPS) POOL32F secondary minor opcodes. 384 */ 385 enum mm_32f_60_minor_op { 386 mm_fadd_op, 387 mm_fsub_op, 388 mm_fmul_op, 389 mm_fdiv_op, 390 }; 391 392 /* 393 * (microMIPS) POOL32F secondary minor opcodes. 394 */ 395 enum mm_32f_70_minor_op { 396 mm_fmovn_op, 397 mm_fmovz_op, 398 }; 399 400 /* 401 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F. 402 */ 403 enum mm_32f_73_minor_op { 404 mm_fmov0_op = 0x01, 405 mm_fcvtl_op = 0x04, 406 mm_movf0_op = 0x05, 407 mm_frsqrt_op = 0x08, 408 mm_ffloorl_op = 0x0c, 409 mm_fabs0_op = 0x0d, 410 mm_fcvtw_op = 0x24, 411 mm_movt0_op = 0x25, 412 mm_fsqrt_op = 0x28, 413 mm_ffloorw_op = 0x2c, 414 mm_fneg0_op = 0x2d, 415 mm_cfc1_op = 0x40, 416 mm_frecip_op = 0x48, 417 mm_fceill_op = 0x4c, 418 mm_fcvtd0_op = 0x4d, 419 mm_ctc1_op = 0x60, 420 mm_fceilw_op = 0x6c, 421 mm_fcvts0_op = 0x6d, 422 mm_mfc1_op = 0x80, 423 mm_fmov1_op = 0x81, 424 mm_movf1_op = 0x85, 425 mm_ftruncl_op = 0x8c, 426 mm_fabs1_op = 0x8d, 427 mm_mtc1_op = 0xa0, 428 mm_movt1_op = 0xa5, 429 mm_ftruncw_op = 0xac, 430 mm_fneg1_op = 0xad, 431 mm_mfhc1_op = 0xc0, 432 mm_froundl_op = 0xcc, 433 mm_fcvtd1_op = 0xcd, 434 mm_mthc1_op = 0xe0, 435 mm_froundw_op = 0xec, 436 mm_fcvts1_op = 0xed, 437 }; 438 439 /* 440 * (microMIPS) POOL16C minor opcodes. 441 */ 442 enum mm_16c_minor_op { 443 mm_lwm16_op = 0x04, 444 mm_swm16_op = 0x05, 445 mm_jr16_op = 0x0c, 446 mm_jrc_op = 0x0d, 447 mm_jalr16_op = 0x0e, 448 mm_jalrs16_op = 0x0f, 449 mm_jraddiusp_op = 0x18, 450 }; 451 452 /* 453 * (microMIPS) POOL16D minor opcodes. 454 */ 455 enum mm_16d_minor_op { 456 mm_addius5_func, 457 mm_addiusp_func, 458 }; 459 460 /* 461 * (MIPS16e) opcodes. 462 */ 463 enum MIPS16e_ops { 464 MIPS16e_jal_op = 003, 465 MIPS16e_ld_op = 007, 466 MIPS16e_i8_op = 014, 467 MIPS16e_sd_op = 017, 468 MIPS16e_lb_op = 020, 469 MIPS16e_lh_op = 021, 470 MIPS16e_lwsp_op = 022, 471 MIPS16e_lw_op = 023, 472 MIPS16e_lbu_op = 024, 473 MIPS16e_lhu_op = 025, 474 MIPS16e_lwpc_op = 026, 475 MIPS16e_lwu_op = 027, 476 MIPS16e_sb_op = 030, 477 MIPS16e_sh_op = 031, 478 MIPS16e_swsp_op = 032, 479 MIPS16e_sw_op = 033, 480 MIPS16e_rr_op = 035, 481 MIPS16e_extend_op = 036, 482 MIPS16e_i64_op = 037, 483 }; 484 485 enum MIPS16e_i64_func { 486 MIPS16e_ldsp_func, 487 MIPS16e_sdsp_func, 488 MIPS16e_sdrasp_func, 489 MIPS16e_dadjsp_func, 490 MIPS16e_ldpc_func, 491 }; 492 493 enum MIPS16e_rr_func { 494 MIPS16e_jr_func, 495 }; 496 497 enum MIPS6e_i8_func { 498 MIPS16e_swrasp_func = 02, 499 }; 500 501 /* 502 * (microMIPS & MIPS16e) NOP instruction. 503 */ 504 #define MM_NOP16 0x0c00 505 506 struct j_format { 507 __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */ 508 __BITFIELD_FIELD(unsigned int target : 26, 509 ;)) 510 }; 511 512 struct i_format { /* signed immediate format */ 513 __BITFIELD_FIELD(unsigned int opcode : 6, 514 __BITFIELD_FIELD(unsigned int rs : 5, 515 __BITFIELD_FIELD(unsigned int rt : 5, 516 __BITFIELD_FIELD(signed int simmediate : 16, 517 ;)))) 518 }; 519 520 struct u_format { /* unsigned immediate format */ 521 __BITFIELD_FIELD(unsigned int opcode : 6, 522 __BITFIELD_FIELD(unsigned int rs : 5, 523 __BITFIELD_FIELD(unsigned int rt : 5, 524 __BITFIELD_FIELD(unsigned int uimmediate : 16, 525 ;)))) 526 }; 527 528 struct c_format { /* Cache (>= R6000) format */ 529 __BITFIELD_FIELD(unsigned int opcode : 6, 530 __BITFIELD_FIELD(unsigned int rs : 5, 531 __BITFIELD_FIELD(unsigned int c_op : 3, 532 __BITFIELD_FIELD(unsigned int cache : 2, 533 __BITFIELD_FIELD(unsigned int simmediate : 16, 534 ;))))) 535 }; 536 537 struct r_format { /* Register format */ 538 __BITFIELD_FIELD(unsigned int opcode : 6, 539 __BITFIELD_FIELD(unsigned int rs : 5, 540 __BITFIELD_FIELD(unsigned int rt : 5, 541 __BITFIELD_FIELD(unsigned int rd : 5, 542 __BITFIELD_FIELD(unsigned int re : 5, 543 __BITFIELD_FIELD(unsigned int func : 6, 544 ;)))))) 545 }; 546 547 struct p_format { /* Performance counter format (R10000) */ 548 __BITFIELD_FIELD(unsigned int opcode : 6, 549 __BITFIELD_FIELD(unsigned int rs : 5, 550 __BITFIELD_FIELD(unsigned int rt : 5, 551 __BITFIELD_FIELD(unsigned int rd : 5, 552 __BITFIELD_FIELD(unsigned int re : 5, 553 __BITFIELD_FIELD(unsigned int func : 6, 554 ;)))))) 555 }; 556 557 struct f_format { /* FPU register format */ 558 __BITFIELD_FIELD(unsigned int opcode : 6, 559 __BITFIELD_FIELD(unsigned int : 1, 560 __BITFIELD_FIELD(unsigned int fmt : 4, 561 __BITFIELD_FIELD(unsigned int rt : 5, 562 __BITFIELD_FIELD(unsigned int rd : 5, 563 __BITFIELD_FIELD(unsigned int re : 5, 564 __BITFIELD_FIELD(unsigned int func : 6, 565 ;))))))) 566 }; 567 568 struct ma_format { /* FPU multiply and add format (MIPS IV) */ 569 __BITFIELD_FIELD(unsigned int opcode : 6, 570 __BITFIELD_FIELD(unsigned int fr : 5, 571 __BITFIELD_FIELD(unsigned int ft : 5, 572 __BITFIELD_FIELD(unsigned int fs : 5, 573 __BITFIELD_FIELD(unsigned int fd : 5, 574 __BITFIELD_FIELD(unsigned int func : 4, 575 __BITFIELD_FIELD(unsigned int fmt : 2, 576 ;))))))) 577 }; 578 579 struct b_format { /* BREAK and SYSCALL */ 580 __BITFIELD_FIELD(unsigned int opcode : 6, 581 __BITFIELD_FIELD(unsigned int code : 20, 582 __BITFIELD_FIELD(unsigned int func : 6, 583 ;))) 584 }; 585 586 struct ps_format { /* MIPS-3D / paired single format */ 587 __BITFIELD_FIELD(unsigned int opcode : 6, 588 __BITFIELD_FIELD(unsigned int rs : 5, 589 __BITFIELD_FIELD(unsigned int ft : 5, 590 __BITFIELD_FIELD(unsigned int fs : 5, 591 __BITFIELD_FIELD(unsigned int fd : 5, 592 __BITFIELD_FIELD(unsigned int func : 6, 593 ;)))))) 594 }; 595 596 struct v_format { /* MDMX vector format */ 597 __BITFIELD_FIELD(unsigned int opcode : 6, 598 __BITFIELD_FIELD(unsigned int sel : 4, 599 __BITFIELD_FIELD(unsigned int fmt : 1, 600 __BITFIELD_FIELD(unsigned int vt : 5, 601 __BITFIELD_FIELD(unsigned int vs : 5, 602 __BITFIELD_FIELD(unsigned int vd : 5, 603 __BITFIELD_FIELD(unsigned int func : 6, 604 ;))))))) 605 }; 606 607 struct spec3_format { /* SPEC3 */ 608 __BITFIELD_FIELD(unsigned int opcode:6, 609 __BITFIELD_FIELD(unsigned int rs:5, 610 __BITFIELD_FIELD(unsigned int rt:5, 611 __BITFIELD_FIELD(signed int simmediate:9, 612 __BITFIELD_FIELD(unsigned int func:7, 613 ;))))) 614 }; 615 616 /* 617 * microMIPS instruction formats (32-bit length) 618 * 619 * NOTE: 620 * Parenthesis denote whether the format is a microMIPS instruction or 621 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE. 622 */ 623 struct fb_format { /* FPU branch format (MIPS32) */ 624 __BITFIELD_FIELD(unsigned int opcode : 6, 625 __BITFIELD_FIELD(unsigned int bc : 5, 626 __BITFIELD_FIELD(unsigned int cc : 3, 627 __BITFIELD_FIELD(unsigned int flag : 2, 628 __BITFIELD_FIELD(signed int simmediate : 16, 629 ;))))) 630 }; 631 632 struct fp0_format { /* FPU multiply and add format (MIPS32) */ 633 __BITFIELD_FIELD(unsigned int opcode : 6, 634 __BITFIELD_FIELD(unsigned int fmt : 5, 635 __BITFIELD_FIELD(unsigned int ft : 5, 636 __BITFIELD_FIELD(unsigned int fs : 5, 637 __BITFIELD_FIELD(unsigned int fd : 5, 638 __BITFIELD_FIELD(unsigned int func : 6, 639 ;)))))) 640 }; 641 642 struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ 643 __BITFIELD_FIELD(unsigned int opcode : 6, 644 __BITFIELD_FIELD(unsigned int ft : 5, 645 __BITFIELD_FIELD(unsigned int fs : 5, 646 __BITFIELD_FIELD(unsigned int fd : 5, 647 __BITFIELD_FIELD(unsigned int fmt : 3, 648 __BITFIELD_FIELD(unsigned int op : 2, 649 __BITFIELD_FIELD(unsigned int func : 6, 650 ;))))))) 651 }; 652 653 struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ 654 __BITFIELD_FIELD(unsigned int opcode : 6, 655 __BITFIELD_FIELD(unsigned int op : 5, 656 __BITFIELD_FIELD(unsigned int rt : 5, 657 __BITFIELD_FIELD(unsigned int fs : 5, 658 __BITFIELD_FIELD(unsigned int fd : 5, 659 __BITFIELD_FIELD(unsigned int func : 6, 660 ;)))))) 661 }; 662 663 struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ 664 __BITFIELD_FIELD(unsigned int opcode : 6, 665 __BITFIELD_FIELD(unsigned int rt : 5, 666 __BITFIELD_FIELD(unsigned int fs : 5, 667 __BITFIELD_FIELD(unsigned int fmt : 2, 668 __BITFIELD_FIELD(unsigned int op : 8, 669 __BITFIELD_FIELD(unsigned int func : 6, 670 ;)))))) 671 }; 672 673 struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ 674 __BITFIELD_FIELD(unsigned int opcode : 6, 675 __BITFIELD_FIELD(unsigned int fd : 5, 676 __BITFIELD_FIELD(unsigned int fs : 5, 677 __BITFIELD_FIELD(unsigned int cc : 3, 678 __BITFIELD_FIELD(unsigned int zero : 2, 679 __BITFIELD_FIELD(unsigned int fmt : 2, 680 __BITFIELD_FIELD(unsigned int op : 3, 681 __BITFIELD_FIELD(unsigned int func : 6, 682 ;)))))))) 683 }; 684 685 struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ 686 __BITFIELD_FIELD(unsigned int opcode : 6, 687 __BITFIELD_FIELD(unsigned int rt : 5, 688 __BITFIELD_FIELD(unsigned int fs : 5, 689 __BITFIELD_FIELD(unsigned int fmt : 3, 690 __BITFIELD_FIELD(unsigned int op : 7, 691 __BITFIELD_FIELD(unsigned int func : 6, 692 ;)))))) 693 }; 694 695 struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ 696 __BITFIELD_FIELD(unsigned int opcode : 6, 697 __BITFIELD_FIELD(unsigned int rt : 5, 698 __BITFIELD_FIELD(unsigned int fs : 5, 699 __BITFIELD_FIELD(unsigned int cc : 3, 700 __BITFIELD_FIELD(unsigned int fmt : 3, 701 __BITFIELD_FIELD(unsigned int cond : 4, 702 __BITFIELD_FIELD(unsigned int func : 6, 703 ;))))))) 704 }; 705 706 struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ 707 __BITFIELD_FIELD(unsigned int opcode : 6, 708 __BITFIELD_FIELD(unsigned int index : 5, 709 __BITFIELD_FIELD(unsigned int base : 5, 710 __BITFIELD_FIELD(unsigned int fd : 5, 711 __BITFIELD_FIELD(unsigned int op : 5, 712 __BITFIELD_FIELD(unsigned int func : 6, 713 ;)))))) 714 }; 715 716 struct fp6_format { /* FPU madd and msub format (MIPS IV) */ 717 __BITFIELD_FIELD(unsigned int opcode : 6, 718 __BITFIELD_FIELD(unsigned int fr : 5, 719 __BITFIELD_FIELD(unsigned int ft : 5, 720 __BITFIELD_FIELD(unsigned int fs : 5, 721 __BITFIELD_FIELD(unsigned int fd : 5, 722 __BITFIELD_FIELD(unsigned int func : 6, 723 ;)))))) 724 }; 725 726 struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ 727 __BITFIELD_FIELD(unsigned int opcode : 6, 728 __BITFIELD_FIELD(unsigned int ft : 5, 729 __BITFIELD_FIELD(unsigned int fs : 5, 730 __BITFIELD_FIELD(unsigned int fd : 5, 731 __BITFIELD_FIELD(unsigned int fr : 5, 732 __BITFIELD_FIELD(unsigned int func : 6, 733 ;)))))) 734 }; 735 736 struct mm_i_format { /* Immediate format (microMIPS) */ 737 __BITFIELD_FIELD(unsigned int opcode : 6, 738 __BITFIELD_FIELD(unsigned int rt : 5, 739 __BITFIELD_FIELD(unsigned int rs : 5, 740 __BITFIELD_FIELD(signed int simmediate : 16, 741 ;)))) 742 }; 743 744 struct mm_m_format { /* Multi-word load/store format (microMIPS) */ 745 __BITFIELD_FIELD(unsigned int opcode : 6, 746 __BITFIELD_FIELD(unsigned int rd : 5, 747 __BITFIELD_FIELD(unsigned int base : 5, 748 __BITFIELD_FIELD(unsigned int func : 4, 749 __BITFIELD_FIELD(signed int simmediate : 12, 750 ;))))) 751 }; 752 753 struct mm_x_format { /* Scaled indexed load format (microMIPS) */ 754 __BITFIELD_FIELD(unsigned int opcode : 6, 755 __BITFIELD_FIELD(unsigned int index : 5, 756 __BITFIELD_FIELD(unsigned int base : 5, 757 __BITFIELD_FIELD(unsigned int rd : 5, 758 __BITFIELD_FIELD(unsigned int func : 11, 759 ;))))) 760 }; 761 762 /* 763 * microMIPS instruction formats (16-bit length) 764 */ 765 struct mm_b0_format { /* Unconditional branch format (microMIPS) */ 766 __BITFIELD_FIELD(unsigned int opcode : 6, 767 __BITFIELD_FIELD(signed int simmediate : 10, 768 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 769 ;))) 770 }; 771 772 struct mm_b1_format { /* Conditional branch format (microMIPS) */ 773 __BITFIELD_FIELD(unsigned int opcode : 6, 774 __BITFIELD_FIELD(unsigned int rs : 3, 775 __BITFIELD_FIELD(signed int simmediate : 7, 776 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 777 ;)))) 778 }; 779 780 struct mm16_m_format { /* Multi-word load/store format */ 781 __BITFIELD_FIELD(unsigned int opcode : 6, 782 __BITFIELD_FIELD(unsigned int func : 4, 783 __BITFIELD_FIELD(unsigned int rlist : 2, 784 __BITFIELD_FIELD(unsigned int imm : 4, 785 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 786 ;))))) 787 }; 788 789 struct mm16_rb_format { /* Signed immediate format */ 790 __BITFIELD_FIELD(unsigned int opcode : 6, 791 __BITFIELD_FIELD(unsigned int rt : 3, 792 __BITFIELD_FIELD(unsigned int base : 3, 793 __BITFIELD_FIELD(signed int simmediate : 4, 794 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 795 ;))))) 796 }; 797 798 struct mm16_r3_format { /* Load from global pointer format */ 799 __BITFIELD_FIELD(unsigned int opcode : 6, 800 __BITFIELD_FIELD(unsigned int rt : 3, 801 __BITFIELD_FIELD(signed int simmediate : 7, 802 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 803 ;)))) 804 }; 805 806 struct mm16_r5_format { /* Load/store from stack pointer format */ 807 __BITFIELD_FIELD(unsigned int opcode : 6, 808 __BITFIELD_FIELD(unsigned int rt : 5, 809 __BITFIELD_FIELD(signed int simmediate : 5, 810 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 811 ;)))) 812 }; 813 814 /* 815 * MIPS16e instruction formats (16-bit length) 816 */ 817 struct m16e_rr { 818 __BITFIELD_FIELD(unsigned int opcode : 5, 819 __BITFIELD_FIELD(unsigned int rx : 3, 820 __BITFIELD_FIELD(unsigned int nd : 1, 821 __BITFIELD_FIELD(unsigned int l : 1, 822 __BITFIELD_FIELD(unsigned int ra : 1, 823 __BITFIELD_FIELD(unsigned int func : 5, 824 ;)))))) 825 }; 826 827 struct m16e_jal { 828 __BITFIELD_FIELD(unsigned int opcode : 5, 829 __BITFIELD_FIELD(unsigned int x : 1, 830 __BITFIELD_FIELD(unsigned int imm20_16 : 5, 831 __BITFIELD_FIELD(signed int imm25_21 : 5, 832 ;)))) 833 }; 834 835 struct m16e_i64 { 836 __BITFIELD_FIELD(unsigned int opcode : 5, 837 __BITFIELD_FIELD(unsigned int func : 3, 838 __BITFIELD_FIELD(unsigned int imm : 8, 839 ;))) 840 }; 841 842 struct m16e_ri64 { 843 __BITFIELD_FIELD(unsigned int opcode : 5, 844 __BITFIELD_FIELD(unsigned int func : 3, 845 __BITFIELD_FIELD(unsigned int ry : 3, 846 __BITFIELD_FIELD(unsigned int imm : 5, 847 ;)))) 848 }; 849 850 struct m16e_ri { 851 __BITFIELD_FIELD(unsigned int opcode : 5, 852 __BITFIELD_FIELD(unsigned int rx : 3, 853 __BITFIELD_FIELD(unsigned int imm : 8, 854 ;))) 855 }; 856 857 struct m16e_rri { 858 __BITFIELD_FIELD(unsigned int opcode : 5, 859 __BITFIELD_FIELD(unsigned int rx : 3, 860 __BITFIELD_FIELD(unsigned int ry : 3, 861 __BITFIELD_FIELD(unsigned int imm : 5, 862 ;)))) 863 }; 864 865 struct m16e_i8 { 866 __BITFIELD_FIELD(unsigned int opcode : 5, 867 __BITFIELD_FIELD(unsigned int func : 3, 868 __BITFIELD_FIELD(unsigned int imm : 8, 869 ;))) 870 }; 871 872 union mips_instruction { 873 unsigned int word; 874 unsigned short halfword[2]; 875 unsigned char byte[4]; 876 struct j_format j_format; 877 struct i_format i_format; 878 struct u_format u_format; 879 struct c_format c_format; 880 struct r_format r_format; 881 struct p_format p_format; 882 struct f_format f_format; 883 struct ma_format ma_format; 884 struct b_format b_format; 885 struct ps_format ps_format; 886 struct v_format v_format; 887 struct spec3_format spec3_format; 888 struct fb_format fb_format; 889 struct fp0_format fp0_format; 890 struct mm_fp0_format mm_fp0_format; 891 struct fp1_format fp1_format; 892 struct mm_fp1_format mm_fp1_format; 893 struct mm_fp2_format mm_fp2_format; 894 struct mm_fp3_format mm_fp3_format; 895 struct mm_fp4_format mm_fp4_format; 896 struct mm_fp5_format mm_fp5_format; 897 struct fp6_format fp6_format; 898 struct mm_fp6_format mm_fp6_format; 899 struct mm_i_format mm_i_format; 900 struct mm_m_format mm_m_format; 901 struct mm_x_format mm_x_format; 902 struct mm_b0_format mm_b0_format; 903 struct mm_b1_format mm_b1_format; 904 struct mm16_m_format mm16_m_format ; 905 struct mm16_rb_format mm16_rb_format; 906 struct mm16_r3_format mm16_r3_format; 907 struct mm16_r5_format mm16_r5_format; 908 }; 909 910 union mips16e_instruction { 911 unsigned int full : 16; 912 struct m16e_rr rr; 913 struct m16e_jal jal; 914 struct m16e_i64 i64; 915 struct m16e_ri64 ri64; 916 struct m16e_ri ri; 917 struct m16e_rri rri; 918 struct m16e_i8 i8; 919 }; 920 921 #endif /* _UAPI_ASM_INST_H */ 922