1 /* 2 * Format of an instruction in memory. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 2000 by Ralf Baechle 9 * Copyright (C) 2006 by Thiemo Seufer 10 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 11 * Copyright (C) 2014 Imagination Technologies Ltd. 12 */ 13 #ifndef _UAPI_ASM_INST_H 14 #define _UAPI_ASM_INST_H 15 16 #include <asm/bitfield.h> 17 18 /* 19 * Major opcodes; before MIPS IV cop1x was called cop3. 20 */ 21 enum major_op { 22 spec_op, bcond_op, j_op, jal_op, 23 beq_op, bne_op, blez_op, bgtz_op, 24 addi_op, addiu_op, slti_op, sltiu_op, 25 andi_op, ori_op, xori_op, lui_op, 26 cop0_op, cop1_op, cop2_op, cop1x_op, 27 beql_op, bnel_op, blezl_op, bgtzl_op, 28 daddi_op, daddiu_op, ldl_op, ldr_op, 29 spec2_op, jalx_op, mdmx_op, spec3_op, 30 lb_op, lh_op, lwl_op, lw_op, 31 lbu_op, lhu_op, lwr_op, lwu_op, 32 sb_op, sh_op, swl_op, sw_op, 33 sdl_op, sdr_op, swr_op, cache_op, 34 ll_op, lwc1_op, lwc2_op, pref_op, 35 lld_op, ldc1_op, ldc2_op, ld_op, 36 sc_op, swc1_op, swc2_op, major_3b_op, 37 scd_op, sdc1_op, sdc2_op, sd_op 38 }; 39 40 /* 41 * func field of spec opcode. 42 */ 43 enum spec_op { 44 sll_op, movc_op, srl_op, sra_op, 45 sllv_op, pmon_op, srlv_op, srav_op, 46 jr_op, jalr_op, movz_op, movn_op, 47 syscall_op, break_op, spim_op, sync_op, 48 mfhi_op, mthi_op, mflo_op, mtlo_op, 49 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, 50 mult_op, multu_op, div_op, divu_op, 51 dmult_op, dmultu_op, ddiv_op, ddivu_op, 52 add_op, addu_op, sub_op, subu_op, 53 and_op, or_op, xor_op, nor_op, 54 spec3_unused_op, spec4_unused_op, slt_op, sltu_op, 55 dadd_op, daddu_op, dsub_op, dsubu_op, 56 tge_op, tgeu_op, tlt_op, tltu_op, 57 teq_op, spec5_unused_op, tne_op, spec6_unused_op, 58 dsll_op, spec7_unused_op, dsrl_op, dsra_op, 59 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op 60 }; 61 62 /* 63 * func field of spec2 opcode. 64 */ 65 enum spec2_op { 66 madd_op, maddu_op, mul_op, spec2_3_unused_op, 67 msub_op, msubu_op, /* more unused ops */ 68 clz_op = 0x20, clo_op, 69 dclz_op = 0x24, dclo_op, 70 sdbpp_op = 0x3f 71 }; 72 73 /* 74 * func field of spec3 opcode. 75 */ 76 enum spec3_op { 77 ext_op, dextm_op, dextu_op, dext_op, 78 ins_op, dinsm_op, dinsu_op, dins_op, 79 lx_op = 0x0a, lwle_op = 0x19, 80 lwre_op = 0x1a, cachee_op = 0x1b, 81 sbe_op = 0x1c, she_op = 0x1d, 82 sce_op = 0x1e, swe_op = 0x1f, 83 bshfl_op = 0x20, swle_op = 0x21, 84 swre_op = 0x22, prefe_op = 0x23, 85 dbshfl_op = 0x24, lbue_op = 0x28, 86 lhue_op = 0x29, lbe_op = 0x2c, 87 lhe_op = 0x2d, lle_op = 0x2e, 88 lwe_op = 0x2f, rdhwr_op = 0x3b 89 }; 90 91 /* 92 * rt field of bcond opcodes. 93 */ 94 enum rt_op { 95 bltz_op, bgez_op, bltzl_op, bgezl_op, 96 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, 97 tgei_op, tgeiu_op, tlti_op, tltiu_op, 98 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, 99 bltzal_op, bgezal_op, bltzall_op, bgezall_op, 100 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17, 101 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b, 102 bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f 103 }; 104 105 /* 106 * rs field of cop opcodes. 107 */ 108 enum cop_op { 109 mfc_op = 0x00, dmfc_op = 0x01, 110 cfc_op = 0x02, mfhc_op = 0x03, 111 mtc_op = 0x04, dmtc_op = 0x05, 112 ctc_op = 0x06, mthc_op = 0x07, 113 bc_op = 0x08, cop_op = 0x10, 114 copm_op = 0x18 115 }; 116 117 /* 118 * rt field of cop.bc_op opcodes 119 */ 120 enum bcop_op { 121 bcf_op, bct_op, bcfl_op, bctl_op 122 }; 123 124 /* 125 * func field of cop0 coi opcodes. 126 */ 127 enum cop0_coi_func { 128 tlbr_op = 0x01, tlbwi_op = 0x02, 129 tlbwr_op = 0x06, tlbp_op = 0x08, 130 rfe_op = 0x10, eret_op = 0x18 131 }; 132 133 /* 134 * func field of cop0 com opcodes. 135 */ 136 enum cop0_com_func { 137 tlbr1_op = 0x01, tlbw_op = 0x02, 138 tlbp1_op = 0x08, dctr_op = 0x09, 139 dctw_op = 0x0a 140 }; 141 142 /* 143 * fmt field of cop1 opcodes. 144 */ 145 enum cop1_fmt { 146 s_fmt, d_fmt, e_fmt, q_fmt, 147 w_fmt, l_fmt 148 }; 149 150 /* 151 * func field of cop1 instructions using d, s or w format. 152 */ 153 enum cop1_sdw_func { 154 fadd_op = 0x00, fsub_op = 0x01, 155 fmul_op = 0x02, fdiv_op = 0x03, 156 fsqrt_op = 0x04, fabs_op = 0x05, 157 fmov_op = 0x06, fneg_op = 0x07, 158 froundl_op = 0x08, ftruncl_op = 0x09, 159 fceill_op = 0x0a, ffloorl_op = 0x0b, 160 fround_op = 0x0c, ftrunc_op = 0x0d, 161 fceil_op = 0x0e, ffloor_op = 0x0f, 162 fmovc_op = 0x11, fmovz_op = 0x12, 163 fmovn_op = 0x13, frecip_op = 0x15, 164 frsqrt_op = 0x16, fcvts_op = 0x20, 165 fcvtd_op = 0x21, fcvte_op = 0x22, 166 fcvtw_op = 0x24, fcvtl_op = 0x25, 167 fcmp_op = 0x30 168 }; 169 170 /* 171 * func field of cop1x opcodes (MIPS IV). 172 */ 173 enum cop1x_func { 174 lwxc1_op = 0x00, ldxc1_op = 0x01, 175 swxc1_op = 0x08, sdxc1_op = 0x09, 176 pfetch_op = 0x0f, madd_s_op = 0x20, 177 madd_d_op = 0x21, madd_e_op = 0x22, 178 msub_s_op = 0x28, msub_d_op = 0x29, 179 msub_e_op = 0x2a, nmadd_s_op = 0x30, 180 nmadd_d_op = 0x31, nmadd_e_op = 0x32, 181 nmsub_s_op = 0x38, nmsub_d_op = 0x39, 182 nmsub_e_op = 0x3a 183 }; 184 185 /* 186 * func field for mad opcodes (MIPS IV). 187 */ 188 enum mad_func { 189 madd_fp_op = 0x08, msub_fp_op = 0x0a, 190 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e 191 }; 192 193 /* 194 * func field for special3 lx opcodes (Cavium Octeon). 195 */ 196 enum lx_func { 197 lwx_op = 0x00, 198 lhx_op = 0x04, 199 lbux_op = 0x06, 200 ldx_op = 0x08, 201 lwux_op = 0x10, 202 lhux_op = 0x14, 203 lbx_op = 0x16, 204 }; 205 206 /* 207 * (microMIPS) Major opcodes. 208 */ 209 enum mm_major_op { 210 mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op, 211 mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op, 212 mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op, 213 mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op, 214 mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op, 215 mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op, 216 mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op, 217 mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op, 218 mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op, 219 mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op, 220 mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op, 221 mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op, 222 mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op, 223 mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op, 224 mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op, 225 mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op, 226 }; 227 228 /* 229 * (microMIPS) POOL32I minor opcodes. 230 */ 231 enum mm_32i_minor_op { 232 mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op, 233 mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op, 234 mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op, 235 mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op, 236 mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op, 237 mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op, 238 mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op, 239 mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op, 240 mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op, 241 }; 242 243 /* 244 * (microMIPS) POOL32A minor opcodes. 245 */ 246 enum mm_32a_minor_op { 247 mm_sll32_op = 0x000, 248 mm_ins_op = 0x00c, 249 mm_ext_op = 0x02c, 250 mm_pool32axf_op = 0x03c, 251 mm_srl32_op = 0x040, 252 mm_sra_op = 0x080, 253 mm_rotr_op = 0x0c0, 254 mm_lwxs_op = 0x118, 255 mm_addu32_op = 0x150, 256 mm_subu32_op = 0x1d0, 257 mm_and_op = 0x250, 258 mm_or32_op = 0x290, 259 mm_xor32_op = 0x310, 260 }; 261 262 /* 263 * (microMIPS) POOL32B functions. 264 */ 265 enum mm_32b_func { 266 mm_lwc2_func = 0x0, 267 mm_lwp_func = 0x1, 268 mm_ldc2_func = 0x2, 269 mm_ldp_func = 0x4, 270 mm_lwm32_func = 0x5, 271 mm_cache_func = 0x6, 272 mm_ldm_func = 0x7, 273 mm_swc2_func = 0x8, 274 mm_swp_func = 0x9, 275 mm_sdc2_func = 0xa, 276 mm_sdp_func = 0xc, 277 mm_swm32_func = 0xd, 278 mm_sdm_func = 0xf, 279 }; 280 281 /* 282 * (microMIPS) POOL32C functions. 283 */ 284 enum mm_32c_func { 285 mm_pref_func = 0x2, 286 mm_ll_func = 0x3, 287 mm_swr_func = 0x9, 288 mm_sc_func = 0xb, 289 mm_lwu_func = 0xe, 290 }; 291 292 /* 293 * (microMIPS) POOL32AXF minor opcodes. 294 */ 295 enum mm_32axf_minor_op { 296 mm_mfc0_op = 0x003, 297 mm_mtc0_op = 0x00b, 298 mm_tlbp_op = 0x00d, 299 mm_jalr_op = 0x03c, 300 mm_tlbr_op = 0x04d, 301 mm_jalrhb_op = 0x07c, 302 mm_tlbwi_op = 0x08d, 303 mm_tlbwr_op = 0x0cd, 304 mm_jalrs_op = 0x13c, 305 mm_jalrshb_op = 0x17c, 306 mm_syscall_op = 0x22d, 307 mm_eret_op = 0x3cd, 308 }; 309 310 /* 311 * (microMIPS) POOL32F minor opcodes. 312 */ 313 enum mm_32f_minor_op { 314 mm_32f_00_op = 0x00, 315 mm_32f_01_op = 0x01, 316 mm_32f_02_op = 0x02, 317 mm_32f_10_op = 0x08, 318 mm_32f_11_op = 0x09, 319 mm_32f_12_op = 0x0a, 320 mm_32f_20_op = 0x10, 321 mm_32f_30_op = 0x18, 322 mm_32f_40_op = 0x20, 323 mm_32f_41_op = 0x21, 324 mm_32f_42_op = 0x22, 325 mm_32f_50_op = 0x28, 326 mm_32f_51_op = 0x29, 327 mm_32f_52_op = 0x2a, 328 mm_32f_60_op = 0x30, 329 mm_32f_70_op = 0x38, 330 mm_32f_73_op = 0x3b, 331 mm_32f_74_op = 0x3c, 332 }; 333 334 /* 335 * (microMIPS) POOL32F secondary minor opcodes. 336 */ 337 enum mm_32f_10_minor_op { 338 mm_lwxc1_op = 0x1, 339 mm_swxc1_op, 340 mm_ldxc1_op, 341 mm_sdxc1_op, 342 mm_luxc1_op, 343 mm_suxc1_op, 344 }; 345 346 enum mm_32f_func { 347 mm_lwxc1_func = 0x048, 348 mm_swxc1_func = 0x088, 349 mm_ldxc1_func = 0x0c8, 350 mm_sdxc1_func = 0x108, 351 }; 352 353 /* 354 * (microMIPS) POOL32F secondary minor opcodes. 355 */ 356 enum mm_32f_40_minor_op { 357 mm_fmovf_op, 358 mm_fmovt_op, 359 }; 360 361 /* 362 * (microMIPS) POOL32F secondary minor opcodes. 363 */ 364 enum mm_32f_60_minor_op { 365 mm_fadd_op, 366 mm_fsub_op, 367 mm_fmul_op, 368 mm_fdiv_op, 369 }; 370 371 /* 372 * (microMIPS) POOL32F secondary minor opcodes. 373 */ 374 enum mm_32f_70_minor_op { 375 mm_fmovn_op, 376 mm_fmovz_op, 377 }; 378 379 /* 380 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F. 381 */ 382 enum mm_32f_73_minor_op { 383 mm_fmov0_op = 0x01, 384 mm_fcvtl_op = 0x04, 385 mm_movf0_op = 0x05, 386 mm_frsqrt_op = 0x08, 387 mm_ffloorl_op = 0x0c, 388 mm_fabs0_op = 0x0d, 389 mm_fcvtw_op = 0x24, 390 mm_movt0_op = 0x25, 391 mm_fsqrt_op = 0x28, 392 mm_ffloorw_op = 0x2c, 393 mm_fneg0_op = 0x2d, 394 mm_cfc1_op = 0x40, 395 mm_frecip_op = 0x48, 396 mm_fceill_op = 0x4c, 397 mm_fcvtd0_op = 0x4d, 398 mm_ctc1_op = 0x60, 399 mm_fceilw_op = 0x6c, 400 mm_fcvts0_op = 0x6d, 401 mm_mfc1_op = 0x80, 402 mm_fmov1_op = 0x81, 403 mm_movf1_op = 0x85, 404 mm_ftruncl_op = 0x8c, 405 mm_fabs1_op = 0x8d, 406 mm_mtc1_op = 0xa0, 407 mm_movt1_op = 0xa5, 408 mm_ftruncw_op = 0xac, 409 mm_fneg1_op = 0xad, 410 mm_mfhc1_op = 0xc0, 411 mm_froundl_op = 0xcc, 412 mm_fcvtd1_op = 0xcd, 413 mm_mthc1_op = 0xe0, 414 mm_froundw_op = 0xec, 415 mm_fcvts1_op = 0xed, 416 }; 417 418 /* 419 * (microMIPS) POOL16C minor opcodes. 420 */ 421 enum mm_16c_minor_op { 422 mm_lwm16_op = 0x04, 423 mm_swm16_op = 0x05, 424 mm_jr16_op = 0x0c, 425 mm_jrc_op = 0x0d, 426 mm_jalr16_op = 0x0e, 427 mm_jalrs16_op = 0x0f, 428 mm_jraddiusp_op = 0x18, 429 }; 430 431 /* 432 * (microMIPS) POOL16D minor opcodes. 433 */ 434 enum mm_16d_minor_op { 435 mm_addius5_func, 436 mm_addiusp_func, 437 }; 438 439 /* 440 * (MIPS16e) opcodes. 441 */ 442 enum MIPS16e_ops { 443 MIPS16e_jal_op = 003, 444 MIPS16e_ld_op = 007, 445 MIPS16e_i8_op = 014, 446 MIPS16e_sd_op = 017, 447 MIPS16e_lb_op = 020, 448 MIPS16e_lh_op = 021, 449 MIPS16e_lwsp_op = 022, 450 MIPS16e_lw_op = 023, 451 MIPS16e_lbu_op = 024, 452 MIPS16e_lhu_op = 025, 453 MIPS16e_lwpc_op = 026, 454 MIPS16e_lwu_op = 027, 455 MIPS16e_sb_op = 030, 456 MIPS16e_sh_op = 031, 457 MIPS16e_swsp_op = 032, 458 MIPS16e_sw_op = 033, 459 MIPS16e_rr_op = 035, 460 MIPS16e_extend_op = 036, 461 MIPS16e_i64_op = 037, 462 }; 463 464 enum MIPS16e_i64_func { 465 MIPS16e_ldsp_func, 466 MIPS16e_sdsp_func, 467 MIPS16e_sdrasp_func, 468 MIPS16e_dadjsp_func, 469 MIPS16e_ldpc_func, 470 }; 471 472 enum MIPS16e_rr_func { 473 MIPS16e_jr_func, 474 }; 475 476 enum MIPS6e_i8_func { 477 MIPS16e_swrasp_func = 02, 478 }; 479 480 /* 481 * (microMIPS & MIPS16e) NOP instruction. 482 */ 483 #define MM_NOP16 0x0c00 484 485 struct j_format { 486 __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */ 487 __BITFIELD_FIELD(unsigned int target : 26, 488 ;)) 489 }; 490 491 struct i_format { /* signed immediate format */ 492 __BITFIELD_FIELD(unsigned int opcode : 6, 493 __BITFIELD_FIELD(unsigned int rs : 5, 494 __BITFIELD_FIELD(unsigned int rt : 5, 495 __BITFIELD_FIELD(signed int simmediate : 16, 496 ;)))) 497 }; 498 499 struct u_format { /* unsigned immediate format */ 500 __BITFIELD_FIELD(unsigned int opcode : 6, 501 __BITFIELD_FIELD(unsigned int rs : 5, 502 __BITFIELD_FIELD(unsigned int rt : 5, 503 __BITFIELD_FIELD(unsigned int uimmediate : 16, 504 ;)))) 505 }; 506 507 struct c_format { /* Cache (>= R6000) format */ 508 __BITFIELD_FIELD(unsigned int opcode : 6, 509 __BITFIELD_FIELD(unsigned int rs : 5, 510 __BITFIELD_FIELD(unsigned int c_op : 3, 511 __BITFIELD_FIELD(unsigned int cache : 2, 512 __BITFIELD_FIELD(unsigned int simmediate : 16, 513 ;))))) 514 }; 515 516 struct r_format { /* Register format */ 517 __BITFIELD_FIELD(unsigned int opcode : 6, 518 __BITFIELD_FIELD(unsigned int rs : 5, 519 __BITFIELD_FIELD(unsigned int rt : 5, 520 __BITFIELD_FIELD(unsigned int rd : 5, 521 __BITFIELD_FIELD(unsigned int re : 5, 522 __BITFIELD_FIELD(unsigned int func : 6, 523 ;)))))) 524 }; 525 526 struct p_format { /* Performance counter format (R10000) */ 527 __BITFIELD_FIELD(unsigned int opcode : 6, 528 __BITFIELD_FIELD(unsigned int rs : 5, 529 __BITFIELD_FIELD(unsigned int rt : 5, 530 __BITFIELD_FIELD(unsigned int rd : 5, 531 __BITFIELD_FIELD(unsigned int re : 5, 532 __BITFIELD_FIELD(unsigned int func : 6, 533 ;)))))) 534 }; 535 536 struct f_format { /* FPU register format */ 537 __BITFIELD_FIELD(unsigned int opcode : 6, 538 __BITFIELD_FIELD(unsigned int : 1, 539 __BITFIELD_FIELD(unsigned int fmt : 4, 540 __BITFIELD_FIELD(unsigned int rt : 5, 541 __BITFIELD_FIELD(unsigned int rd : 5, 542 __BITFIELD_FIELD(unsigned int re : 5, 543 __BITFIELD_FIELD(unsigned int func : 6, 544 ;))))))) 545 }; 546 547 struct ma_format { /* FPU multiply and add format (MIPS IV) */ 548 __BITFIELD_FIELD(unsigned int opcode : 6, 549 __BITFIELD_FIELD(unsigned int fr : 5, 550 __BITFIELD_FIELD(unsigned int ft : 5, 551 __BITFIELD_FIELD(unsigned int fs : 5, 552 __BITFIELD_FIELD(unsigned int fd : 5, 553 __BITFIELD_FIELD(unsigned int func : 4, 554 __BITFIELD_FIELD(unsigned int fmt : 2, 555 ;))))))) 556 }; 557 558 struct b_format { /* BREAK and SYSCALL */ 559 __BITFIELD_FIELD(unsigned int opcode : 6, 560 __BITFIELD_FIELD(unsigned int code : 20, 561 __BITFIELD_FIELD(unsigned int func : 6, 562 ;))) 563 }; 564 565 struct ps_format { /* MIPS-3D / paired single format */ 566 __BITFIELD_FIELD(unsigned int opcode : 6, 567 __BITFIELD_FIELD(unsigned int rs : 5, 568 __BITFIELD_FIELD(unsigned int ft : 5, 569 __BITFIELD_FIELD(unsigned int fs : 5, 570 __BITFIELD_FIELD(unsigned int fd : 5, 571 __BITFIELD_FIELD(unsigned int func : 6, 572 ;)))))) 573 }; 574 575 struct v_format { /* MDMX vector format */ 576 __BITFIELD_FIELD(unsigned int opcode : 6, 577 __BITFIELD_FIELD(unsigned int sel : 4, 578 __BITFIELD_FIELD(unsigned int fmt : 1, 579 __BITFIELD_FIELD(unsigned int vt : 5, 580 __BITFIELD_FIELD(unsigned int vs : 5, 581 __BITFIELD_FIELD(unsigned int vd : 5, 582 __BITFIELD_FIELD(unsigned int func : 6, 583 ;))))))) 584 }; 585 586 struct spec3_format { /* SPEC3 */ 587 __BITFIELD_FIELD(unsigned int opcode:6, 588 __BITFIELD_FIELD(unsigned int rs:5, 589 __BITFIELD_FIELD(unsigned int rt:5, 590 __BITFIELD_FIELD(signed int simmediate:9, 591 __BITFIELD_FIELD(unsigned int func:7, 592 ;))))) 593 }; 594 595 /* 596 * microMIPS instruction formats (32-bit length) 597 * 598 * NOTE: 599 * Parenthesis denote whether the format is a microMIPS instruction or 600 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE. 601 */ 602 struct fb_format { /* FPU branch format (MIPS32) */ 603 __BITFIELD_FIELD(unsigned int opcode : 6, 604 __BITFIELD_FIELD(unsigned int bc : 5, 605 __BITFIELD_FIELD(unsigned int cc : 3, 606 __BITFIELD_FIELD(unsigned int flag : 2, 607 __BITFIELD_FIELD(signed int simmediate : 16, 608 ;))))) 609 }; 610 611 struct fp0_format { /* FPU multiply and add format (MIPS32) */ 612 __BITFIELD_FIELD(unsigned int opcode : 6, 613 __BITFIELD_FIELD(unsigned int fmt : 5, 614 __BITFIELD_FIELD(unsigned int ft : 5, 615 __BITFIELD_FIELD(unsigned int fs : 5, 616 __BITFIELD_FIELD(unsigned int fd : 5, 617 __BITFIELD_FIELD(unsigned int func : 6, 618 ;)))))) 619 }; 620 621 struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ 622 __BITFIELD_FIELD(unsigned int opcode : 6, 623 __BITFIELD_FIELD(unsigned int ft : 5, 624 __BITFIELD_FIELD(unsigned int fs : 5, 625 __BITFIELD_FIELD(unsigned int fd : 5, 626 __BITFIELD_FIELD(unsigned int fmt : 3, 627 __BITFIELD_FIELD(unsigned int op : 2, 628 __BITFIELD_FIELD(unsigned int func : 6, 629 ;))))))) 630 }; 631 632 struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ 633 __BITFIELD_FIELD(unsigned int opcode : 6, 634 __BITFIELD_FIELD(unsigned int op : 5, 635 __BITFIELD_FIELD(unsigned int rt : 5, 636 __BITFIELD_FIELD(unsigned int fs : 5, 637 __BITFIELD_FIELD(unsigned int fd : 5, 638 __BITFIELD_FIELD(unsigned int func : 6, 639 ;)))))) 640 }; 641 642 struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ 643 __BITFIELD_FIELD(unsigned int opcode : 6, 644 __BITFIELD_FIELD(unsigned int rt : 5, 645 __BITFIELD_FIELD(unsigned int fs : 5, 646 __BITFIELD_FIELD(unsigned int fmt : 2, 647 __BITFIELD_FIELD(unsigned int op : 8, 648 __BITFIELD_FIELD(unsigned int func : 6, 649 ;)))))) 650 }; 651 652 struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ 653 __BITFIELD_FIELD(unsigned int opcode : 6, 654 __BITFIELD_FIELD(unsigned int fd : 5, 655 __BITFIELD_FIELD(unsigned int fs : 5, 656 __BITFIELD_FIELD(unsigned int cc : 3, 657 __BITFIELD_FIELD(unsigned int zero : 2, 658 __BITFIELD_FIELD(unsigned int fmt : 2, 659 __BITFIELD_FIELD(unsigned int op : 3, 660 __BITFIELD_FIELD(unsigned int func : 6, 661 ;)))))))) 662 }; 663 664 struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ 665 __BITFIELD_FIELD(unsigned int opcode : 6, 666 __BITFIELD_FIELD(unsigned int rt : 5, 667 __BITFIELD_FIELD(unsigned int fs : 5, 668 __BITFIELD_FIELD(unsigned int fmt : 3, 669 __BITFIELD_FIELD(unsigned int op : 7, 670 __BITFIELD_FIELD(unsigned int func : 6, 671 ;)))))) 672 }; 673 674 struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ 675 __BITFIELD_FIELD(unsigned int opcode : 6, 676 __BITFIELD_FIELD(unsigned int rt : 5, 677 __BITFIELD_FIELD(unsigned int fs : 5, 678 __BITFIELD_FIELD(unsigned int cc : 3, 679 __BITFIELD_FIELD(unsigned int fmt : 3, 680 __BITFIELD_FIELD(unsigned int cond : 4, 681 __BITFIELD_FIELD(unsigned int func : 6, 682 ;))))))) 683 }; 684 685 struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ 686 __BITFIELD_FIELD(unsigned int opcode : 6, 687 __BITFIELD_FIELD(unsigned int index : 5, 688 __BITFIELD_FIELD(unsigned int base : 5, 689 __BITFIELD_FIELD(unsigned int fd : 5, 690 __BITFIELD_FIELD(unsigned int op : 5, 691 __BITFIELD_FIELD(unsigned int func : 6, 692 ;)))))) 693 }; 694 695 struct fp6_format { /* FPU madd and msub format (MIPS IV) */ 696 __BITFIELD_FIELD(unsigned int opcode : 6, 697 __BITFIELD_FIELD(unsigned int fr : 5, 698 __BITFIELD_FIELD(unsigned int ft : 5, 699 __BITFIELD_FIELD(unsigned int fs : 5, 700 __BITFIELD_FIELD(unsigned int fd : 5, 701 __BITFIELD_FIELD(unsigned int func : 6, 702 ;)))))) 703 }; 704 705 struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ 706 __BITFIELD_FIELD(unsigned int opcode : 6, 707 __BITFIELD_FIELD(unsigned int ft : 5, 708 __BITFIELD_FIELD(unsigned int fs : 5, 709 __BITFIELD_FIELD(unsigned int fd : 5, 710 __BITFIELD_FIELD(unsigned int fr : 5, 711 __BITFIELD_FIELD(unsigned int func : 6, 712 ;)))))) 713 }; 714 715 struct mm_i_format { /* Immediate format (microMIPS) */ 716 __BITFIELD_FIELD(unsigned int opcode : 6, 717 __BITFIELD_FIELD(unsigned int rt : 5, 718 __BITFIELD_FIELD(unsigned int rs : 5, 719 __BITFIELD_FIELD(signed int simmediate : 16, 720 ;)))) 721 }; 722 723 struct mm_m_format { /* Multi-word load/store format (microMIPS) */ 724 __BITFIELD_FIELD(unsigned int opcode : 6, 725 __BITFIELD_FIELD(unsigned int rd : 5, 726 __BITFIELD_FIELD(unsigned int base : 5, 727 __BITFIELD_FIELD(unsigned int func : 4, 728 __BITFIELD_FIELD(signed int simmediate : 12, 729 ;))))) 730 }; 731 732 struct mm_x_format { /* Scaled indexed load format (microMIPS) */ 733 __BITFIELD_FIELD(unsigned int opcode : 6, 734 __BITFIELD_FIELD(unsigned int index : 5, 735 __BITFIELD_FIELD(unsigned int base : 5, 736 __BITFIELD_FIELD(unsigned int rd : 5, 737 __BITFIELD_FIELD(unsigned int func : 11, 738 ;))))) 739 }; 740 741 /* 742 * microMIPS instruction formats (16-bit length) 743 */ 744 struct mm_b0_format { /* Unconditional branch format (microMIPS) */ 745 __BITFIELD_FIELD(unsigned int opcode : 6, 746 __BITFIELD_FIELD(signed int simmediate : 10, 747 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 748 ;))) 749 }; 750 751 struct mm_b1_format { /* Conditional branch format (microMIPS) */ 752 __BITFIELD_FIELD(unsigned int opcode : 6, 753 __BITFIELD_FIELD(unsigned int rs : 3, 754 __BITFIELD_FIELD(signed int simmediate : 7, 755 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 756 ;)))) 757 }; 758 759 struct mm16_m_format { /* Multi-word load/store format */ 760 __BITFIELD_FIELD(unsigned int opcode : 6, 761 __BITFIELD_FIELD(unsigned int func : 4, 762 __BITFIELD_FIELD(unsigned int rlist : 2, 763 __BITFIELD_FIELD(unsigned int imm : 4, 764 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 765 ;))))) 766 }; 767 768 struct mm16_rb_format { /* Signed immediate format */ 769 __BITFIELD_FIELD(unsigned int opcode : 6, 770 __BITFIELD_FIELD(unsigned int rt : 3, 771 __BITFIELD_FIELD(unsigned int base : 3, 772 __BITFIELD_FIELD(signed int simmediate : 4, 773 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 774 ;))))) 775 }; 776 777 struct mm16_r3_format { /* Load from global pointer format */ 778 __BITFIELD_FIELD(unsigned int opcode : 6, 779 __BITFIELD_FIELD(unsigned int rt : 3, 780 __BITFIELD_FIELD(signed int simmediate : 7, 781 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 782 ;)))) 783 }; 784 785 struct mm16_r5_format { /* Load/store from stack pointer format */ 786 __BITFIELD_FIELD(unsigned int opcode : 6, 787 __BITFIELD_FIELD(unsigned int rt : 5, 788 __BITFIELD_FIELD(signed int simmediate : 5, 789 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 790 ;)))) 791 }; 792 793 /* 794 * MIPS16e instruction formats (16-bit length) 795 */ 796 struct m16e_rr { 797 __BITFIELD_FIELD(unsigned int opcode : 5, 798 __BITFIELD_FIELD(unsigned int rx : 3, 799 __BITFIELD_FIELD(unsigned int nd : 1, 800 __BITFIELD_FIELD(unsigned int l : 1, 801 __BITFIELD_FIELD(unsigned int ra : 1, 802 __BITFIELD_FIELD(unsigned int func : 5, 803 ;)))))) 804 }; 805 806 struct m16e_jal { 807 __BITFIELD_FIELD(unsigned int opcode : 5, 808 __BITFIELD_FIELD(unsigned int x : 1, 809 __BITFIELD_FIELD(unsigned int imm20_16 : 5, 810 __BITFIELD_FIELD(signed int imm25_21 : 5, 811 ;)))) 812 }; 813 814 struct m16e_i64 { 815 __BITFIELD_FIELD(unsigned int opcode : 5, 816 __BITFIELD_FIELD(unsigned int func : 3, 817 __BITFIELD_FIELD(unsigned int imm : 8, 818 ;))) 819 }; 820 821 struct m16e_ri64 { 822 __BITFIELD_FIELD(unsigned int opcode : 5, 823 __BITFIELD_FIELD(unsigned int func : 3, 824 __BITFIELD_FIELD(unsigned int ry : 3, 825 __BITFIELD_FIELD(unsigned int imm : 5, 826 ;)))) 827 }; 828 829 struct m16e_ri { 830 __BITFIELD_FIELD(unsigned int opcode : 5, 831 __BITFIELD_FIELD(unsigned int rx : 3, 832 __BITFIELD_FIELD(unsigned int imm : 8, 833 ;))) 834 }; 835 836 struct m16e_rri { 837 __BITFIELD_FIELD(unsigned int opcode : 5, 838 __BITFIELD_FIELD(unsigned int rx : 3, 839 __BITFIELD_FIELD(unsigned int ry : 3, 840 __BITFIELD_FIELD(unsigned int imm : 5, 841 ;)))) 842 }; 843 844 struct m16e_i8 { 845 __BITFIELD_FIELD(unsigned int opcode : 5, 846 __BITFIELD_FIELD(unsigned int func : 3, 847 __BITFIELD_FIELD(unsigned int imm : 8, 848 ;))) 849 }; 850 851 union mips_instruction { 852 unsigned int word; 853 unsigned short halfword[2]; 854 unsigned char byte[4]; 855 struct j_format j_format; 856 struct i_format i_format; 857 struct u_format u_format; 858 struct c_format c_format; 859 struct r_format r_format; 860 struct p_format p_format; 861 struct f_format f_format; 862 struct ma_format ma_format; 863 struct b_format b_format; 864 struct ps_format ps_format; 865 struct v_format v_format; 866 struct spec3_format spec3_format; 867 struct fb_format fb_format; 868 struct fp0_format fp0_format; 869 struct mm_fp0_format mm_fp0_format; 870 struct fp1_format fp1_format; 871 struct mm_fp1_format mm_fp1_format; 872 struct mm_fp2_format mm_fp2_format; 873 struct mm_fp3_format mm_fp3_format; 874 struct mm_fp4_format mm_fp4_format; 875 struct mm_fp5_format mm_fp5_format; 876 struct fp6_format fp6_format; 877 struct mm_fp6_format mm_fp6_format; 878 struct mm_i_format mm_i_format; 879 struct mm_m_format mm_m_format; 880 struct mm_x_format mm_x_format; 881 struct mm_b0_format mm_b0_format; 882 struct mm_b1_format mm_b1_format; 883 struct mm16_m_format mm16_m_format ; 884 struct mm16_rb_format mm16_rb_format; 885 struct mm16_r3_format mm16_r3_format; 886 struct mm16_r5_format mm16_r5_format; 887 }; 888 889 union mips16e_instruction { 890 unsigned int full : 16; 891 struct m16e_rr rr; 892 struct m16e_jal jal; 893 struct m16e_i64 i64; 894 struct m16e_ri64 ri64; 895 struct m16e_ri ri; 896 struct m16e_rri rri; 897 struct m16e_i8 i8; 898 }; 899 900 #endif /* _UAPI_ASM_INST_H */ 901