1*1a59d1b8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2384740dcSRalf Baechle /* ********************************************************************* 3384740dcSRalf Baechle * SB1250 Board Support Package 4384740dcSRalf Baechle * 5384740dcSRalf Baechle * MAC constants and macros File: sb1250_mac.h 6384740dcSRalf Baechle * 7384740dcSRalf Baechle * This module contains constants and macros for the SB1250's 8384740dcSRalf Baechle * ethernet controllers. 9384740dcSRalf Baechle * 10384740dcSRalf Baechle * SB1250 specification level: User's manual 1/02/02 11384740dcSRalf Baechle * 12384740dcSRalf Baechle ********************************************************************* 13384740dcSRalf Baechle * 14384740dcSRalf Baechle * Copyright 2000,2001,2002,2003 15384740dcSRalf Baechle * Broadcom Corporation. All rights reserved. 16384740dcSRalf Baechle * 17384740dcSRalf Baechle ********************************************************************* */ 18384740dcSRalf Baechle 19384740dcSRalf Baechle 20384740dcSRalf Baechle #ifndef _SB1250_MAC_H 21384740dcSRalf Baechle #define _SB1250_MAC_H 22384740dcSRalf Baechle 23a1ce3928SDavid Howells #include <asm/sibyte/sb1250_defs.h> 24384740dcSRalf Baechle 25384740dcSRalf Baechle /* ********************************************************************* 26384740dcSRalf Baechle * Ethernet MAC Registers 27384740dcSRalf Baechle ********************************************************************* */ 28384740dcSRalf Baechle 29384740dcSRalf Baechle /* 30384740dcSRalf Baechle * MAC Configuration Register (Table 9-13) 31384740dcSRalf Baechle * Register: MAC_CFG_0 32384740dcSRalf Baechle * Register: MAC_CFG_1 33384740dcSRalf Baechle * Register: MAC_CFG_2 34384740dcSRalf Baechle */ 35384740dcSRalf Baechle 36384740dcSRalf Baechle 37384740dcSRalf Baechle #define M_MAC_RESERVED0 _SB_MAKEMASK1(0) 38384740dcSRalf Baechle #define M_MAC_TX_HOLD_SOP_EN _SB_MAKEMASK1(1) 39384740dcSRalf Baechle #define M_MAC_RETRY_EN _SB_MAKEMASK1(2) 40384740dcSRalf Baechle #define M_MAC_RET_DRPREQ_EN _SB_MAKEMASK1(3) 41384740dcSRalf Baechle #define M_MAC_RET_UFL_EN _SB_MAKEMASK1(4) 42384740dcSRalf Baechle #define M_MAC_BURST_EN _SB_MAKEMASK1(5) 43384740dcSRalf Baechle 44384740dcSRalf Baechle #define S_MAC_TX_PAUSE _SB_MAKE64(6) 45384740dcSRalf Baechle #define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3, S_MAC_TX_PAUSE) 46384740dcSRalf Baechle #define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x, S_MAC_TX_PAUSE) 47384740dcSRalf Baechle 48384740dcSRalf Baechle #define K_MAC_TX_PAUSE_CNT_512 0 49384740dcSRalf Baechle #define K_MAC_TX_PAUSE_CNT_1K 1 50384740dcSRalf Baechle #define K_MAC_TX_PAUSE_CNT_2K 2 51384740dcSRalf Baechle #define K_MAC_TX_PAUSE_CNT_4K 3 52384740dcSRalf Baechle #define K_MAC_TX_PAUSE_CNT_8K 4 53384740dcSRalf Baechle #define K_MAC_TX_PAUSE_CNT_16K 5 54384740dcSRalf Baechle #define K_MAC_TX_PAUSE_CNT_32K 6 55384740dcSRalf Baechle #define K_MAC_TX_PAUSE_CNT_64K 7 56384740dcSRalf Baechle 57384740dcSRalf Baechle #define V_MAC_TX_PAUSE_CNT_512 V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512) 58384740dcSRalf Baechle #define V_MAC_TX_PAUSE_CNT_1K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K) 59384740dcSRalf Baechle #define V_MAC_TX_PAUSE_CNT_2K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K) 60384740dcSRalf Baechle #define V_MAC_TX_PAUSE_CNT_4K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K) 61384740dcSRalf Baechle #define V_MAC_TX_PAUSE_CNT_8K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K) 62384740dcSRalf Baechle #define V_MAC_TX_PAUSE_CNT_16K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K) 63384740dcSRalf Baechle #define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) 64384740dcSRalf Baechle #define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) 65384740dcSRalf Baechle 66384740dcSRalf Baechle #define M_MAC_RESERVED1 _SB_MAKEMASK(8, 9) 67384740dcSRalf Baechle 68384740dcSRalf Baechle #define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) 69384740dcSRalf Baechle 70384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_CHIP(1480) 71384740dcSRalf Baechle #define M_MAC_TIMESTAMP _SB_MAKEMASK1(18) 72384740dcSRalf Baechle #endif 73384740dcSRalf Baechle #define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19) 74384740dcSRalf Baechle #define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20) 75384740dcSRalf Baechle #define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21) 76384740dcSRalf Baechle #define M_MAC_DRP_DRBLERRPKT_EN _SB_MAKEMASK1(22) 77384740dcSRalf Baechle #define M_MAC_DRP_RNTPKT_EN _SB_MAKEMASK1(23) 78384740dcSRalf Baechle #define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) 79384740dcSRalf Baechle #define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) 80384740dcSRalf Baechle 81384740dcSRalf Baechle #define M_MAC_RESERVED3 _SB_MAKEMASK(6, 26) 82384740dcSRalf Baechle 83384740dcSRalf Baechle #define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) 84384740dcSRalf Baechle #define M_MAC_HDX_EN _SB_MAKEMASK1(33) 85384740dcSRalf Baechle 86384740dcSRalf Baechle #define S_MAC_SPEED_SEL _SB_MAKE64(34) 87384740dcSRalf Baechle #define M_MAC_SPEED_SEL _SB_MAKEMASK(2, S_MAC_SPEED_SEL) 88384740dcSRalf Baechle #define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x, S_MAC_SPEED_SEL) 89384740dcSRalf Baechle #define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x, S_MAC_SPEED_SEL, M_MAC_SPEED_SEL) 90384740dcSRalf Baechle 91384740dcSRalf Baechle #define K_MAC_SPEED_SEL_10MBPS 0 92384740dcSRalf Baechle #define K_MAC_SPEED_SEL_100MBPS 1 93384740dcSRalf Baechle #define K_MAC_SPEED_SEL_1000MBPS 2 94384740dcSRalf Baechle #define K_MAC_SPEED_SEL_RESERVED 3 95384740dcSRalf Baechle 96384740dcSRalf Baechle #define V_MAC_SPEED_SEL_10MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS) 97384740dcSRalf Baechle #define V_MAC_SPEED_SEL_100MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS) 98384740dcSRalf Baechle #define V_MAC_SPEED_SEL_1000MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS) 99384740dcSRalf Baechle #define V_MAC_SPEED_SEL_RESERVED V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED) 100384740dcSRalf Baechle 101384740dcSRalf Baechle #define M_MAC_TX_CLK_EDGE_SEL _SB_MAKEMASK1(36) 102384740dcSRalf Baechle #define M_MAC_LOOPBACK_SEL _SB_MAKEMASK1(37) 103384740dcSRalf Baechle #define M_MAC_FAST_SYNC _SB_MAKEMASK1(38) 104384740dcSRalf Baechle #define M_MAC_SS_EN _SB_MAKEMASK1(39) 105384740dcSRalf Baechle 106384740dcSRalf Baechle #define S_MAC_BYPASS_CFG _SB_MAKE64(40) 107384740dcSRalf Baechle #define M_MAC_BYPASS_CFG _SB_MAKEMASK(2, S_MAC_BYPASS_CFG) 108384740dcSRalf Baechle #define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_CFG) 109384740dcSRalf Baechle #define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_CFG, M_MAC_BYPASS_CFG) 110384740dcSRalf Baechle 111384740dcSRalf Baechle #define K_MAC_BYPASS_GMII 0 112384740dcSRalf Baechle #define K_MAC_BYPASS_ENCODED 1 113384740dcSRalf Baechle #define K_MAC_BYPASS_SOP 2 114384740dcSRalf Baechle #define K_MAC_BYPASS_EOP 3 115384740dcSRalf Baechle 116384740dcSRalf Baechle #define M_MAC_BYPASS_16 _SB_MAKEMASK1(42) 117384740dcSRalf Baechle #define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43) 118384740dcSRalf Baechle 119384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 120384740dcSRalf Baechle #define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44) 121384740dcSRalf Baechle #endif /* 1250 PASS2 || 112x PASS1 || 1480*/ 122384740dcSRalf Baechle 123384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 124384740dcSRalf Baechle #define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45) 125384740dcSRalf Baechle #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 126384740dcSRalf Baechle 127384740dcSRalf Baechle #define S_MAC_BYPASS_IFG _SB_MAKE64(46) 128384740dcSRalf Baechle #define M_MAC_BYPASS_IFG _SB_MAKEMASK(8, S_MAC_BYPASS_IFG) 129384740dcSRalf Baechle #define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_IFG) 130384740dcSRalf Baechle #define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_IFG, M_MAC_BYPASS_IFG) 131384740dcSRalf Baechle 132384740dcSRalf Baechle #define K_MAC_FC_CMD_DISABLED 0 133384740dcSRalf Baechle #define K_MAC_FC_CMD_ENABLED 1 134384740dcSRalf Baechle #define K_MAC_FC_CMD_ENAB_FALSECARR 2 135384740dcSRalf Baechle 136384740dcSRalf Baechle #define V_MAC_FC_CMD_DISABLED V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED) 137384740dcSRalf Baechle #define V_MAC_FC_CMD_ENABLED V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED) 138384740dcSRalf Baechle #define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR) 139384740dcSRalf Baechle 140384740dcSRalf Baechle #define M_MAC_FC_SEL _SB_MAKEMASK1(54) 141384740dcSRalf Baechle 142384740dcSRalf Baechle #define S_MAC_FC_CMD _SB_MAKE64(55) 143384740dcSRalf Baechle #define M_MAC_FC_CMD _SB_MAKEMASK(2, S_MAC_FC_CMD) 144384740dcSRalf Baechle #define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x, S_MAC_FC_CMD) 145384740dcSRalf Baechle #define G_MAC_FC_CMD(x) _SB_GETVALUE(x, S_MAC_FC_CMD, M_MAC_FC_CMD) 146384740dcSRalf Baechle 147384740dcSRalf Baechle #define S_MAC_RX_CH_SEL _SB_MAKE64(57) 148384740dcSRalf Baechle #define M_MAC_RX_CH_SEL _SB_MAKEMASK(7, S_MAC_RX_CH_SEL) 149384740dcSRalf Baechle #define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_SEL) 150384740dcSRalf Baechle #define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_SEL, M_MAC_RX_CH_SEL) 151384740dcSRalf Baechle 152384740dcSRalf Baechle 153384740dcSRalf Baechle /* 154384740dcSRalf Baechle * MAC Enable Registers 155384740dcSRalf Baechle * Register: MAC_ENABLE_0 156384740dcSRalf Baechle * Register: MAC_ENABLE_1 157384740dcSRalf Baechle * Register: MAC_ENABLE_2 158384740dcSRalf Baechle */ 159384740dcSRalf Baechle 160384740dcSRalf Baechle #define M_MAC_RXDMA_EN0 _SB_MAKEMASK1(0) 161384740dcSRalf Baechle #define M_MAC_RXDMA_EN1 _SB_MAKEMASK1(1) 162384740dcSRalf Baechle #define M_MAC_TXDMA_EN0 _SB_MAKEMASK1(4) 163384740dcSRalf Baechle #define M_MAC_TXDMA_EN1 _SB_MAKEMASK1(5) 164384740dcSRalf Baechle 165384740dcSRalf Baechle #define M_MAC_PORT_RESET _SB_MAKEMASK1(8) 166384740dcSRalf Baechle 167384740dcSRalf Baechle #if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x)) 168384740dcSRalf Baechle #define M_MAC_RX_ENABLE _SB_MAKEMASK1(10) 169384740dcSRalf Baechle #define M_MAC_TX_ENABLE _SB_MAKEMASK1(11) 170384740dcSRalf Baechle #define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12) 171384740dcSRalf Baechle #define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13) 172384740dcSRalf Baechle #endif 173384740dcSRalf Baechle 174384740dcSRalf Baechle /* 175384740dcSRalf Baechle * MAC reset information register (1280/1255) 176384740dcSRalf Baechle */ 177384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_CHIP(1480) 178384740dcSRalf Baechle #define M_MAC_RX_CH0_PAUSE_ON _SB_MAKEMASK1(8) 179384740dcSRalf Baechle #define M_MAC_RX_CH1_PAUSE_ON _SB_MAKEMASK1(16) 180384740dcSRalf Baechle #define M_MAC_TX_CH0_PAUSE_ON _SB_MAKEMASK1(24) 181384740dcSRalf Baechle #define M_MAC_TX_CH1_PAUSE_ON _SB_MAKEMASK1(32) 182384740dcSRalf Baechle #endif 183384740dcSRalf Baechle 184384740dcSRalf Baechle /* 185384740dcSRalf Baechle * MAC DMA Control Register 186384740dcSRalf Baechle * Register: MAC_TXD_CTL_0 187384740dcSRalf Baechle * Register: MAC_TXD_CTL_1 188384740dcSRalf Baechle * Register: MAC_TXD_CTL_2 189384740dcSRalf Baechle */ 190384740dcSRalf Baechle 191384740dcSRalf Baechle #define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) 192384740dcSRalf Baechle #define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT0) 193384740dcSRalf Baechle #define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT0) 194384740dcSRalf Baechle #define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT0, M_MAC_TXD_WEIGHT0) 195384740dcSRalf Baechle 196384740dcSRalf Baechle #define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) 197384740dcSRalf Baechle #define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT1) 198384740dcSRalf Baechle #define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT1) 199384740dcSRalf Baechle #define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1) 200384740dcSRalf Baechle 201384740dcSRalf Baechle /* 202af901ca1SAndré Goddard Rosa * MAC Fifo Threshold registers (Table 9-14) 203384740dcSRalf Baechle * Register: MAC_THRSH_CFG_0 204384740dcSRalf Baechle * Register: MAC_THRSH_CFG_1 205384740dcSRalf Baechle * Register: MAC_THRSH_CFG_2 206384740dcSRalf Baechle */ 207384740dcSRalf Baechle 208384740dcSRalf Baechle #define S_MAC_TX_WR_THRSH _SB_MAKE64(0) 209384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 210384740dcSRalf Baechle /* XXX: Can't enable, as it has the same name as a pass2+ define below. */ 211384740dcSRalf Baechle /* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6, S_MAC_TX_WR_THRSH) */ 212384740dcSRalf Baechle #endif /* up to 1250 PASS1 */ 213384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 214384740dcSRalf Baechle #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7, S_MAC_TX_WR_THRSH) 215384740dcSRalf Baechle #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 216384740dcSRalf Baechle #define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_WR_THRSH) 217384740dcSRalf Baechle #define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_WR_THRSH, M_MAC_TX_WR_THRSH) 218384740dcSRalf Baechle 219384740dcSRalf Baechle #define S_MAC_TX_RD_THRSH _SB_MAKE64(8) 220384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 221384740dcSRalf Baechle /* XXX: Can't enable, as it has the same name as a pass2+ define below. */ 222384740dcSRalf Baechle /* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6, S_MAC_TX_RD_THRSH) */ 223384740dcSRalf Baechle #endif /* up to 1250 PASS1 */ 224384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 225384740dcSRalf Baechle #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7, S_MAC_TX_RD_THRSH) 226384740dcSRalf Baechle #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 227384740dcSRalf Baechle #define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RD_THRSH) 228384740dcSRalf Baechle #define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RD_THRSH, M_MAC_TX_RD_THRSH) 229384740dcSRalf Baechle 230384740dcSRalf Baechle #define S_MAC_TX_RL_THRSH _SB_MAKE64(16) 231384740dcSRalf Baechle #define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4, S_MAC_TX_RL_THRSH) 232384740dcSRalf Baechle #define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RL_THRSH) 233384740dcSRalf Baechle #define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RL_THRSH, M_MAC_TX_RL_THRSH) 234384740dcSRalf Baechle 235384740dcSRalf Baechle #define S_MAC_RX_PL_THRSH _SB_MAKE64(24) 236384740dcSRalf Baechle #define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6, S_MAC_RX_PL_THRSH) 237384740dcSRalf Baechle #define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_PL_THRSH) 238384740dcSRalf Baechle #define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_PL_THRSH, M_MAC_RX_PL_THRSH) 239384740dcSRalf Baechle 240384740dcSRalf Baechle #define S_MAC_RX_RD_THRSH _SB_MAKE64(32) 241384740dcSRalf Baechle #define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6, S_MAC_RX_RD_THRSH) 242384740dcSRalf Baechle #define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RD_THRSH) 243384740dcSRalf Baechle #define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RD_THRSH, M_MAC_RX_RD_THRSH) 244384740dcSRalf Baechle 245384740dcSRalf Baechle #define S_MAC_RX_RL_THRSH _SB_MAKE64(40) 246384740dcSRalf Baechle #define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6, S_MAC_RX_RL_THRSH) 247384740dcSRalf Baechle #define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RL_THRSH) 248384740dcSRalf Baechle #define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RL_THRSH, M_MAC_RX_RL_THRSH) 249384740dcSRalf Baechle 250384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 251384740dcSRalf Baechle #define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) 252384740dcSRalf Baechle #define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6, S_MAC_ENC_FC_THRSH) 253384740dcSRalf Baechle #define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x, S_MAC_ENC_FC_THRSH) 254384740dcSRalf Baechle #define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x, S_MAC_ENC_FC_THRSH, M_MAC_ENC_FC_THRSH) 255384740dcSRalf Baechle #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 256384740dcSRalf Baechle 257384740dcSRalf Baechle /* 258384740dcSRalf Baechle * MAC Frame Configuration Registers (Table 9-15) 259384740dcSRalf Baechle * Register: MAC_FRAME_CFG_0 260384740dcSRalf Baechle * Register: MAC_FRAME_CFG_1 261384740dcSRalf Baechle * Register: MAC_FRAME_CFG_2 262384740dcSRalf Baechle */ 263384740dcSRalf Baechle 264384740dcSRalf Baechle /* XXXCGD: ??? Unused in pass2? */ 265384740dcSRalf Baechle #define S_MAC_IFG_RX _SB_MAKE64(0) 266384740dcSRalf Baechle #define M_MAC_IFG_RX _SB_MAKEMASK(6, S_MAC_IFG_RX) 267384740dcSRalf Baechle #define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x, S_MAC_IFG_RX) 268384740dcSRalf Baechle #define G_MAC_IFG_RX(x) _SB_GETVALUE(x, S_MAC_IFG_RX, M_MAC_IFG_RX) 269384740dcSRalf Baechle 270384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 271384740dcSRalf Baechle #define S_MAC_PRE_LEN _SB_MAKE64(0) 272384740dcSRalf Baechle #define M_MAC_PRE_LEN _SB_MAKEMASK(6, S_MAC_PRE_LEN) 273384740dcSRalf Baechle #define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x, S_MAC_PRE_LEN) 274384740dcSRalf Baechle #define G_MAC_PRE_LEN(x) _SB_GETVALUE(x, S_MAC_PRE_LEN, M_MAC_PRE_LEN) 275384740dcSRalf Baechle #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 276384740dcSRalf Baechle 277384740dcSRalf Baechle #define S_MAC_IFG_TX _SB_MAKE64(6) 278384740dcSRalf Baechle #define M_MAC_IFG_TX _SB_MAKEMASK(6, S_MAC_IFG_TX) 279384740dcSRalf Baechle #define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x, S_MAC_IFG_TX) 280384740dcSRalf Baechle #define G_MAC_IFG_TX(x) _SB_GETVALUE(x, S_MAC_IFG_TX, M_MAC_IFG_TX) 281384740dcSRalf Baechle 282384740dcSRalf Baechle #define S_MAC_IFG_THRSH _SB_MAKE64(12) 283384740dcSRalf Baechle #define M_MAC_IFG_THRSH _SB_MAKEMASK(6, S_MAC_IFG_THRSH) 284384740dcSRalf Baechle #define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x, S_MAC_IFG_THRSH) 285384740dcSRalf Baechle #define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x, S_MAC_IFG_THRSH, M_MAC_IFG_THRSH) 286384740dcSRalf Baechle 287384740dcSRalf Baechle #define S_MAC_BACKOFF_SEL _SB_MAKE64(18) 288384740dcSRalf Baechle #define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4, S_MAC_BACKOFF_SEL) 289384740dcSRalf Baechle #define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x, S_MAC_BACKOFF_SEL) 290384740dcSRalf Baechle #define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x, S_MAC_BACKOFF_SEL, M_MAC_BACKOFF_SEL) 291384740dcSRalf Baechle 292384740dcSRalf Baechle #define S_MAC_LFSR_SEED _SB_MAKE64(22) 293384740dcSRalf Baechle #define M_MAC_LFSR_SEED _SB_MAKEMASK(8, S_MAC_LFSR_SEED) 294384740dcSRalf Baechle #define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x, S_MAC_LFSR_SEED) 295384740dcSRalf Baechle #define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x, S_MAC_LFSR_SEED, M_MAC_LFSR_SEED) 296384740dcSRalf Baechle 297384740dcSRalf Baechle #define S_MAC_SLOT_SIZE _SB_MAKE64(30) 298384740dcSRalf Baechle #define M_MAC_SLOT_SIZE _SB_MAKEMASK(10, S_MAC_SLOT_SIZE) 299384740dcSRalf Baechle #define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x, S_MAC_SLOT_SIZE) 300384740dcSRalf Baechle #define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x, S_MAC_SLOT_SIZE, M_MAC_SLOT_SIZE) 301384740dcSRalf Baechle 302384740dcSRalf Baechle #define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) 303384740dcSRalf Baechle #define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8, S_MAC_MIN_FRAMESZ) 304384740dcSRalf Baechle #define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MIN_FRAMESZ) 305384740dcSRalf Baechle #define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MIN_FRAMESZ, M_MAC_MIN_FRAMESZ) 306384740dcSRalf Baechle 307384740dcSRalf Baechle #define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) 308384740dcSRalf Baechle #define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16, S_MAC_MAX_FRAMESZ) 309384740dcSRalf Baechle #define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MAX_FRAMESZ) 310384740dcSRalf Baechle #define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MAX_FRAMESZ, M_MAC_MAX_FRAMESZ) 311384740dcSRalf Baechle 312384740dcSRalf Baechle /* 313384740dcSRalf Baechle * These constants are used to configure the fields within the Frame 314384740dcSRalf Baechle * Configuration Register. 315384740dcSRalf Baechle */ 316384740dcSRalf Baechle 317384740dcSRalf Baechle #define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */ 318384740dcSRalf Baechle #define K_MAC_IFG_RX_100 _SB_MAKE64(0) 319384740dcSRalf Baechle #define K_MAC_IFG_RX_1000 _SB_MAKE64(0) 320384740dcSRalf Baechle 321384740dcSRalf Baechle #define K_MAC_IFG_TX_10 _SB_MAKE64(20) 322384740dcSRalf Baechle #define K_MAC_IFG_TX_100 _SB_MAKE64(20) 323384740dcSRalf Baechle #define K_MAC_IFG_TX_1000 _SB_MAKE64(8) 324384740dcSRalf Baechle 325384740dcSRalf Baechle #define K_MAC_IFG_THRSH_10 _SB_MAKE64(4) 326384740dcSRalf Baechle #define K_MAC_IFG_THRSH_100 _SB_MAKE64(4) 327384740dcSRalf Baechle #define K_MAC_IFG_THRSH_1000 _SB_MAKE64(0) 328384740dcSRalf Baechle 329384740dcSRalf Baechle #define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0) 330384740dcSRalf Baechle #define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0) 331384740dcSRalf Baechle #define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0) 332384740dcSRalf Baechle 333384740dcSRalf Baechle #define V_MAC_IFG_RX_10 V_MAC_IFG_RX(K_MAC_IFG_RX_10) 334384740dcSRalf Baechle #define V_MAC_IFG_RX_100 V_MAC_IFG_RX(K_MAC_IFG_RX_100) 335384740dcSRalf Baechle #define V_MAC_IFG_RX_1000 V_MAC_IFG_RX(K_MAC_IFG_RX_1000) 336384740dcSRalf Baechle 337384740dcSRalf Baechle #define V_MAC_IFG_TX_10 V_MAC_IFG_TX(K_MAC_IFG_TX_10) 338384740dcSRalf Baechle #define V_MAC_IFG_TX_100 V_MAC_IFG_TX(K_MAC_IFG_TX_100) 339384740dcSRalf Baechle #define V_MAC_IFG_TX_1000 V_MAC_IFG_TX(K_MAC_IFG_TX_1000) 340384740dcSRalf Baechle 341384740dcSRalf Baechle #define V_MAC_IFG_THRSH_10 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10) 342384740dcSRalf Baechle #define V_MAC_IFG_THRSH_100 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100) 343384740dcSRalf Baechle #define V_MAC_IFG_THRSH_1000 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000) 344384740dcSRalf Baechle 345384740dcSRalf Baechle #define V_MAC_SLOT_SIZE_10 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10) 346384740dcSRalf Baechle #define V_MAC_SLOT_SIZE_100 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100) 347384740dcSRalf Baechle #define V_MAC_SLOT_SIZE_1000 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000) 348384740dcSRalf Baechle 349384740dcSRalf Baechle #define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9) 350384740dcSRalf Baechle #define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64) 351384740dcSRalf Baechle #define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518) 352384740dcSRalf Baechle #define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216) 353384740dcSRalf Baechle 354384740dcSRalf Baechle #define V_MAC_MIN_FRAMESZ_FIFO V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO) 355384740dcSRalf Baechle #define V_MAC_MIN_FRAMESZ_DEFAULT V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT) 356384740dcSRalf Baechle #define V_MAC_MAX_FRAMESZ_DEFAULT V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT) 357384740dcSRalf Baechle #define V_MAC_MAX_FRAMESZ_JUMBO V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO) 358384740dcSRalf Baechle 359384740dcSRalf Baechle /* 360384740dcSRalf Baechle * MAC VLAN Tag Registers (Table 9-16) 361384740dcSRalf Baechle * Register: MAC_VLANTAG_0 362384740dcSRalf Baechle * Register: MAC_VLANTAG_1 363384740dcSRalf Baechle * Register: MAC_VLANTAG_2 364384740dcSRalf Baechle */ 365384740dcSRalf Baechle 366384740dcSRalf Baechle #define S_MAC_VLAN_TAG _SB_MAKE64(0) 367384740dcSRalf Baechle #define M_MAC_VLAN_TAG _SB_MAKEMASK(32, S_MAC_VLAN_TAG) 368384740dcSRalf Baechle #define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x, S_MAC_VLAN_TAG) 369384740dcSRalf Baechle #define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x, S_MAC_VLAN_TAG, M_MAC_VLAN_TAG) 370384740dcSRalf Baechle 371384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 372384740dcSRalf Baechle #define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) 373384740dcSRalf Baechle #define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_TX_PKT_OFFSET) 374384740dcSRalf Baechle #define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_PKT_OFFSET) 375384740dcSRalf Baechle #define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_PKT_OFFSET, M_MAC_TX_PKT_OFFSET) 376384740dcSRalf Baechle 377384740dcSRalf Baechle #define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) 378384740dcSRalf Baechle #define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_TX_CRC_OFFSET) 379384740dcSRalf Baechle #define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_CRC_OFFSET) 380384740dcSRalf Baechle #define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_CRC_OFFSET, M_MAC_TX_CRC_OFFSET) 381384740dcSRalf Baechle 382384740dcSRalf Baechle #define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48) 383384740dcSRalf Baechle #endif /* 1250 PASS3 || 112x PASS1 */ 384384740dcSRalf Baechle 385384740dcSRalf Baechle /* 386384740dcSRalf Baechle * MAC Status Registers (Table 9-17) 387384740dcSRalf Baechle * Also used for the MAC Interrupt Mask Register (Table 9-18) 388384740dcSRalf Baechle * Register: MAC_STATUS_0 389384740dcSRalf Baechle * Register: MAC_STATUS_1 390384740dcSRalf Baechle * Register: MAC_STATUS_2 391384740dcSRalf Baechle * Register: MAC_INT_MASK_0 392384740dcSRalf Baechle * Register: MAC_INT_MASK_1 393384740dcSRalf Baechle * Register: MAC_INT_MASK_2 394384740dcSRalf Baechle */ 395384740dcSRalf Baechle 396384740dcSRalf Baechle /* 397384740dcSRalf Baechle * Use these constants to shift the appropriate channel 398384740dcSRalf Baechle * into the CH0 position so the same tests can be used 399384740dcSRalf Baechle * on each channel. 400384740dcSRalf Baechle */ 401384740dcSRalf Baechle 402384740dcSRalf Baechle #define S_MAC_RX_CH0 _SB_MAKE64(0) 403384740dcSRalf Baechle #define S_MAC_RX_CH1 _SB_MAKE64(8) 404384740dcSRalf Baechle #define S_MAC_TX_CH0 _SB_MAKE64(16) 405384740dcSRalf Baechle #define S_MAC_TX_CH1 _SB_MAKE64(24) 406384740dcSRalf Baechle 407384740dcSRalf Baechle #define S_MAC_TXCHANNELS _SB_MAKE64(16) /* this is 1st TX chan */ 408384740dcSRalf Baechle #define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */ 409384740dcSRalf Baechle 410384740dcSRalf Baechle /* 411384740dcSRalf Baechle * These are the same as RX channel 0. The idea here 412384740dcSRalf Baechle * is that you'll use one of the "S_" things above 413384740dcSRalf Baechle * and pass just the six bits to a DMA-channel-specific ISR 414384740dcSRalf Baechle */ 415384740dcSRalf Baechle #define M_MAC_INT_CHANNEL _SB_MAKEMASK(8, 0) 416384740dcSRalf Baechle #define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) 417384740dcSRalf Baechle #define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) 418384740dcSRalf Baechle #define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) 419384740dcSRalf Baechle #define M_MAC_INT_HWM _SB_MAKEMASK1(3) 420384740dcSRalf Baechle #define M_MAC_INT_LWM _SB_MAKEMASK1(4) 421384740dcSRalf Baechle #define M_MAC_INT_DSCR _SB_MAKEMASK1(5) 422384740dcSRalf Baechle #define M_MAC_INT_ERR _SB_MAKEMASK1(6) 423384740dcSRalf Baechle #define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */ 424384740dcSRalf Baechle #define M_MAC_INT_DROP _SB_MAKEMASK1(7) /* only for RX channels */ 425384740dcSRalf Baechle 426384740dcSRalf Baechle /* 427384740dcSRalf Baechle * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see 428384740dcSRalf Baechle * also DMA_TX/DMA_RX in sb_regs.h). 429384740dcSRalf Baechle */ 430384740dcSRalf Baechle #define S_MAC_STATUS_CH_OFFSET(ch, txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) 431384740dcSRalf Baechle 432384740dcSRalf Baechle #define M_MAC_STATUS_CHANNEL(ch, txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8, 0), S_MAC_STATUS_CH_OFFSET(ch, txrx)) 433384740dcSRalf Baechle #define M_MAC_STATUS_EOP_COUNT(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 434384740dcSRalf Baechle #define M_MAC_STATUS_EOP_TIMER(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 435384740dcSRalf Baechle #define M_MAC_STATUS_EOP_SEEN(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 436384740dcSRalf Baechle #define M_MAC_STATUS_HWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_HWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 437384740dcSRalf Baechle #define M_MAC_STATUS_LWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_LWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 438384740dcSRalf Baechle #define M_MAC_STATUS_DSCR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 439384740dcSRalf Baechle #define M_MAC_STATUS_ERR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_ERR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 440384740dcSRalf Baechle #define M_MAC_STATUS_DZERO(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 441384740dcSRalf Baechle #define M_MAC_STATUS_DROP(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DROP, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 442384740dcSRalf Baechle #define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7, 0), 40) 443384740dcSRalf Baechle 444384740dcSRalf Baechle 445384740dcSRalf Baechle #define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) 446384740dcSRalf Baechle #define M_MAC_RX_OVRFL _SB_MAKEMASK1(41) 447384740dcSRalf Baechle #define M_MAC_TX_UNDRFL _SB_MAKEMASK1(42) 448384740dcSRalf Baechle #define M_MAC_TX_OVRFL _SB_MAKEMASK1(43) 449384740dcSRalf Baechle #define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44) 450384740dcSRalf Baechle #define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45) 451384740dcSRalf Baechle #define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46) 452384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 453384740dcSRalf Baechle #define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */ 454384740dcSRalf Baechle #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 455384740dcSRalf Baechle 456384740dcSRalf Baechle #define S_MAC_COUNTER_ADDR _SB_MAKE64(47) 457384740dcSRalf Baechle #define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5, S_MAC_COUNTER_ADDR) 458384740dcSRalf Baechle #define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x, S_MAC_COUNTER_ADDR) 459384740dcSRalf Baechle #define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x, S_MAC_COUNTER_ADDR, M_MAC_COUNTER_ADDR) 460384740dcSRalf Baechle 461384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 462384740dcSRalf Baechle #define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) 463384740dcSRalf Baechle #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 464384740dcSRalf Baechle 465384740dcSRalf Baechle /* 466384740dcSRalf Baechle * MAC Fifo Pointer Registers (Table 9-19) [Debug register] 467384740dcSRalf Baechle * Register: MAC_FIFO_PTRS_0 468384740dcSRalf Baechle * Register: MAC_FIFO_PTRS_1 469384740dcSRalf Baechle * Register: MAC_FIFO_PTRS_2 470384740dcSRalf Baechle */ 471384740dcSRalf Baechle 472384740dcSRalf Baechle #define S_MAC_TX_WRPTR _SB_MAKE64(0) 473384740dcSRalf Baechle #define M_MAC_TX_WRPTR _SB_MAKEMASK(6, S_MAC_TX_WRPTR) 474384740dcSRalf Baechle #define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_WRPTR) 475384740dcSRalf Baechle #define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x, S_MAC_TX_WRPTR, M_MAC_TX_WRPTR) 476384740dcSRalf Baechle 477384740dcSRalf Baechle #define S_MAC_TX_RDPTR _SB_MAKE64(8) 478384740dcSRalf Baechle #define M_MAC_TX_RDPTR _SB_MAKEMASK(6, S_MAC_TX_RDPTR) 479384740dcSRalf Baechle #define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_RDPTR) 480384740dcSRalf Baechle #define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x, S_MAC_TX_RDPTR, M_MAC_TX_RDPTR) 481384740dcSRalf Baechle 482384740dcSRalf Baechle #define S_MAC_RX_WRPTR _SB_MAKE64(16) 483384740dcSRalf Baechle #define M_MAC_RX_WRPTR _SB_MAKEMASK(6, S_MAC_RX_WRPTR) 484384740dcSRalf Baechle #define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_WRPTR) 485384740dcSRalf Baechle #define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x, S_MAC_RX_WRPTR, M_MAC_TX_WRPTR) 486384740dcSRalf Baechle 487384740dcSRalf Baechle #define S_MAC_RX_RDPTR _SB_MAKE64(24) 488384740dcSRalf Baechle #define M_MAC_RX_RDPTR _SB_MAKEMASK(6, S_MAC_RX_RDPTR) 489384740dcSRalf Baechle #define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_RDPTR) 490384740dcSRalf Baechle #define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x, S_MAC_RX_RDPTR, M_MAC_TX_RDPTR) 491384740dcSRalf Baechle 492384740dcSRalf Baechle /* 493384740dcSRalf Baechle * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] 494384740dcSRalf Baechle * Register: MAC_EOPCNT_0 495384740dcSRalf Baechle * Register: MAC_EOPCNT_1 496384740dcSRalf Baechle * Register: MAC_EOPCNT_2 497384740dcSRalf Baechle */ 498384740dcSRalf Baechle 499384740dcSRalf Baechle #define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) 500384740dcSRalf Baechle #define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_TX_EOP_COUNTER) 501384740dcSRalf Baechle #define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_TX_EOP_COUNTER) 502384740dcSRalf Baechle #define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_TX_EOP_COUNTER, M_MAC_TX_EOP_COUNTER) 503384740dcSRalf Baechle 504384740dcSRalf Baechle #define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) 505384740dcSRalf Baechle #define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_RX_EOP_COUNTER) 506384740dcSRalf Baechle #define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_RX_EOP_COUNTER) 507384740dcSRalf Baechle #define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER) 508384740dcSRalf Baechle 509384740dcSRalf Baechle /* 51025985edcSLucas De Marchi * MAC Receive Address Filter Exact Match Registers (Table 9-21) 511384740dcSRalf Baechle * Registers: MAC_ADDR0_0 through MAC_ADDR7_0 512384740dcSRalf Baechle * Registers: MAC_ADDR0_1 through MAC_ADDR7_1 513384740dcSRalf Baechle * Registers: MAC_ADDR0_2 through MAC_ADDR7_2 514384740dcSRalf Baechle */ 515384740dcSRalf Baechle 516384740dcSRalf Baechle /* No bitfields */ 517384740dcSRalf Baechle 518384740dcSRalf Baechle /* 519384740dcSRalf Baechle * MAC Receive Address Filter Mask Registers 520384740dcSRalf Baechle * Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1 521384740dcSRalf Baechle * Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1 522384740dcSRalf Baechle * Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1 523384740dcSRalf Baechle */ 524384740dcSRalf Baechle 525384740dcSRalf Baechle /* No bitfields */ 526384740dcSRalf Baechle 527384740dcSRalf Baechle /* 52825985edcSLucas De Marchi * MAC Receive Address Filter Hash Match Registers (Table 9-22) 529384740dcSRalf Baechle * Registers: MAC_HASH0_0 through MAC_HASH7_0 530384740dcSRalf Baechle * Registers: MAC_HASH0_1 through MAC_HASH7_1 531384740dcSRalf Baechle * Registers: MAC_HASH0_2 through MAC_HASH7_2 532384740dcSRalf Baechle */ 533384740dcSRalf Baechle 534384740dcSRalf Baechle /* No bitfields */ 535384740dcSRalf Baechle 536384740dcSRalf Baechle /* 537384740dcSRalf Baechle * MAC Transmit Source Address Registers (Table 9-23) 538384740dcSRalf Baechle * Register: MAC_ETHERNET_ADDR_0 539384740dcSRalf Baechle * Register: MAC_ETHERNET_ADDR_1 540384740dcSRalf Baechle * Register: MAC_ETHERNET_ADDR_2 541384740dcSRalf Baechle */ 542384740dcSRalf Baechle 543384740dcSRalf Baechle /* No bitfields */ 544384740dcSRalf Baechle 545384740dcSRalf Baechle /* 546384740dcSRalf Baechle * MAC Packet Type Configuration Register 547384740dcSRalf Baechle * Register: MAC_TYPE_CFG_0 548384740dcSRalf Baechle * Register: MAC_TYPE_CFG_1 549384740dcSRalf Baechle * Register: MAC_TYPE_CFG_2 550384740dcSRalf Baechle */ 551384740dcSRalf Baechle 552384740dcSRalf Baechle #define S_TYPECFG_TYPESIZE _SB_MAKE64(16) 553384740dcSRalf Baechle 554384740dcSRalf Baechle #define S_TYPECFG_TYPE0 _SB_MAKE64(0) 555384740dcSRalf Baechle #define M_TYPECFG_TYPE0 _SB_MAKEMASK(16, S_TYPECFG_TYPE0) 556384740dcSRalf Baechle #define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE0) 557384740dcSRalf Baechle #define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x, S_TYPECFG_TYPE0, M_TYPECFG_TYPE0) 558384740dcSRalf Baechle 559384740dcSRalf Baechle #define S_TYPECFG_TYPE1 _SB_MAKE64(0) 560384740dcSRalf Baechle #define M_TYPECFG_TYPE1 _SB_MAKEMASK(16, S_TYPECFG_TYPE1) 561384740dcSRalf Baechle #define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE1) 562384740dcSRalf Baechle #define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x, S_TYPECFG_TYPE1, M_TYPECFG_TYPE1) 563384740dcSRalf Baechle 564384740dcSRalf Baechle #define S_TYPECFG_TYPE2 _SB_MAKE64(0) 565384740dcSRalf Baechle #define M_TYPECFG_TYPE2 _SB_MAKEMASK(16, S_TYPECFG_TYPE2) 566384740dcSRalf Baechle #define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE2) 567384740dcSRalf Baechle #define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x, S_TYPECFG_TYPE2, M_TYPECFG_TYPE2) 568384740dcSRalf Baechle 569384740dcSRalf Baechle #define S_TYPECFG_TYPE3 _SB_MAKE64(0) 570384740dcSRalf Baechle #define M_TYPECFG_TYPE3 _SB_MAKEMASK(16, S_TYPECFG_TYPE3) 571384740dcSRalf Baechle #define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE3) 572384740dcSRalf Baechle #define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x, S_TYPECFG_TYPE3, M_TYPECFG_TYPE3) 573384740dcSRalf Baechle 574384740dcSRalf Baechle /* 575384740dcSRalf Baechle * MAC Receive Address Filter Control Registers (Table 9-24) 576384740dcSRalf Baechle * Register: MAC_ADFILTER_CFG_0 577384740dcSRalf Baechle * Register: MAC_ADFILTER_CFG_1 578384740dcSRalf Baechle * Register: MAC_ADFILTER_CFG_2 579384740dcSRalf Baechle */ 580384740dcSRalf Baechle 581384740dcSRalf Baechle #define M_MAC_ALLPKT_EN _SB_MAKEMASK1(0) 582384740dcSRalf Baechle #define M_MAC_UCAST_EN _SB_MAKEMASK1(1) 583384740dcSRalf Baechle #define M_MAC_UCAST_INV _SB_MAKEMASK1(2) 584384740dcSRalf Baechle #define M_MAC_MCAST_EN _SB_MAKEMASK1(3) 585384740dcSRalf Baechle #define M_MAC_MCAST_INV _SB_MAKEMASK1(4) 586384740dcSRalf Baechle #define M_MAC_BCAST_EN _SB_MAKEMASK1(5) 587384740dcSRalf Baechle #define M_MAC_DIRECT_INV _SB_MAKEMASK1(6) 588384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 589384740dcSRalf Baechle #define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7) 590384740dcSRalf Baechle #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 591384740dcSRalf Baechle 592384740dcSRalf Baechle #define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) 593384740dcSRalf Baechle #define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8, S_MAC_IPHDR_OFFSET) 594384740dcSRalf Baechle #define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_IPHDR_OFFSET) 595384740dcSRalf Baechle #define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x, S_MAC_IPHDR_OFFSET, M_MAC_IPHDR_OFFSET) 596384740dcSRalf Baechle 597384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 598384740dcSRalf Baechle #define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) 599384740dcSRalf Baechle #define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_RX_CRC_OFFSET) 600384740dcSRalf Baechle #define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_CRC_OFFSET) 601384740dcSRalf Baechle #define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_CRC_OFFSET, M_MAC_RX_CRC_OFFSET) 602384740dcSRalf Baechle 603384740dcSRalf Baechle #define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) 604384740dcSRalf Baechle #define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_RX_PKT_OFFSET) 605384740dcSRalf Baechle #define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_PKT_OFFSET) 606384740dcSRalf Baechle #define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_PKT_OFFSET, M_MAC_RX_PKT_OFFSET) 607384740dcSRalf Baechle 608384740dcSRalf Baechle #define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32) 609384740dcSRalf Baechle #define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33) 610384740dcSRalf Baechle 611384740dcSRalf Baechle #define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) 612384740dcSRalf Baechle #define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8, S_MAC_RX_CH_MSN_SEL) 613384740dcSRalf Baechle #define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_MSN_SEL) 614384740dcSRalf Baechle #define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_MSN_SEL, M_MAC_RX_CH_MSN_SEL) 615384740dcSRalf Baechle #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 616384740dcSRalf Baechle 617384740dcSRalf Baechle /* 618384740dcSRalf Baechle * MAC Receive Channel Select Registers (Table 9-25) 619384740dcSRalf Baechle */ 620384740dcSRalf Baechle 621384740dcSRalf Baechle /* no bitfields */ 622384740dcSRalf Baechle 623384740dcSRalf Baechle /* 624384740dcSRalf Baechle * MAC MII Management Interface Registers (Table 9-26) 625384740dcSRalf Baechle * Register: MAC_MDIO_0 626384740dcSRalf Baechle * Register: MAC_MDIO_1 627384740dcSRalf Baechle * Register: MAC_MDIO_2 628384740dcSRalf Baechle */ 629384740dcSRalf Baechle 630384740dcSRalf Baechle #define S_MAC_MDC 0 631384740dcSRalf Baechle #define S_MAC_MDIO_DIR 1 632384740dcSRalf Baechle #define S_MAC_MDIO_OUT 2 633384740dcSRalf Baechle #define S_MAC_GENC 3 634384740dcSRalf Baechle #define S_MAC_MDIO_IN 4 635384740dcSRalf Baechle 636384740dcSRalf Baechle #define M_MAC_MDC _SB_MAKEMASK1(S_MAC_MDC) 637384740dcSRalf Baechle #define M_MAC_MDIO_DIR _SB_MAKEMASK1(S_MAC_MDIO_DIR) 638384740dcSRalf Baechle #define M_MAC_MDIO_DIR_INPUT _SB_MAKEMASK1(S_MAC_MDIO_DIR) 639384740dcSRalf Baechle #define M_MAC_MDIO_OUT _SB_MAKEMASK1(S_MAC_MDIO_OUT) 640384740dcSRalf Baechle #define M_MAC_GENC _SB_MAKEMASK1(S_MAC_GENC) 641384740dcSRalf Baechle #define M_MAC_MDIO_IN _SB_MAKEMASK1(S_MAC_MDIO_IN) 642384740dcSRalf Baechle 643384740dcSRalf Baechle #endif 644