1*1a59d1b8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2384740dcSRalf Baechle /* ********************************************************************* 3384740dcSRalf Baechle * BCM1280/BCM1400 Board Support Package 4384740dcSRalf Baechle * 5384740dcSRalf Baechle * SCD Constants and Macros File: bcm1480_scd.h 6384740dcSRalf Baechle * 7384740dcSRalf Baechle * This module contains constants and macros useful for 8384740dcSRalf Baechle * manipulating the System Control and Debug module. 9384740dcSRalf Baechle * 10384740dcSRalf Baechle * BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03) 11384740dcSRalf Baechle * 12384740dcSRalf Baechle ********************************************************************* 13384740dcSRalf Baechle * 14384740dcSRalf Baechle * Copyright 2000,2001,2002,2003,2004,2005 15384740dcSRalf Baechle * Broadcom Corporation. All rights reserved. 16384740dcSRalf Baechle * 17384740dcSRalf Baechle ********************************************************************* */ 18384740dcSRalf Baechle 19384740dcSRalf Baechle #ifndef _BCM1480_SCD_H 20384740dcSRalf Baechle #define _BCM1480_SCD_H 21384740dcSRalf Baechle 22a1ce3928SDavid Howells #include <asm/sibyte/sb1250_defs.h> 23384740dcSRalf Baechle 24384740dcSRalf Baechle /* ********************************************************************* 25384740dcSRalf Baechle * Pull in the BCM1250's SCD since lots of stuff is the same. 26384740dcSRalf Baechle ********************************************************************* */ 27384740dcSRalf Baechle 28a1ce3928SDavid Howells #include <asm/sibyte/sb1250_scd.h> 29384740dcSRalf Baechle 30384740dcSRalf Baechle /* ********************************************************************* 31384740dcSRalf Baechle * Some general notes: 32384740dcSRalf Baechle * 33384740dcSRalf Baechle * This file is basically a "what's new" header file. Since the 34384740dcSRalf Baechle * BCM1250 and the new BCM1480 (and derivatives) share many common 35384740dcSRalf Baechle * features, this file contains only what's new or changed from 36384740dcSRalf Baechle * the 1250. (above, you can see that we include the 1250 symbols 37384740dcSRalf Baechle * to get the base functionality). 38384740dcSRalf Baechle * 39384740dcSRalf Baechle * In software, be sure to use the correct symbols, particularly 40384740dcSRalf Baechle * for blocks that are different between the two chip families. 41384740dcSRalf Baechle * All BCM1480-specific symbols have _BCM1480_ in their names, 42384740dcSRalf Baechle * and all BCM1250-specific and "base" functions that are common in 43384740dcSRalf Baechle * both chips have no special names (this is for compatibility with 44384740dcSRalf Baechle * older include files). Therefore, if you're working with the 45384740dcSRalf Baechle * SCD, which is very different on each chip, A_SCD_xxx implies 46384740dcSRalf Baechle * the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480 47384740dcSRalf Baechle * version. 48384740dcSRalf Baechle ********************************************************************* */ 49384740dcSRalf Baechle 50384740dcSRalf Baechle /* ********************************************************************* 51384740dcSRalf Baechle * System control/debug registers 52384740dcSRalf Baechle ********************************************************************* */ 53384740dcSRalf Baechle 54384740dcSRalf Baechle /* 55384740dcSRalf Baechle * System Identification and Revision Register (Table 12) 56384740dcSRalf Baechle * Register: SCD_SYSTEM_REVISION 57384740dcSRalf Baechle * This register is field compatible with the 1250. 58384740dcSRalf Baechle */ 59384740dcSRalf Baechle 60384740dcSRalf Baechle /* 61384740dcSRalf Baechle * New part definitions 62384740dcSRalf Baechle */ 63384740dcSRalf Baechle 64384740dcSRalf Baechle #define K_SYS_PART_BCM1480 0x1406 65384740dcSRalf Baechle #define K_SYS_PART_BCM1280 0x1206 66384740dcSRalf Baechle #define K_SYS_PART_BCM1455 0x1407 67384740dcSRalf Baechle #define K_SYS_PART_BCM1255 0x1257 68384740dcSRalf Baechle #define K_SYS_PART_BCM1158 0x1156 69384740dcSRalf Baechle 70384740dcSRalf Baechle /* 71384740dcSRalf Baechle * Manufacturing Information Register (Table 14) 72384740dcSRalf Baechle * Register: SCD_SYSTEM_MANUF 73384740dcSRalf Baechle */ 74384740dcSRalf Baechle 75384740dcSRalf Baechle /* 76384740dcSRalf Baechle * System Configuration Register (Table 15) 77384740dcSRalf Baechle * Register: SCD_SYSTEM_CFG 78384740dcSRalf Baechle * Entire register is different from 1250, all new constants below 79384740dcSRalf Baechle */ 80384740dcSRalf Baechle 81384740dcSRalf Baechle #define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0) 82384740dcSRalf Baechle #define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1) 83384740dcSRalf Baechle #define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2) 84384740dcSRalf Baechle #define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3) 85384740dcSRalf Baechle #define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4) 86384740dcSRalf Baechle #define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) 87384740dcSRalf Baechle 88384740dcSRalf Baechle #define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) 89384740dcSRalf Baechle #define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV) 90384740dcSRalf Baechle #define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV) 91384740dcSRalf Baechle #define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV) 92384740dcSRalf Baechle 93384740dcSRalf Baechle #define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) 94384740dcSRalf Baechle #define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV) 95384740dcSRalf Baechle #define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV) 96384740dcSRalf Baechle #define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV) 97384740dcSRalf Baechle 98384740dcSRalf Baechle #define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) 99384740dcSRalf Baechle #define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) 100384740dcSRalf Baechle 101384740dcSRalf Baechle #define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) 102384740dcSRalf Baechle #define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE) 103384740dcSRalf Baechle #define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE) 104384740dcSRalf Baechle #define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE) 105384740dcSRalf Baechle #define K_BCM1480_SYS_BOOT_MODE_ROM32 0 106384740dcSRalf Baechle #define K_BCM1480_SYS_BOOT_MODE_ROM8 1 107384740dcSRalf Baechle #define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2 108384740dcSRalf Baechle #define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG 3 109384740dcSRalf Baechle #define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19) 110384740dcSRalf Baechle 111384740dcSRalf Baechle #define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20) 112384740dcSRalf Baechle #define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21) 113384740dcSRalf Baechle #define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) 114384740dcSRalf Baechle #define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23) 115384740dcSRalf Baechle #define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24) 116384740dcSRalf Baechle #define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) 117384740dcSRalf Baechle 118384740dcSRalf Baechle #define S_BCM1480_SYS_CONFIG 26 119384740dcSRalf Baechle #define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG) 120384740dcSRalf Baechle #define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG) 121384740dcSRalf Baechle #define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG) 122384740dcSRalf Baechle 123384740dcSRalf Baechle #define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15) 124384740dcSRalf Baechle 125384740dcSRalf Baechle #define S_BCM1480_SYS_NODEID 47 126384740dcSRalf Baechle #define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID) 127384740dcSRalf Baechle #define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID) 128384740dcSRalf Baechle #define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID) 129384740dcSRalf Baechle 130384740dcSRalf Baechle #define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) 131384740dcSRalf Baechle #define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) 132384740dcSRalf Baechle #define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53) 133384740dcSRalf Baechle #define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54) 134384740dcSRalf Baechle #define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55) 135384740dcSRalf Baechle #define S_BCM1480_SYS_DISABLECPU0 56 136384740dcSRalf Baechle #define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0) 137384740dcSRalf Baechle #define S_BCM1480_SYS_DISABLECPU1 57 138384740dcSRalf Baechle #define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1) 139384740dcSRalf Baechle #define S_BCM1480_SYS_DISABLECPU2 58 140384740dcSRalf Baechle #define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2) 141384740dcSRalf Baechle #define S_BCM1480_SYS_DISABLECPU3 59 142384740dcSRalf Baechle #define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3) 143384740dcSRalf Baechle 144384740dcSRalf Baechle #define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60) 145384740dcSRalf Baechle #define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61) 146384740dcSRalf Baechle #define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62) 147384740dcSRalf Baechle #define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63) 148384740dcSRalf Baechle 149384740dcSRalf Baechle /* 150384740dcSRalf Baechle * Scratch Register (Table 16) 151384740dcSRalf Baechle * Register: SCD_SYSTEM_SCRATCH 152384740dcSRalf Baechle * Same as BCM1250 153384740dcSRalf Baechle */ 154384740dcSRalf Baechle 155384740dcSRalf Baechle 156384740dcSRalf Baechle /* 157384740dcSRalf Baechle * Mailbox Registers (Table 17) 158384740dcSRalf Baechle * Registers: SCD_MBOX_{0,1}_CPU_x 159384740dcSRalf Baechle * Same as BCM1250 160384740dcSRalf Baechle */ 161384740dcSRalf Baechle 162384740dcSRalf Baechle 163384740dcSRalf Baechle /* 164384740dcSRalf Baechle * See bcm1480_int.h for interrupt mapper registers. 165384740dcSRalf Baechle */ 166384740dcSRalf Baechle 167384740dcSRalf Baechle 168384740dcSRalf Baechle /* 169384740dcSRalf Baechle * Watchdog Timer Initial Count Registers (Table 23) 170384740dcSRalf Baechle * Registers: SCD_WDOG_INIT_CNT_x 171384740dcSRalf Baechle * 172384740dcSRalf Baechle * The watchdogs are almost the same as the 1250, except 173384740dcSRalf Baechle * the configuration register has more bits to control the 174384740dcSRalf Baechle * other CPUs. 175384740dcSRalf Baechle */ 176384740dcSRalf Baechle 177384740dcSRalf Baechle 178384740dcSRalf Baechle /* 179384740dcSRalf Baechle * Watchdog Timer Configuration Registers (Table 25) 180384740dcSRalf Baechle * Registers: SCD_WDOG_CFG_x 181384740dcSRalf Baechle */ 182384740dcSRalf Baechle 183384740dcSRalf Baechle #define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) 184384740dcSRalf Baechle 185384740dcSRalf Baechle #define S_BCM1480_SCD_WDOG_RESET_TYPE 2 186384740dcSRalf Baechle #define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE) 187384740dcSRalf Baechle #define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE) 188384740dcSRalf Baechle #define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE) 189384740dcSRalf Baechle 190384740dcSRalf Baechle #define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ 191384740dcSRalf Baechle #define K_BCM1480_SCD_WDOG_RESET_SOFT 1 192384740dcSRalf Baechle #define K_BCM1480_SCD_WDOG_RESET_CPU0 3 193384740dcSRalf Baechle #define K_BCM1480_SCD_WDOG_RESET_CPU1 5 194384740dcSRalf Baechle #define K_BCM1480_SCD_WDOG_RESET_CPU2 9 195384740dcSRalf Baechle #define K_BCM1480_SCD_WDOG_RESET_CPU3 17 196384740dcSRalf Baechle #define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS 31 197384740dcSRalf Baechle 198384740dcSRalf Baechle 199384740dcSRalf Baechle #define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8) 200384740dcSRalf Baechle 201384740dcSRalf Baechle /* 202384740dcSRalf Baechle * General Timer Initial Count Registers (Table 26) 203384740dcSRalf Baechle * Registers: SCD_TIMER_INIT_x 204384740dcSRalf Baechle * 205384740dcSRalf Baechle * The timer registers are the same as the BCM1250 206384740dcSRalf Baechle */ 207384740dcSRalf Baechle 208384740dcSRalf Baechle 209384740dcSRalf Baechle /* 210384740dcSRalf Baechle * ZBbus Count Register (Table 29) 211384740dcSRalf Baechle * Register: ZBBUS_CYCLE_COUNT 212384740dcSRalf Baechle * 213384740dcSRalf Baechle * Same as BCM1250 214384740dcSRalf Baechle */ 215384740dcSRalf Baechle 216384740dcSRalf Baechle /* 217384740dcSRalf Baechle * ZBbus Compare Registers (Table 30) 218384740dcSRalf Baechle * Registers: ZBBUS_CYCLE_CPx 219384740dcSRalf Baechle * 220384740dcSRalf Baechle * Same as BCM1250 221384740dcSRalf Baechle */ 222384740dcSRalf Baechle 223384740dcSRalf Baechle 224384740dcSRalf Baechle /* 225384740dcSRalf Baechle * System Performance Counter Configuration Register (Table 31) 226384740dcSRalf Baechle * Register: PERF_CNT_CFG_0 227384740dcSRalf Baechle * 228384740dcSRalf Baechle * SPC_CFG_SRC[0-3] is the same as the 1250. 229384740dcSRalf Baechle * SPC_CFG_SRC[4-7] only exist on the 1480 230384740dcSRalf Baechle * The clear/enable bits are in different locations on the 1250 and 1480. 231384740dcSRalf Baechle */ 232384740dcSRalf Baechle 233384740dcSRalf Baechle #define S_SPC_CFG_SRC4 32 234384740dcSRalf Baechle #define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4) 235384740dcSRalf Baechle #define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4) 236384740dcSRalf Baechle #define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4) 237384740dcSRalf Baechle 238384740dcSRalf Baechle #define S_SPC_CFG_SRC5 40 239384740dcSRalf Baechle #define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5) 240384740dcSRalf Baechle #define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5) 241384740dcSRalf Baechle #define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5) 242384740dcSRalf Baechle 243384740dcSRalf Baechle #define S_SPC_CFG_SRC6 48 244384740dcSRalf Baechle #define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6) 245384740dcSRalf Baechle #define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6) 246384740dcSRalf Baechle #define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6) 247384740dcSRalf Baechle 248384740dcSRalf Baechle #define S_SPC_CFG_SRC7 56 249384740dcSRalf Baechle #define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7) 250384740dcSRalf Baechle #define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7) 251384740dcSRalf Baechle #define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7) 252384740dcSRalf Baechle 253384740dcSRalf Baechle /* 254384740dcSRalf Baechle * System Performance Counter Control Register (Table 32) 255384740dcSRalf Baechle * Register: PERF_CNT_CFG_1 256384740dcSRalf Baechle * BCM1480 specific 257384740dcSRalf Baechle */ 258384740dcSRalf Baechle #define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) 259384740dcSRalf Baechle #define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1) 260384740dcSRalf Baechle #if SIBYTE_HDR_FEATURE_CHIP(1480) 261384740dcSRalf Baechle #define M_SPC_CFG_CLEAR M_BCM1480_SPC_CFG_CLEAR 262384740dcSRalf Baechle #define M_SPC_CFG_ENABLE M_BCM1480_SPC_CFG_ENABLE 263384740dcSRalf Baechle #endif 264384740dcSRalf Baechle 265384740dcSRalf Baechle /* 266384740dcSRalf Baechle * System Performance Counters (Table 33) 267384740dcSRalf Baechle * Registers: PERF_CNT_x 268384740dcSRalf Baechle */ 269384740dcSRalf Baechle 270384740dcSRalf Baechle #define S_BCM1480_SPC_CNT_COUNT 0 271384740dcSRalf Baechle #define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT) 272384740dcSRalf Baechle #define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT) 273384740dcSRalf Baechle #define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT) 274384740dcSRalf Baechle 275384740dcSRalf Baechle #define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) 276384740dcSRalf Baechle 277384740dcSRalf Baechle 278384740dcSRalf Baechle /* 279384740dcSRalf Baechle * Bus Watcher Error Status Register (Tables 36, 37) 280384740dcSRalf Baechle * Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG 281384740dcSRalf Baechle * Same as BCM1250. 282384740dcSRalf Baechle */ 283384740dcSRalf Baechle 284384740dcSRalf Baechle /* 285384740dcSRalf Baechle * Bus Watcher Error Data Registers (Table 38) 286384740dcSRalf Baechle * Registers: BUS_ERR_DATA_x 287384740dcSRalf Baechle * Same as BCM1250. 288384740dcSRalf Baechle */ 289384740dcSRalf Baechle 290384740dcSRalf Baechle /* 291384740dcSRalf Baechle * Bus Watcher L2 ECC Counter Register (Table 39) 292384740dcSRalf Baechle * Register: BUS_L2_ERRORS 293384740dcSRalf Baechle * Same as BCM1250. 294384740dcSRalf Baechle */ 295384740dcSRalf Baechle 296384740dcSRalf Baechle 297384740dcSRalf Baechle /* 298384740dcSRalf Baechle * Bus Watcher Memory and I/O Error Counter Register (Table 40) 299384740dcSRalf Baechle * Register: BUS_MEM_IO_ERRORS 300384740dcSRalf Baechle * Same as BCM1250. 301384740dcSRalf Baechle */ 302384740dcSRalf Baechle 303384740dcSRalf Baechle 304384740dcSRalf Baechle /* 305384740dcSRalf Baechle * Address Trap Registers 306384740dcSRalf Baechle * 307384740dcSRalf Baechle * Register layout same as BCM1250, almost. The bus agents 308384740dcSRalf Baechle * are different, and the address trap configuration bits are 309384740dcSRalf Baechle * slightly different. 310384740dcSRalf Baechle */ 311384740dcSRalf Baechle 312384740dcSRalf Baechle #define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4, 0) 313384740dcSRalf Baechle #define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) 314384740dcSRalf Baechle 315384740dcSRalf Baechle #define S_BCM1480_ATRAP_CFG_CNT 0 316384740dcSRalf Baechle #define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT) 317384740dcSRalf Baechle #define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT) 318384740dcSRalf Baechle #define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT) 319384740dcSRalf Baechle 320384740dcSRalf Baechle #define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) 321384740dcSRalf Baechle #define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) 322384740dcSRalf Baechle #define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5) 323384740dcSRalf Baechle #define M_BCM1480_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) 324384740dcSRalf Baechle #define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) 325384740dcSRalf Baechle 326384740dcSRalf Baechle #define S_BCM1480_ATRAP_CFG_AGENTID 8 327384740dcSRalf Baechle #define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID) 328384740dcSRalf Baechle #define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID) 329384740dcSRalf Baechle #define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID) 330384740dcSRalf Baechle 331384740dcSRalf Baechle 332384740dcSRalf Baechle #define K_BCM1480_BUS_AGENT_CPU0 0 333384740dcSRalf Baechle #define K_BCM1480_BUS_AGENT_CPU1 1 334384740dcSRalf Baechle #define K_BCM1480_BUS_AGENT_NC 2 335384740dcSRalf Baechle #define K_BCM1480_BUS_AGENT_IOB 3 336384740dcSRalf Baechle #define K_BCM1480_BUS_AGENT_SCD 4 337384740dcSRalf Baechle #define K_BCM1480_BUS_AGENT_L2C 6 338384740dcSRalf Baechle #define K_BCM1480_BUS_AGENT_MC 7 339384740dcSRalf Baechle #define K_BCM1480_BUS_AGENT_CPU2 8 340384740dcSRalf Baechle #define K_BCM1480_BUS_AGENT_CPU3 9 341384740dcSRalf Baechle #define K_BCM1480_BUS_AGENT_PM 10 342384740dcSRalf Baechle 343384740dcSRalf Baechle #define S_BCM1480_ATRAP_CFG_CATTR 12 344384740dcSRalf Baechle #define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR) 345384740dcSRalf Baechle #define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR) 346384740dcSRalf Baechle #define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR) 347384740dcSRalf Baechle 348384740dcSRalf Baechle #define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0 349384740dcSRalf Baechle #define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 350384740dcSRalf Baechle #define K_BCM1480_ATRAP_CFG_CATTR_NONCOH 2 351384740dcSRalf Baechle #define K_BCM1480_ATRAP_CFG_CATTR_COHERENT 3 352384740dcSRalf Baechle 353384740dcSRalf Baechle #define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14) 354384740dcSRalf Baechle 355384740dcSRalf Baechle 356384740dcSRalf Baechle /* 357384740dcSRalf Baechle * Trace Event Registers (Table 47) 358384740dcSRalf Baechle * Same as BCM1250. 359384740dcSRalf Baechle */ 360384740dcSRalf Baechle 361384740dcSRalf Baechle /* 362384740dcSRalf Baechle * Trace Sequence Control Registers (Table 48) 363384740dcSRalf Baechle * Registers: TRACE_SEQUENCE_x 364384740dcSRalf Baechle * 365384740dcSRalf Baechle * Same as BCM1250 except for two new fields. 366384740dcSRalf Baechle */ 367384740dcSRalf Baechle 368384740dcSRalf Baechle 369384740dcSRalf Baechle #define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25) 370384740dcSRalf Baechle 371384740dcSRalf Baechle #define S_BCM1480_SCD_TRSEQ_SWFUNC 26 372384740dcSRalf Baechle #define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC) 373384740dcSRalf Baechle #define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC) 374384740dcSRalf Baechle #define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC) 375384740dcSRalf Baechle 376384740dcSRalf Baechle /* 377384740dcSRalf Baechle * Trace Control Register (Table 49) 378384740dcSRalf Baechle * Register: TRACE_CFG 379384740dcSRalf Baechle * 380384740dcSRalf Baechle * BCM1480 changes to this register (other than location of the CUR_ADDR field) 381384740dcSRalf Baechle * are defined below. 382384740dcSRalf Baechle */ 383384740dcSRalf Baechle 384384740dcSRalf Baechle #define S_BCM1480_SCD_TRACE_CFG_MODE 16 385384740dcSRalf Baechle #define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE) 386384740dcSRalf Baechle #define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE) 387384740dcSRalf Baechle #define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE) 388384740dcSRalf Baechle 389384740dcSRalf Baechle #define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0 390384740dcSRalf Baechle #define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 391384740dcSRalf Baechle #define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2 392384740dcSRalf Baechle 393384740dcSRalf Baechle #endif /* _BCM1480_SCD_H */ 394