1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2384740dcSRalf Baechle /* 3384740dcSRalf Baechle * pi1.h: Definitions for SGI PI1 parallel port 4384740dcSRalf Baechle */ 5384740dcSRalf Baechle 6384740dcSRalf Baechle #ifndef _SGI_PI1_H 7384740dcSRalf Baechle #define _SGI_PI1_H 8384740dcSRalf Baechle 9384740dcSRalf Baechle struct pi1_regs { 10384740dcSRalf Baechle u8 _data[3]; 11384740dcSRalf Baechle volatile u8 data; 12384740dcSRalf Baechle u8 _ctrl[3]; 13384740dcSRalf Baechle volatile u8 ctrl; 14384740dcSRalf Baechle #define PI1_CTRL_STROBE_N 0x01 15384740dcSRalf Baechle #define PI1_CTRL_AFD_N 0x02 16384740dcSRalf Baechle #define PI1_CTRL_INIT_N 0x04 17384740dcSRalf Baechle #define PI1_CTRL_SLIN_N 0x08 18384740dcSRalf Baechle #define PI1_CTRL_IRQ_ENA 0x10 19384740dcSRalf Baechle #define PI1_CTRL_DIR 0x20 20384740dcSRalf Baechle #define PI1_CTRL_SEL 0x40 21384740dcSRalf Baechle u8 _status[3]; 22384740dcSRalf Baechle volatile u8 status; 23384740dcSRalf Baechle #define PI1_STAT_DEVID 0x03 /* bits 0-1 */ 24384740dcSRalf Baechle #define PI1_STAT_NOINK 0x04 /* SGI MODE only */ 25384740dcSRalf Baechle #define PI1_STAT_ERROR 0x08 26384740dcSRalf Baechle #define PI1_STAT_ONLINE 0x10 27384740dcSRalf Baechle #define PI1_STAT_PE 0x20 28384740dcSRalf Baechle #define PI1_STAT_ACK 0x40 29384740dcSRalf Baechle #define PI1_STAT_BUSY 0x80 30384740dcSRalf Baechle u8 _dmactrl[3]; 31384740dcSRalf Baechle volatile u8 dmactrl; 32384740dcSRalf Baechle #define PI1_DMACTRL_FIFO_EMPTY 0x01 /* fifo empty R/O */ 33384740dcSRalf Baechle #define PI1_DMACTRL_ABORT 0x02 /* reset DMA and internal fifo W/O */ 34384740dcSRalf Baechle #define PI1_DMACTRL_STDMODE 0x00 /* bits 2-3 */ 35384740dcSRalf Baechle #define PI1_DMACTRL_SGIMODE 0x04 /* bits 2-3 */ 36384740dcSRalf Baechle #define PI1_DMACTRL_RICOHMODE 0x08 /* bits 2-3 */ 37384740dcSRalf Baechle #define PI1_DMACTRL_HPMODE 0x0c /* bits 2-3 */ 38384740dcSRalf Baechle #define PI1_DMACTRL_BLKMODE 0x10 /* block mode */ 39384740dcSRalf Baechle #define PI1_DMACTRL_FIFO_CLEAR 0x20 /* clear fifo W/O */ 40384740dcSRalf Baechle #define PI1_DMACTRL_READ 0x40 /* read */ 41384740dcSRalf Baechle #define PI1_DMACTRL_RUN 0x80 /* pedal to the metal */ 42384740dcSRalf Baechle u8 _intstat[3]; 43384740dcSRalf Baechle volatile u8 intstat; 44384740dcSRalf Baechle #define PI1_INTSTAT_ACK 0x04 45384740dcSRalf Baechle #define PI1_INTSTAT_FEMPTY 0x08 46384740dcSRalf Baechle #define PI1_INTSTAT_NOINK 0x10 47384740dcSRalf Baechle #define PI1_INTSTAT_ONLINE 0x20 48384740dcSRalf Baechle #define PI1_INTSTAT_ERR 0x40 49384740dcSRalf Baechle #define PI1_INTSTAT_PE 0x80 50384740dcSRalf Baechle u8 _intmask[3]; 51384740dcSRalf Baechle volatile u8 intmask; /* enabled low, reset high*/ 52384740dcSRalf Baechle #define PI1_INTMASK_ACK 0x04 53384740dcSRalf Baechle #define PI1_INTMASK_FIFO_EMPTY 0x08 54384740dcSRalf Baechle #define PI1_INTMASK_NOINK 0x10 55384740dcSRalf Baechle #define PI1_INTMASK_ONLINE 0x20 56384740dcSRalf Baechle #define PI1_INTMASK_ERR 0x40 57384740dcSRalf Baechle #define PI1_INTMASK_PE 0x80 58384740dcSRalf Baechle u8 _timer1[3]; 59384740dcSRalf Baechle volatile u8 timer1; 60384740dcSRalf Baechle #define PI1_TIME1 0x27 61384740dcSRalf Baechle u8 _timer2[3]; 62384740dcSRalf Baechle volatile u8 timer2; 63384740dcSRalf Baechle #define PI1_TIME2 0x13 64384740dcSRalf Baechle u8 _timer3[3]; 65384740dcSRalf Baechle volatile u8 timer3; 66384740dcSRalf Baechle #define PI1_TIME3 0x10 67384740dcSRalf Baechle u8 _timer4[3]; 68384740dcSRalf Baechle volatile u8 timer4; 69384740dcSRalf Baechle #define PI1_TIME4 0x00 70384740dcSRalf Baechle }; 71384740dcSRalf Baechle 72384740dcSRalf Baechle #endif 73