1384740dcSRalf Baechle /* 2127993e5SSteven J. Hill * This file is subject to the terms and conditions of the GNU General Public 3127993e5SSteven J. Hill * License. See the file "COPYING" in the main directory of this archive 4384740dcSRalf Baechle * for more details. 5384740dcSRalf Baechle * 6384740dcSRalf Baechle * Defines of the MIPS boards specific address-MAP, registers, etc. 7127993e5SSteven J. Hill * 8127993e5SSteven J. Hill * Copyright (C) 2000,2012 MIPS Technologies, Inc. 9127993e5SSteven J. Hill * All rights reserved. 10127993e5SSteven J. Hill * Authors: Carsten Langgaard <carstenl@mips.com> 11127993e5SSteven J. Hill * Steven J. Hill <sjhill@mips.com> 12384740dcSRalf Baechle */ 13384740dcSRalf Baechle #ifndef __ASM_MIPS_BOARDS_GENERIC_H 14384740dcSRalf Baechle #define __ASM_MIPS_BOARDS_GENERIC_H 15384740dcSRalf Baechle 16384740dcSRalf Baechle #include <asm/addrspace.h> 17384740dcSRalf Baechle #include <asm/byteorder.h> 18384740dcSRalf Baechle #include <asm/mips-boards/bonito64.h> 19384740dcSRalf Baechle 20384740dcSRalf Baechle /* 21384740dcSRalf Baechle * Display register base. 22384740dcSRalf Baechle */ 23384740dcSRalf Baechle #define ASCII_DISPLAY_WORD_BASE 0x1f000410 24384740dcSRalf Baechle #define ASCII_DISPLAY_POS_BASE 0x1f000418 25384740dcSRalf Baechle 26384740dcSRalf Baechle /* 27384740dcSRalf Baechle * Revision register. 28384740dcSRalf Baechle */ 29384740dcSRalf Baechle #define MIPS_REVISION_REG 0x1fc00010 30384740dcSRalf Baechle #define MIPS_REVISION_CORID_QED_RM5261 0 31384740dcSRalf Baechle #define MIPS_REVISION_CORID_CORE_LV 1 32384740dcSRalf Baechle #define MIPS_REVISION_CORID_BONITO64 2 33384740dcSRalf Baechle #define MIPS_REVISION_CORID_CORE_20K 3 34384740dcSRalf Baechle #define MIPS_REVISION_CORID_CORE_FPGA 4 35384740dcSRalf Baechle #define MIPS_REVISION_CORID_CORE_MSC 5 36384740dcSRalf Baechle #define MIPS_REVISION_CORID_CORE_EMUL 6 37384740dcSRalf Baechle #define MIPS_REVISION_CORID_CORE_FPGA2 7 38384740dcSRalf Baechle #define MIPS_REVISION_CORID_CORE_FPGAR2 8 39384740dcSRalf Baechle #define MIPS_REVISION_CORID_CORE_FPGA3 9 40384740dcSRalf Baechle #define MIPS_REVISION_CORID_CORE_24K 10 41384740dcSRalf Baechle #define MIPS_REVISION_CORID_CORE_FPGA4 11 42384740dcSRalf Baechle #define MIPS_REVISION_CORID_CORE_FPGA5 12 43384740dcSRalf Baechle 44384740dcSRalf Baechle /**** Artificial corid defines ****/ 45384740dcSRalf Baechle /* 46384740dcSRalf Baechle * CoreEMUL with Bonito System Controller is treated like a Core20K 47384740dcSRalf Baechle * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC 48384740dcSRalf Baechle */ 49384740dcSRalf Baechle #define MIPS_REVISION_CORID_CORE_EMUL_BON -1 50384740dcSRalf Baechle #define MIPS_REVISION_CORID_CORE_EMUL_MSC -2 51384740dcSRalf Baechle 52384740dcSRalf Baechle #define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) 53384740dcSRalf Baechle 54384740dcSRalf Baechle #define MIPS_REVISION_SCON_OTHER 0 55384740dcSRalf Baechle #define MIPS_REVISION_SCON_SOCITSC 1 56384740dcSRalf Baechle #define MIPS_REVISION_SCON_SOCITSCP 2 57384740dcSRalf Baechle 58384740dcSRalf Baechle /* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */ 59384740dcSRalf Baechle #define MIPS_REVISION_SCON_UNKNOWN -1 60384740dcSRalf Baechle #define MIPS_REVISION_SCON_GT64120 -2 61384740dcSRalf Baechle #define MIPS_REVISION_SCON_BONITO -3 62384740dcSRalf Baechle #define MIPS_REVISION_SCON_BRTL -4 63384740dcSRalf Baechle #define MIPS_REVISION_SCON_SOCIT -5 64384740dcSRalf Baechle #define MIPS_REVISION_SCON_ROCIT -6 65384740dcSRalf Baechle 66384740dcSRalf Baechle #define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff) 67384740dcSRalf Baechle 68384740dcSRalf Baechle extern int mips_revision_sconid; 69384740dcSRalf Baechle 70384740dcSRalf Baechle #ifdef CONFIG_PCI 71384740dcSRalf Baechle extern void mips_pcibios_init(void); 72384740dcSRalf Baechle #else 73384740dcSRalf Baechle #define mips_pcibios_init() do { } while (0) 74384740dcSRalf Baechle #endif 75384740dcSRalf Baechle 76*98ffcf60SSteven J. Hill extern void mips_scroll_message(void); 77*98ffcf60SSteven J. Hill extern void mips_display_message(const char *str); 78*98ffcf60SSteven J. Hill 79384740dcSRalf Baechle #endif /* __ASM_MIPS_BOARDS_GENERIC_H */ 80