1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2de3eb02aSGabor Juhos /* 3de3eb02aSGabor Juhos * Ralink RT3662/RT3883 specific CPU feature overrides 4de3eb02aSGabor Juhos * 5de3eb02aSGabor Juhos * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org> 6de3eb02aSGabor Juhos * 7de3eb02aSGabor Juhos * This file was derived from: include/asm-mips/cpu-features.h 8de3eb02aSGabor Juhos * Copyright (C) 2003, 2004 Ralf Baechle 9de3eb02aSGabor Juhos * Copyright (C) 2004 Maciej W. Rozycki 10de3eb02aSGabor Juhos */ 11de3eb02aSGabor Juhos #ifndef _RT3883_CPU_FEATURE_OVERRIDES_H 12de3eb02aSGabor Juhos #define _RT3883_CPU_FEATURE_OVERRIDES_H 13de3eb02aSGabor Juhos 14de3eb02aSGabor Juhos #define cpu_has_tlb 1 15de3eb02aSGabor Juhos #define cpu_has_4kex 1 16de3eb02aSGabor Juhos #define cpu_has_3k_cache 0 17de3eb02aSGabor Juhos #define cpu_has_4k_cache 1 18de3eb02aSGabor Juhos #define cpu_has_sb1_cache 0 19de3eb02aSGabor Juhos #define cpu_has_fpu 0 20de3eb02aSGabor Juhos #define cpu_has_32fpr 0 21de3eb02aSGabor Juhos #define cpu_has_counter 1 22de3eb02aSGabor Juhos #define cpu_has_watch 1 23de3eb02aSGabor Juhos #define cpu_has_divec 1 24de3eb02aSGabor Juhos 25de3eb02aSGabor Juhos #define cpu_has_prefetch 1 26de3eb02aSGabor Juhos #define cpu_has_ejtag 1 27de3eb02aSGabor Juhos #define cpu_has_llsc 1 28de3eb02aSGabor Juhos 29de3eb02aSGabor Juhos #define cpu_has_mips16 1 30de3eb02aSGabor Juhos #define cpu_has_mdmx 0 31de3eb02aSGabor Juhos #define cpu_has_mips3d 0 32de3eb02aSGabor Juhos #define cpu_has_smartmips 0 33de3eb02aSGabor Juhos 34de3eb02aSGabor Juhos #define cpu_has_mips32r1 1 35de3eb02aSGabor Juhos #define cpu_has_mips32r2 1 36de3eb02aSGabor Juhos #define cpu_has_mips64r1 0 37de3eb02aSGabor Juhos #define cpu_has_mips64r2 0 38de3eb02aSGabor Juhos 39de3eb02aSGabor Juhos #define cpu_has_dsp 1 40de3eb02aSGabor Juhos #define cpu_has_mipsmt 0 41de3eb02aSGabor Juhos 42de3eb02aSGabor Juhos #define cpu_has_64bits 0 43de3eb02aSGabor Juhos #define cpu_has_64bit_zero_reg 0 44de3eb02aSGabor Juhos #define cpu_has_64bit_gp_regs 0 45de3eb02aSGabor Juhos 46de3eb02aSGabor Juhos #define cpu_dcache_line_size() 32 47de3eb02aSGabor Juhos #define cpu_icache_line_size() 32 48de3eb02aSGabor Juhos 49de3eb02aSGabor Juhos #endif /* _RT3883_CPU_FEATURE_OVERRIDES_H */ 50