1*2572f00dSJoshua Henderson /* 2*2572f00dSJoshua Henderson * Joshua Henderson <joshua.henderson@microchip.com> 3*2572f00dSJoshua Henderson * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. 4*2572f00dSJoshua Henderson * 5*2572f00dSJoshua Henderson * This file is subject to the terms and conditions of the GNU General Public 6*2572f00dSJoshua Henderson * License. See the file "COPYING" in the main directory of this archive 7*2572f00dSJoshua Henderson * for more details. 8*2572f00dSJoshua Henderson */ 9*2572f00dSJoshua Henderson #ifndef __ASM_MACH_PIC32_CPU_FEATURE_OVERRIDES_H 10*2572f00dSJoshua Henderson #define __ASM_MACH_PIC32_CPU_FEATURE_OVERRIDES_H 11*2572f00dSJoshua Henderson 12*2572f00dSJoshua Henderson /* 13*2572f00dSJoshua Henderson * CPU feature overrides for PIC32 boards 14*2572f00dSJoshua Henderson */ 15*2572f00dSJoshua Henderson #ifdef CONFIG_CPU_MIPS32 16*2572f00dSJoshua Henderson #define cpu_has_vint 1 17*2572f00dSJoshua Henderson #define cpu_has_veic 0 18*2572f00dSJoshua Henderson #define cpu_has_tlb 1 19*2572f00dSJoshua Henderson #define cpu_has_4kex 1 20*2572f00dSJoshua Henderson #define cpu_has_4k_cache 1 21*2572f00dSJoshua Henderson #define cpu_has_fpu 0 22*2572f00dSJoshua Henderson #define cpu_has_counter 1 23*2572f00dSJoshua Henderson #define cpu_has_llsc 1 24*2572f00dSJoshua Henderson #define cpu_has_nofpuex 0 25*2572f00dSJoshua Henderson #define cpu_icache_snoops_remote_store 1 26*2572f00dSJoshua Henderson #endif 27*2572f00dSJoshua Henderson 28*2572f00dSJoshua Henderson #ifdef CONFIG_CPU_MIPS64 29*2572f00dSJoshua Henderson #error This platform does not support 64bit. 30*2572f00dSJoshua Henderson #endif 31*2572f00dSJoshua Henderson 32*2572f00dSJoshua Henderson #endif /* __ASM_MACH_PIC32_CPU_FEATURE_OVERRIDES_H */ 33