1384740dcSRalf Baechle /* 2384740dcSRalf Baechle * Cobalt IRQ definitions. 3384740dcSRalf Baechle * 4384740dcSRalf Baechle * This file is subject to the terms and conditions of the GNU General Public 5384740dcSRalf Baechle * License. See the file "COPYING" in the main directory of this archive 6384740dcSRalf Baechle * for more details. 7384740dcSRalf Baechle * 8384740dcSRalf Baechle * Copyright (C) 1997 Cobalt Microserver 9384740dcSRalf Baechle * Copyright (C) 1997, 2003 Ralf Baechle 10384740dcSRalf Baechle * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv) 11*ada8e951SYoichi Yuasa * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org> 12384740dcSRalf Baechle */ 13384740dcSRalf Baechle #ifndef _ASM_COBALT_IRQ_H 14384740dcSRalf Baechle #define _ASM_COBALT_IRQ_H 15384740dcSRalf Baechle 16384740dcSRalf Baechle /* 17384740dcSRalf Baechle * i8259 interrupts used on Cobalt: 18384740dcSRalf Baechle * 19384740dcSRalf Baechle * 8 - RTC 20384740dcSRalf Baechle * 9 - PCI slot 21384740dcSRalf Baechle * 14 - IDE0 22384740dcSRalf Baechle * 15 - IDE1(no connector on board) 23384740dcSRalf Baechle */ 24384740dcSRalf Baechle #define I8259A_IRQ_BASE 0 25384740dcSRalf Baechle 26384740dcSRalf Baechle #define PCISLOT_IRQ (I8259A_IRQ_BASE + 9) 27384740dcSRalf Baechle 28384740dcSRalf Baechle /* 29384740dcSRalf Baechle * CPU interrupts used on Cobalt: 30384740dcSRalf Baechle * 31384740dcSRalf Baechle * 0 - Software interrupt 0 (unused) 32384740dcSRalf Baechle * 1 - Software interrupt 0 (unused) 33384740dcSRalf Baechle * 2 - cascade GT64111 34384740dcSRalf Baechle * 3 - ethernet or SCSI host controller 35384740dcSRalf Baechle * 4 - ethernet 36384740dcSRalf Baechle * 5 - 16550 UART 37384740dcSRalf Baechle * 6 - cascade i8259 38384740dcSRalf Baechle * 7 - CP0 counter 39384740dcSRalf Baechle */ 40384740dcSRalf Baechle #define MIPS_CPU_IRQ_BASE 16 41384740dcSRalf Baechle 42384740dcSRalf Baechle #define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2) 43384740dcSRalf Baechle #define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3) 44384740dcSRalf Baechle #define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3) 45384740dcSRalf Baechle #define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4) 46384740dcSRalf Baechle #define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4) 47384740dcSRalf Baechle #define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5) 48384740dcSRalf Baechle #define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5) 49384740dcSRalf Baechle #define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6) 50384740dcSRalf Baechle 51384740dcSRalf Baechle #define GT641XX_IRQ_BASE 24 52384740dcSRalf Baechle 53384740dcSRalf Baechle #include <asm/irq_gt641xx.h> 54384740dcSRalf Baechle 55384740dcSRalf Baechle #define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1) 56384740dcSRalf Baechle 57384740dcSRalf Baechle #endif /* _ASM_COBALT_IRQ_H */ 58