15b3b1688SDavid Daney /* 25b3b1688SDavid Daney * This file is subject to the terms and conditions of the GNU General Public 35b3b1688SDavid Daney * License. See the file "COPYING" in the main directory of this archive 45b3b1688SDavid Daney * for more details. 55b3b1688SDavid Daney * 65b3b1688SDavid Daney * Copyright (C) 2004 Cavium Networks 75b3b1688SDavid Daney */ 85b3b1688SDavid Daney #ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H 95b3b1688SDavid Daney #define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H 105b3b1688SDavid Daney 115b3b1688SDavid Daney #include <linux/types.h> 125b3b1688SDavid Daney #include <asm/mipsregs.h> 135b3b1688SDavid Daney 145b3b1688SDavid Daney /* 155b3b1688SDavid Daney * Cavium Octeons are MIPS64v2 processors 165b3b1688SDavid Daney */ 175b3b1688SDavid Daney #define cpu_dcache_line_size() 128 185b3b1688SDavid Daney #define cpu_icache_line_size() 128 195b3b1688SDavid Daney 205b3b1688SDavid Daney 215b3b1688SDavid Daney #define cpu_has_4kex 1 225b3b1688SDavid Daney #define cpu_has_3k_cache 0 235b3b1688SDavid Daney #define cpu_has_4k_cache 0 245b3b1688SDavid Daney #define cpu_has_counter 1 255b3b1688SDavid Daney #define cpu_has_watch 1 265b3b1688SDavid Daney #define cpu_has_divec 1 275b3b1688SDavid Daney #define cpu_has_vce 0 285b3b1688SDavid Daney #define cpu_has_cache_cdex_p 0 295b3b1688SDavid Daney #define cpu_has_cache_cdex_s 0 305b3b1688SDavid Daney #define cpu_has_prefetch 1 315b3b1688SDavid Daney 325b3b1688SDavid Daney #define cpu_has_llsc 1 339d24bafbSDavid Daney /* 349d24bafbSDavid Daney * We Disable LL/SC on non SMP systems as it is faster to disable 359d24bafbSDavid Daney * interrupts for atomic access than a LL/SC. 369d24bafbSDavid Daney */ 379d24bafbSDavid Daney #ifdef CONFIG_SMP 389d24bafbSDavid Daney # define kernel_uses_llsc 1 399d24bafbSDavid Daney #else 409d24bafbSDavid Daney # define kernel_uses_llsc 0 419d24bafbSDavid Daney #endif 425b3b1688SDavid Daney #define cpu_has_vtag_icache 1 435b3b1688SDavid Daney #define cpu_has_dc_aliases 0 445b3b1688SDavid Daney #define cpu_has_ic_fills_f_dc 0 455b3b1688SDavid Daney #define cpu_has_64bits 1 465b3b1688SDavid Daney #define cpu_has_octeon_cache 1 47*846fbcfeSPetar Jovanovic #define cpu_has_mips32r1 1 48*846fbcfeSPetar Jovanovic #define cpu_has_mips32r2 1 49*846fbcfeSPetar Jovanovic #define cpu_has_mips64r1 1 505b3b1688SDavid Daney #define cpu_has_mips64r2 1 515b3b1688SDavid Daney #define cpu_has_dsp 0 5247503256SRalf Baechle #define cpu_has_dsp2 0 535b3b1688SDavid Daney #define cpu_has_mipsmt 0 545b3b1688SDavid Daney #define cpu_has_vint 0 555b3b1688SDavid Daney #define cpu_has_veic 0 56aff565aaSJames Hogan #define cpu_hwrena_impl_bits (MIPS_HWRENA_IMPL1 | MIPS_HWRENA_IMPL2) 573c09bae4SChen Jie #define cpu_has_wsbh 1 5827a5bd64SDavid Daney 5905857c64SSteven J. Hill #define cpu_has_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON) 6027a5bd64SDavid Daney 615b3b1688SDavid Daney #define PREFETCH_STRIDE 128 625b3b1688SDavid Daney 631d1929c7SDavid Daney #ifdef __OCTEON__ 641d1929c7SDavid Daney /* 651d1929c7SDavid Daney * All gcc versions that have OCTEON support define __OCTEON__ and have the 661d1929c7SDavid Daney * __builtin_popcount support. 671d1929c7SDavid Daney */ 681d1929c7SDavid Daney #define ARCH_HAS_USABLE_BUILTIN_POPCOUNT 1 691d1929c7SDavid Daney #endif 701d1929c7SDavid Daney 7157575b5cSDavid Daney /* 7257575b5cSDavid Daney * The last 256MB are reserved for device to device mappings and the 7357575b5cSDavid Daney * BAR1 hole. 7457575b5cSDavid Daney */ 7557575b5cSDavid Daney #define MAX_DMA32_PFN (((1ULL << 32) - (1ULL << 28)) >> PAGE_SHIFT) 7657575b5cSDavid Daney 775b3b1688SDavid Daney #endif 78