1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 243cc739fSSergey Ryazanov /* 343cc739fSSergey Ryazanov * Atheros AR231x/AR531x SoC specific CPU feature overrides 443cc739fSSergey Ryazanov * 543cc739fSSergey Ryazanov * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org> 643cc739fSSergey Ryazanov * 743cc739fSSergey Ryazanov * This file was derived from: include/asm-mips/cpu-features.h 843cc739fSSergey Ryazanov * Copyright (C) 2003, 2004 Ralf Baechle 943cc739fSSergey Ryazanov * Copyright (C) 2004 Maciej W. Rozycki 1043cc739fSSergey Ryazanov */ 1143cc739fSSergey Ryazanov #ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H 1243cc739fSSergey Ryazanov #define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H 1343cc739fSSergey Ryazanov 1443cc739fSSergey Ryazanov /* 1543cc739fSSergey Ryazanov * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core. 1643cc739fSSergey Ryazanov */ 1743cc739fSSergey Ryazanov #define cpu_has_tlb 1 1843cc739fSSergey Ryazanov #define cpu_has_4kex 1 1943cc739fSSergey Ryazanov #define cpu_has_3k_cache 0 2043cc739fSSergey Ryazanov #define cpu_has_4k_cache 1 2143cc739fSSergey Ryazanov #define cpu_has_sb1_cache 0 2243cc739fSSergey Ryazanov #define cpu_has_fpu 0 2343cc739fSSergey Ryazanov #define cpu_has_32fpr 0 2443cc739fSSergey Ryazanov #define cpu_has_counter 1 2543cc739fSSergey Ryazanov #define cpu_has_ejtag 1 2643cc739fSSergey Ryazanov 27ba910345SSergey Ryazanov #if !defined(CONFIG_SOC_AR5312) 28ba910345SSergey Ryazanov # define cpu_has_llsc 1 29ba910345SSergey Ryazanov #else 3043cc739fSSergey Ryazanov /* 3143cc739fSSergey Ryazanov * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the 3243cc739fSSergey Ryazanov * ll/sc instructions. 3343cc739fSSergey Ryazanov */ 3443cc739fSSergey Ryazanov # define cpu_has_llsc 0 35ba910345SSergey Ryazanov #endif 3643cc739fSSergey Ryazanov 3743cc739fSSergey Ryazanov #define cpu_has_mips16 0 3865ae8d26SMaciej W. Rozycki #define cpu_has_mips16e2 0 3943cc739fSSergey Ryazanov #define cpu_has_mdmx 0 4043cc739fSSergey Ryazanov #define cpu_has_mips3d 0 4143cc739fSSergey Ryazanov #define cpu_has_smartmips 0 4243cc739fSSergey Ryazanov 4343cc739fSSergey Ryazanov #define cpu_has_mips32r1 1 4443cc739fSSergey Ryazanov 45ba910345SSergey Ryazanov #if !defined(CONFIG_SOC_AR5312) 46ba910345SSergey Ryazanov # define cpu_has_mips32r2 1 47ba910345SSergey Ryazanov #endif 48ba910345SSergey Ryazanov 4943cc739fSSergey Ryazanov #define cpu_has_mips64r1 0 5043cc739fSSergey Ryazanov #define cpu_has_mips64r2 0 5143cc739fSSergey Ryazanov 5243cc739fSSergey Ryazanov #define cpu_has_dsp 0 5343cc739fSSergey Ryazanov #define cpu_has_mipsmt 0 5443cc739fSSergey Ryazanov 5543cc739fSSergey Ryazanov #define cpu_has_64bits 0 5643cc739fSSergey Ryazanov #define cpu_has_64bit_zero_reg 0 5743cc739fSSergey Ryazanov #define cpu_has_64bit_gp_regs 0 5843cc739fSSergey Ryazanov 5943cc739fSSergey Ryazanov #endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */ 60