1*384740dcSRalf Baechle /* 2*384740dcSRalf Baechle * This file is subject to the terms and conditions of the GNU General Public 3*384740dcSRalf Baechle * License. See the file "COPYING" in the main directory of this archive 4*384740dcSRalf Baechle * for more details. 5*384740dcSRalf Baechle * 6*384740dcSRalf Baechle * Definitions for the interrupt related bits in the I/O ASIC 7*384740dcSRalf Baechle * interrupt status register (and the interrupt mask register, of course) 8*384740dcSRalf Baechle * 9*384740dcSRalf Baechle * Created with Information from: 10*384740dcSRalf Baechle * 11*384740dcSRalf Baechle * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual" 12*384740dcSRalf Baechle * 13*384740dcSRalf Baechle * and the Mach Sources 14*384740dcSRalf Baechle * 15*384740dcSRalf Baechle * Copyright (C) 199x the Anonymous 16*384740dcSRalf Baechle * Copyright (C) 2002 Maciej W. Rozycki 17*384740dcSRalf Baechle */ 18*384740dcSRalf Baechle 19*384740dcSRalf Baechle #ifndef __ASM_DEC_IOASIC_INTS_H 20*384740dcSRalf Baechle #define __ASM_DEC_IOASIC_INTS_H 21*384740dcSRalf Baechle 22*384740dcSRalf Baechle /* 23*384740dcSRalf Baechle * The upper 16 bits are a part of the I/O ASIC's internal DMA engine 24*384740dcSRalf Baechle * and thus are common to all I/O ASIC machines. The exception is 25*384740dcSRalf Baechle * the Maxine, which makes use of the FLOPPY and ISDN bits (otherwise 26*384740dcSRalf Baechle * unused) and has a different SCC wiring. 27*384740dcSRalf Baechle */ 28*384740dcSRalf Baechle /* all systems */ 29*384740dcSRalf Baechle #define IO_INR_SCC0A_TXDMA 31 /* SCC0A transmit page end */ 30*384740dcSRalf Baechle #define IO_INR_SCC0A_TXERR 30 /* SCC0A transmit memory read error */ 31*384740dcSRalf Baechle #define IO_INR_SCC0A_RXDMA 29 /* SCC0A receive half page */ 32*384740dcSRalf Baechle #define IO_INR_SCC0A_RXERR 28 /* SCC0A receive overrun */ 33*384740dcSRalf Baechle #define IO_INR_ASC_DMA 19 /* ASC buffer pointer loaded */ 34*384740dcSRalf Baechle #define IO_INR_ASC_ERR 18 /* ASC page overrun */ 35*384740dcSRalf Baechle #define IO_INR_ASC_MERR 17 /* ASC memory read error */ 36*384740dcSRalf Baechle #define IO_INR_LANCE_MERR 16 /* LANCE memory read error */ 37*384740dcSRalf Baechle 38*384740dcSRalf Baechle /* except Maxine */ 39*384740dcSRalf Baechle #define IO_INR_SCC1A_TXDMA 27 /* SCC1A transmit page end */ 40*384740dcSRalf Baechle #define IO_INR_SCC1A_TXERR 26 /* SCC1A transmit memory read error */ 41*384740dcSRalf Baechle #define IO_INR_SCC1A_RXDMA 25 /* SCC1A receive half page */ 42*384740dcSRalf Baechle #define IO_INR_SCC1A_RXERR 24 /* SCC1A receive overrun */ 43*384740dcSRalf Baechle #define IO_INR_RES_23 23 /* unused */ 44*384740dcSRalf Baechle #define IO_INR_RES_22 22 /* unused */ 45*384740dcSRalf Baechle #define IO_INR_RES_21 21 /* unused */ 46*384740dcSRalf Baechle #define IO_INR_RES_20 20 /* unused */ 47*384740dcSRalf Baechle 48*384740dcSRalf Baechle /* Maxine */ 49*384740dcSRalf Baechle #define IO_INR_AB_TXDMA 27 /* ACCESS.bus transmit page end */ 50*384740dcSRalf Baechle #define IO_INR_AB_TXERR 26 /* ACCESS.bus xmit memory read error */ 51*384740dcSRalf Baechle #define IO_INR_AB_RXDMA 25 /* ACCESS.bus receive half page */ 52*384740dcSRalf Baechle #define IO_INR_AB_RXERR 24 /* ACCESS.bus receive overrun */ 53*384740dcSRalf Baechle #define IO_INR_FLOPPY_ERR 23 /* FDC error */ 54*384740dcSRalf Baechle #define IO_INR_ISDN_TXDMA 22 /* ISDN xmit buffer pointer loaded */ 55*384740dcSRalf Baechle #define IO_INR_ISDN_RXDMA 21 /* ISDN recv buffer pointer loaded */ 56*384740dcSRalf Baechle #define IO_INR_ISDN_ERR 20 /* ISDN memory read/overrun error */ 57*384740dcSRalf Baechle 58*384740dcSRalf Baechle #define IO_INR_DMA 16 /* first DMA IRQ */ 59*384740dcSRalf Baechle 60*384740dcSRalf Baechle /* 61*384740dcSRalf Baechle * The lower 16 bits are system-specific and thus defined in 62*384740dcSRalf Baechle * system-specific headers. 63*384740dcSRalf Baechle */ 64*384740dcSRalf Baechle 65*384740dcSRalf Baechle 66*384740dcSRalf Baechle #define IO_IRQ_BASE 8 /* first IRQ assigned to I/O ASIC */ 67*384740dcSRalf Baechle #define IO_IRQ_LINES 32 /* number of I/O ASIC interrupts */ 68*384740dcSRalf Baechle 69*384740dcSRalf Baechle #define IO_IRQ_NR(n) ((n) + IO_IRQ_BASE) 70*384740dcSRalf Baechle #define IO_IRQ_MASK(n) (1 << (n)) 71*384740dcSRalf Baechle #define IO_IRQ_ALL 0x0000ffff 72*384740dcSRalf Baechle #define IO_IRQ_DMA 0xffff0000 73*384740dcSRalf Baechle 74*384740dcSRalf Baechle #endif /* __ASM_DEC_IOASIC_INTS_H */ 75