xref: /openbmc/linux/arch/mips/include/asm/cpu.h (revision 0c94fa33b4de55a0dcb60519ba04a0fd49da124d)
1384740dcSRalf Baechle /*
2384740dcSRalf Baechle  * cpu.h: Values of the PRId register used to match up
3384740dcSRalf Baechle  *	  various MIPS cpu types.
4384740dcSRalf Baechle  *
579add627SJustin P. Mattock  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
68ff374b9SMaciej W. Rozycki  * Copyright (C) 2004, 2013  Maciej W. Rozycki
7384740dcSRalf Baechle  */
8384740dcSRalf Baechle #ifndef _ASM_CPU_H
9384740dcSRalf Baechle #define _ASM_CPU_H
10384740dcSRalf Baechle 
118ff374b9SMaciej W. Rozycki /*
128ff374b9SMaciej W. Rozycki    As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
138ff374b9SMaciej W. Rozycki    register 15, select 0) is defined in this (backwards compatible) way:
14384740dcSRalf Baechle 
15384740dcSRalf Baechle   +----------------+----------------+----------------+----------------+
16384740dcSRalf Baechle   | Company Options| Company ID	    | Processor ID   | Revision	      |
17384740dcSRalf Baechle   +----------------+----------------+----------------+----------------+
18384740dcSRalf Baechle    31		 24 23		  16 15		    8 7
19384740dcSRalf Baechle 
20384740dcSRalf Baechle    I don't have docs for all the previous processors, but my impression is
21384740dcSRalf Baechle    that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
22384740dcSRalf Baechle    spec.
23384740dcSRalf Baechle */
24384740dcSRalf Baechle 
258ff374b9SMaciej W. Rozycki #define PRID_OPT_MASK		0xff000000
268ff374b9SMaciej W. Rozycki 
278ff374b9SMaciej W. Rozycki /*
288ff374b9SMaciej W. Rozycki  * Assigned Company values for bits 23:16 of the PRId register.
298ff374b9SMaciej W. Rozycki  */
308ff374b9SMaciej W. Rozycki 
318ff374b9SMaciej W. Rozycki #define PRID_COMP_MASK		0xff0000
328ff374b9SMaciej W. Rozycki 
33384740dcSRalf Baechle #define PRID_COMP_LEGACY	0x000000
34384740dcSRalf Baechle #define PRID_COMP_MIPS		0x010000
35384740dcSRalf Baechle #define PRID_COMP_BROADCOM	0x020000
36384740dcSRalf Baechle #define PRID_COMP_ALCHEMY	0x030000
37384740dcSRalf Baechle #define PRID_COMP_SIBYTE	0x040000
38384740dcSRalf Baechle #define PRID_COMP_SANDCRAFT	0x050000
39384740dcSRalf Baechle #define PRID_COMP_NXP		0x060000
40384740dcSRalf Baechle #define PRID_COMP_TOSHIBA	0x070000
41384740dcSRalf Baechle #define PRID_COMP_LSI		0x080000
42384740dcSRalf Baechle #define PRID_COMP_LEXRA		0x0b0000
43a7117c6bSJayachandran C #define PRID_COMP_NETLOGIC	0x0c0000
440dd4781bSDavid Daney #define PRID_COMP_CAVIUM	0x0d0000
45252617a4SPaul Burton #define PRID_COMP_INGENIC_D0	0xd00000	/* JZ4740, JZ4750 */
46252617a4SPaul Burton #define PRID_COMP_INGENIC_D1	0xd10000	/* JZ4770, JZ4775 */
47252617a4SPaul Burton #define PRID_COMP_INGENIC_E1	0xe10000	/* JZ4780 */
48384740dcSRalf Baechle 
49384740dcSRalf Baechle /*
508ff374b9SMaciej W. Rozycki  * Assigned Processor ID (implementation) values for bits 15:8 of the PRId
518ff374b9SMaciej W. Rozycki  * register.  In order to detect a certain CPU type exactly eventually
528ff374b9SMaciej W. Rozycki  * additional registers may need to be examined.
53384740dcSRalf Baechle  */
548ff374b9SMaciej W. Rozycki 
558ff374b9SMaciej W. Rozycki #define PRID_IMP_MASK		0xff00
568ff374b9SMaciej W. Rozycki 
578ff374b9SMaciej W. Rozycki /*
588ff374b9SMaciej W. Rozycki  * These are valid when 23:16 == PRID_COMP_LEGACY
598ff374b9SMaciej W. Rozycki  */
608ff374b9SMaciej W. Rozycki 
61384740dcSRalf Baechle #define PRID_IMP_R2000		0x0100
62384740dcSRalf Baechle #define PRID_IMP_AU1_REV1	0x0100
63384740dcSRalf Baechle #define PRID_IMP_AU1_REV2	0x0200
64384740dcSRalf Baechle #define PRID_IMP_R3000		0x0200		/* Same as R2000A  */
65384740dcSRalf Baechle #define PRID_IMP_R6000		0x0300		/* Same as R3000A  */
66384740dcSRalf Baechle #define PRID_IMP_R4000		0x0400
67384740dcSRalf Baechle #define PRID_IMP_R6000A		0x0600
68384740dcSRalf Baechle #define PRID_IMP_R10000		0x0900
69384740dcSRalf Baechle #define PRID_IMP_R4300		0x0b00
70384740dcSRalf Baechle #define PRID_IMP_VR41XX		0x0c00
71384740dcSRalf Baechle #define PRID_IMP_R12000		0x0e00
7230577391SJoshua Kinard #define PRID_IMP_R14000		0x0f00		/* R14K && R16K */
73384740dcSRalf Baechle #define PRID_IMP_R8000		0x1000
74384740dcSRalf Baechle #define PRID_IMP_PR4450		0x1200
75384740dcSRalf Baechle #define PRID_IMP_R4600		0x2000
76384740dcSRalf Baechle #define PRID_IMP_R4700		0x2100
77384740dcSRalf Baechle #define PRID_IMP_TX39		0x2200
78384740dcSRalf Baechle #define PRID_IMP_R4640		0x2200
79384740dcSRalf Baechle #define PRID_IMP_R4650		0x2200		/* Same as R4640 */
80384740dcSRalf Baechle #define PRID_IMP_R5000		0x2300
81384740dcSRalf Baechle #define PRID_IMP_TX49		0x2d00
82384740dcSRalf Baechle #define PRID_IMP_SONIC		0x2400
83384740dcSRalf Baechle #define PRID_IMP_MAGIC		0x2500
84384740dcSRalf Baechle #define PRID_IMP_RM7000		0x2700
85384740dcSRalf Baechle #define PRID_IMP_NEVADA		0x2800		/* RM5260 ??? */
86384740dcSRalf Baechle #define PRID_IMP_RM9000		0x3400
8726859198SHuacai Chen #define PRID_IMP_LOONGSON_32	0x4200  /* Loongson-1 */
88384740dcSRalf Baechle #define PRID_IMP_R5432		0x5400
89384740dcSRalf Baechle #define PRID_IMP_R5500		0x5500
9026859198SHuacai Chen #define PRID_IMP_LOONGSON_64	0x6300  /* Loongson-2/3 */
91384740dcSRalf Baechle 
92384740dcSRalf Baechle #define PRID_IMP_UNKNOWN	0xff00
93384740dcSRalf Baechle 
94384740dcSRalf Baechle /*
95384740dcSRalf Baechle  * These are the PRID's for when 23:16 == PRID_COMP_MIPS
96384740dcSRalf Baechle  */
97384740dcSRalf Baechle 
98aca5721eSLeonid Yegoshin #define PRID_IMP_QEMU_GENERIC	0x0000
99384740dcSRalf Baechle #define PRID_IMP_4KC		0x8000
100384740dcSRalf Baechle #define PRID_IMP_5KC		0x8100
101384740dcSRalf Baechle #define PRID_IMP_20KC		0x8200
102384740dcSRalf Baechle #define PRID_IMP_4KEC		0x8400
103384740dcSRalf Baechle #define PRID_IMP_4KSC		0x8600
104384740dcSRalf Baechle #define PRID_IMP_25KF		0x8800
105384740dcSRalf Baechle #define PRID_IMP_5KE		0x8900
106384740dcSRalf Baechle #define PRID_IMP_4KECR2		0x9000
107384740dcSRalf Baechle #define PRID_IMP_4KEMPR2	0x9100
108384740dcSRalf Baechle #define PRID_IMP_4KSD		0x9200
109384740dcSRalf Baechle #define PRID_IMP_24K		0x9300
110384740dcSRalf Baechle #define PRID_IMP_34K		0x9500
111384740dcSRalf Baechle #define PRID_IMP_24KE		0x9600
112384740dcSRalf Baechle #define PRID_IMP_74K		0x9700
113384740dcSRalf Baechle #define PRID_IMP_1004K		0x9900
114006a851bSSteven J. Hill #define PRID_IMP_1074K		0x9a00
115113c62d9SSteven J. Hill #define PRID_IMP_M14KC		0x9c00
116f8fa4811SSteven J. Hill #define PRID_IMP_M14KEC		0x9e00
1170ce7d58eSLeonid Yegoshin #define PRID_IMP_INTERAPTIV_UP	0xa000
1180ce7d58eSLeonid Yegoshin #define PRID_IMP_INTERAPTIV_MP	0xa100
11976f59e32SLeonid Yegoshin #define PRID_IMP_PROAPTIV_UP	0xa200
12076f59e32SLeonid Yegoshin #define PRID_IMP_PROAPTIV_MP	0xa300
1215cd0d5beSPaul Burton #define PRID_IMP_P6600		0xa400
1224975b86aSLeonid Yegoshin #define PRID_IMP_M5150		0xa700
123f43e4dfdSJames Hogan #define PRID_IMP_P5600		0xa800
12490b8baa2SMarkos Chandras #define PRID_IMP_I6400		0xa900
125df8b1a5eSPaul Burton #define PRID_IMP_M6250		0xab00
126384740dcSRalf Baechle 
127384740dcSRalf Baechle /*
128384740dcSRalf Baechle  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
129384740dcSRalf Baechle  */
130384740dcSRalf Baechle 
131384740dcSRalf Baechle #define PRID_IMP_SB1		0x0100
132384740dcSRalf Baechle #define PRID_IMP_SB1A		0x1100
133384740dcSRalf Baechle 
134384740dcSRalf Baechle /*
135384740dcSRalf Baechle  * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
136384740dcSRalf Baechle  */
137384740dcSRalf Baechle 
138384740dcSRalf Baechle #define PRID_IMP_SR71000	0x0400
139384740dcSRalf Baechle 
140384740dcSRalf Baechle /*
141384740dcSRalf Baechle  * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
142384740dcSRalf Baechle  */
143384740dcSRalf Baechle 
144190fca3eSKevin Cernekee #define PRID_IMP_BMIPS32_REV4	0x4000
145190fca3eSKevin Cernekee #define PRID_IMP_BMIPS32_REV8	0x8000
146602977b0SKevin Cernekee #define PRID_IMP_BMIPS3300	0x9000
147602977b0SKevin Cernekee #define PRID_IMP_BMIPS3300_ALT	0x9100
148602977b0SKevin Cernekee #define PRID_IMP_BMIPS3300_BUG	0x0000
149602977b0SKevin Cernekee #define PRID_IMP_BMIPS43XX	0xa000
150602977b0SKevin Cernekee #define PRID_IMP_BMIPS5000	0x5a00
15168e6a783SKevin Cernekee #define PRID_IMP_BMIPS5200	0x5b00
152602977b0SKevin Cernekee 
153602977b0SKevin Cernekee #define PRID_REV_BMIPS4380_LO	0x0040
154602977b0SKevin Cernekee #define PRID_REV_BMIPS4380_HI	0x006f
155384740dcSRalf Baechle 
156384740dcSRalf Baechle /*
1570dd4781bSDavid Daney  * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
1580dd4781bSDavid Daney  */
1590dd4781bSDavid Daney 
1600dd4781bSDavid Daney #define PRID_IMP_CAVIUM_CN38XX 0x0000
1610dd4781bSDavid Daney #define PRID_IMP_CAVIUM_CN31XX 0x0100
1620dd4781bSDavid Daney #define PRID_IMP_CAVIUM_CN30XX 0x0200
1630dd4781bSDavid Daney #define PRID_IMP_CAVIUM_CN58XX 0x0300
1640dd4781bSDavid Daney #define PRID_IMP_CAVIUM_CN56XX 0x0400
1650dd4781bSDavid Daney #define PRID_IMP_CAVIUM_CN50XX 0x0600
1660dd4781bSDavid Daney #define PRID_IMP_CAVIUM_CN52XX 0x0700
1671584d7f2SDavid Daney #define PRID_IMP_CAVIUM_CN63XX 0x9000
168074ef0d2SDavid Daney #define PRID_IMP_CAVIUM_CN68XX 0x9100
169074ef0d2SDavid Daney #define PRID_IMP_CAVIUM_CN66XX 0x9200
170074ef0d2SDavid Daney #define PRID_IMP_CAVIUM_CN61XX 0x9300
17171a8b7d8SDavid Daney #define PRID_IMP_CAVIUM_CNF71XX 0x9400
17271a8b7d8SDavid Daney #define PRID_IMP_CAVIUM_CN78XX 0x9500
17371a8b7d8SDavid Daney #define PRID_IMP_CAVIUM_CN70XX 0x9600
174b8c8f665SDavid Daney #define PRID_IMP_CAVIUM_CN73XX 0x9700
175b8c8f665SDavid Daney #define PRID_IMP_CAVIUM_CNF75XX 0x9800
1760dd4781bSDavid Daney 
1770dd4781bSDavid Daney /*
178252617a4SPaul Burton  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
17983ccf69dSLars-Peter Clausen  */
18083ccf69dSLars-Peter Clausen 
18183ccf69dSLars-Peter Clausen #define PRID_IMP_JZRISC	       0x0200
18283ccf69dSLars-Peter Clausen 
18383ccf69dSLars-Peter Clausen /*
184a7117c6bSJayachandran C  * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
185a7117c6bSJayachandran C  */
186a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLR732	0x0000
187a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLR716	0x0200
188a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLR532	0x0900
189a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLR308	0x0600
190a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLR532C	0x0800
191a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLR516C	0x0a00
192a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLR508C	0x0b00
193a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLR308C	0x0f00
194a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS608	0x8000
195a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS408	0x8800
196a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS404	0x8c00
197a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS208	0x8e00
198a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS204	0x8f00
199a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS108	0xce00
200a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS104	0xcf00
201a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS616B	0x4000
202a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS608B	0x4a00
203a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS416B	0x4400
204a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS412B	0x4c00
205a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS408B	0x4e00
206a7117c6bSJayachandran C #define PRID_IMP_NETLOGIC_XLS404B	0x4f00
207809f36c6SManuel Lauss #define PRID_IMP_NETLOGIC_AU13XX	0x8000
208a7117c6bSJayachandran C 
2092aa54b20SJayachandran C #define PRID_IMP_NETLOGIC_XLP8XX	0x1000
2102aa54b20SJayachandran C #define PRID_IMP_NETLOGIC_XLP3XX	0x1100
2114ca86a2fSJayachandran C #define PRID_IMP_NETLOGIC_XLP2XX	0x1200
2128907c55eSJayachandran C #define PRID_IMP_NETLOGIC_XLP9XX	0x1500
2131c983986SYonghong Song #define PRID_IMP_NETLOGIC_XLP5XX	0x1300
214a7117c6bSJayachandran C 
215a7117c6bSJayachandran C /*
2168ff374b9SMaciej W. Rozycki  * Particular Revision values for bits 7:0 of the PRId register.
217384740dcSRalf Baechle  */
218384740dcSRalf Baechle 
219384740dcSRalf Baechle #define PRID_REV_MASK		0x00ff
220384740dcSRalf Baechle 
2218ff374b9SMaciej W. Rozycki /*
2228ff374b9SMaciej W. Rozycki  * Definitions for 7:0 on legacy processors
2238ff374b9SMaciej W. Rozycki  */
2248ff374b9SMaciej W. Rozycki 
225384740dcSRalf Baechle #define PRID_REV_TX4927		0x0022
226384740dcSRalf Baechle #define PRID_REV_TX4937		0x0030
227384740dcSRalf Baechle #define PRID_REV_R4400		0x0040
228384740dcSRalf Baechle #define PRID_REV_R3000A		0x0030
229384740dcSRalf Baechle #define PRID_REV_R3000		0x0020
230384740dcSRalf Baechle #define PRID_REV_R2000A		0x0010
231384740dcSRalf Baechle #define PRID_REV_TX3912		0x0010
232384740dcSRalf Baechle #define PRID_REV_TX3922		0x0030
233384740dcSRalf Baechle #define PRID_REV_TX3927		0x0040
234384740dcSRalf Baechle #define PRID_REV_VR4111		0x0050
235384740dcSRalf Baechle #define PRID_REV_VR4181		0x0050	/* Same as VR4111 */
236384740dcSRalf Baechle #define PRID_REV_VR4121		0x0060
237384740dcSRalf Baechle #define PRID_REV_VR4122		0x0070
238384740dcSRalf Baechle #define PRID_REV_VR4181A	0x0070	/* Same as VR4122 */
239384740dcSRalf Baechle #define PRID_REV_VR4130		0x0080
240384740dcSRalf Baechle #define PRID_REV_34K_V1_0_2	0x0022
2412fa36399SKelvin Cheung #define PRID_REV_LOONGSON1B	0x0020
242f8ede0f7SWu Zhangjin #define PRID_REV_LOONGSON2E	0x0002
243f8ede0f7SWu Zhangjin #define PRID_REV_LOONGSON2F	0x0003
244152ebb44SHuacai Chen #define PRID_REV_LOONGSON3A	0x0005
245e7841be5SHuacai Chen #define PRID_REV_LOONGSON3B_R1	0x0006
246e7841be5SHuacai Chen #define PRID_REV_LOONGSON3B_R2	0x0007
247384740dcSRalf Baechle 
248384740dcSRalf Baechle /*
249384740dcSRalf Baechle  * Older processors used to encode processor version and revision in two
250384740dcSRalf Baechle  * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
251384740dcSRalf Baechle  * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
252384740dcSRalf Baechle  * the patch number.  *ARGH*
253384740dcSRalf Baechle  */
254384740dcSRalf Baechle #define PRID_REV_ENCODE_44(ver, rev)					\
255384740dcSRalf Baechle 	((ver) << 4 | (rev))
256384740dcSRalf Baechle #define PRID_REV_ENCODE_332(ver, rev, patch)				\
257384740dcSRalf Baechle 	((ver) << 5 | (rev) << 2 | (patch))
258384740dcSRalf Baechle 
259384740dcSRalf Baechle /*
260384740dcSRalf Baechle  * FPU implementation/revision register (CP1 control register 0).
261384740dcSRalf Baechle  *
262384740dcSRalf Baechle  * +---------------------------------+----------------+----------------+
263384740dcSRalf Baechle  * | 0				     | Implementation | Revision       |
264384740dcSRalf Baechle  * +---------------------------------+----------------+----------------+
265384740dcSRalf Baechle  *  31				   16 15	     8 7	      0
266384740dcSRalf Baechle  */
267384740dcSRalf Baechle 
2688ff374b9SMaciej W. Rozycki #define FPIR_IMP_MASK		0xff00
2698ff374b9SMaciej W. Rozycki 
270384740dcSRalf Baechle #define FPIR_IMP_NONE		0x0000
271384740dcSRalf Baechle 
27268248d0cSJonas Gorski #if !defined(__ASSEMBLY__)
27368248d0cSJonas Gorski 
274384740dcSRalf Baechle enum cpu_type_enum {
275384740dcSRalf Baechle 	CPU_UNKNOWN,
276384740dcSRalf Baechle 
277384740dcSRalf Baechle 	/*
278384740dcSRalf Baechle 	 * R2000 class processors
279384740dcSRalf Baechle 	 */
280384740dcSRalf Baechle 	CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
281384740dcSRalf Baechle 	CPU_R3081, CPU_R3081E,
282384740dcSRalf Baechle 
283384740dcSRalf Baechle 	/*
284384740dcSRalf Baechle 	 * R6000 class processors
285384740dcSRalf Baechle 	 */
286384740dcSRalf Baechle 	CPU_R6000, CPU_R6000A,
287384740dcSRalf Baechle 
288384740dcSRalf Baechle 	/*
289384740dcSRalf Baechle 	 * R4000 class processors
290384740dcSRalf Baechle 	 */
291384740dcSRalf Baechle 	CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
292384740dcSRalf Baechle 	CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
293fb2b1dbaSRalf Baechle 	CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
29430577391SJoshua Kinard 	CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
29530577391SJoshua Kinard 	CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
296321b1863SRalf Baechle 	CPU_SR71000, CPU_TX49XX,
297384740dcSRalf Baechle 
298384740dcSRalf Baechle 	/*
299384740dcSRalf Baechle 	 * R8000 class processors
300384740dcSRalf Baechle 	 */
301384740dcSRalf Baechle 	CPU_R8000,
302384740dcSRalf Baechle 
303384740dcSRalf Baechle 	/*
304384740dcSRalf Baechle 	 * TX3900 class processors
305384740dcSRalf Baechle 	 */
306384740dcSRalf Baechle 	CPU_TX3912, CPU_TX3922, CPU_TX3927,
307384740dcSRalf Baechle 
308384740dcSRalf Baechle 	/*
309384740dcSRalf Baechle 	 * MIPS32 class processors
310384740dcSRalf Baechle 	 */
311384740dcSRalf Baechle 	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
312602977b0SKevin Cernekee 	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
3132fa36399SKelvin Cheung 	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
314bff3d472SRalf Baechle 	CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,
315df8b1a5eSPaul Burton 	CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250,
316384740dcSRalf Baechle 
317384740dcSRalf Baechle 	/*
318384740dcSRalf Baechle 	 * MIPS64 class processors
319384740dcSRalf Baechle 	 */
32078d4803fSLeonid Yegoshin 	CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
321152ebb44SHuacai Chen 	CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
322152ebb44SHuacai Chen 	CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
323384740dcSRalf Baechle 
324aca5721eSLeonid Yegoshin 	CPU_QEMU_GENERIC,
325aca5721eSLeonid Yegoshin 
326384740dcSRalf Baechle 	CPU_LAST
327384740dcSRalf Baechle };
328384740dcSRalf Baechle 
32968248d0cSJonas Gorski #endif /* !__ASSEMBLY */
330384740dcSRalf Baechle 
331384740dcSRalf Baechle /*
332384740dcSRalf Baechle  * ISA Level encodings
333384740dcSRalf Baechle  *
334384740dcSRalf Baechle  */
3351990e542SRalf Baechle #define MIPS_CPU_ISA_II		0x00000001
3361990e542SRalf Baechle #define MIPS_CPU_ISA_III	0x00000002
3371990e542SRalf Baechle #define MIPS_CPU_ISA_IV		0x00000004
3381990e542SRalf Baechle #define MIPS_CPU_ISA_V		0x00000008
3391990e542SRalf Baechle #define MIPS_CPU_ISA_M32R1	0x00000010
3401990e542SRalf Baechle #define MIPS_CPU_ISA_M32R2	0x00000020
3411990e542SRalf Baechle #define MIPS_CPU_ISA_M64R1	0x00000040
3421990e542SRalf Baechle #define MIPS_CPU_ISA_M64R2	0x00000080
34334c56fc1SLeonid Yegoshin #define MIPS_CPU_ISA_M32R6	0x00000100
34434c56fc1SLeonid Yegoshin #define MIPS_CPU_ISA_M64R6	0x00000200
345384740dcSRalf Baechle 
3461990e542SRalf Baechle #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
34734c56fc1SLeonid Yegoshin 	MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6)
348384740dcSRalf Baechle #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
34934c56fc1SLeonid Yegoshin 	MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \
35034c56fc1SLeonid Yegoshin 	MIPS_CPU_ISA_M64R6)
351384740dcSRalf Baechle 
352384740dcSRalf Baechle /*
353*0c94fa33SJames Hogan  * Private version of BIT_ULL() to escape include file recursion hell.
354*0c94fa33SJames Hogan  * We soon will have to switch to another mechanism that will work with
355*0c94fa33SJames Hogan  * more than 64 bits anyway.
356*0c94fa33SJames Hogan  */
357*0c94fa33SJames Hogan #define MBIT_ULL(bit)		(1ULL << (bit))
358*0c94fa33SJames Hogan 
359*0c94fa33SJames Hogan /*
360384740dcSRalf Baechle  * CPU Option encodings
361384740dcSRalf Baechle  */
362*0c94fa33SJames Hogan #define MIPS_CPU_TLB		MBIT_ULL( 0)	/* CPU has TLB */
363*0c94fa33SJames Hogan #define MIPS_CPU_4KEX		MBIT_ULL( 1)	/* "R4K" exception model */
364*0c94fa33SJames Hogan #define MIPS_CPU_3K_CACHE	MBIT_ULL( 2)	/* R3000-style caches */
365*0c94fa33SJames Hogan #define MIPS_CPU_4K_CACHE	MBIT_ULL( 3)	/* R4000-style caches */
366*0c94fa33SJames Hogan #define MIPS_CPU_TX39_CACHE	MBIT_ULL( 4)	/* TX3900-style caches */
367*0c94fa33SJames Hogan #define MIPS_CPU_FPU		MBIT_ULL( 5)	/* CPU has FPU */
368*0c94fa33SJames Hogan #define MIPS_CPU_32FPR		MBIT_ULL( 6)	/* 32 dbl. prec. FP registers */
369*0c94fa33SJames Hogan #define MIPS_CPU_COUNTER	MBIT_ULL( 7)	/* Cycle count/compare */
370*0c94fa33SJames Hogan #define MIPS_CPU_WATCH		MBIT_ULL( 8)	/* watchpoint registers */
371*0c94fa33SJames Hogan #define MIPS_CPU_DIVEC		MBIT_ULL( 9)	/* dedicated interrupt vector */
372*0c94fa33SJames Hogan #define MIPS_CPU_VCE		MBIT_ULL(10)	/* virt. coherence conflict possible */
373*0c94fa33SJames Hogan #define MIPS_CPU_CACHE_CDEX_P	MBIT_ULL(11)	/* Create_Dirty_Exclusive CACHE op */
374*0c94fa33SJames Hogan #define MIPS_CPU_CACHE_CDEX_S	MBIT_ULL(12)	/* ... same for seconary cache ... */
375*0c94fa33SJames Hogan #define MIPS_CPU_MCHECK		MBIT_ULL(13)	/* Machine check exception */
376*0c94fa33SJames Hogan #define MIPS_CPU_EJTAG		MBIT_ULL(14)	/* EJTAG exception */
377*0c94fa33SJames Hogan #define MIPS_CPU_NOFPUEX	MBIT_ULL(15)	/* no FPU exception */
378*0c94fa33SJames Hogan #define MIPS_CPU_LLSC		MBIT_ULL(16)	/* CPU has ll/sc instructions */
379*0c94fa33SJames Hogan #define MIPS_CPU_INCLUSIVE_CACHES	MBIT_ULL(17)	/* P-cache subset enforced */
380*0c94fa33SJames Hogan #define MIPS_CPU_PREFETCH	MBIT_ULL(18)	/* CPU has usable prefetch */
381*0c94fa33SJames Hogan #define MIPS_CPU_VINT		MBIT_ULL(19)	/* CPU supports MIPSR2 vectored interrupts */
382*0c94fa33SJames Hogan #define MIPS_CPU_VEIC		MBIT_ULL(20)	/* CPU supports MIPSR2 external interrupt controller mode */
383*0c94fa33SJames Hogan #define MIPS_CPU_ULRI		MBIT_ULL(21)	/* CPU has ULRI feature */
384*0c94fa33SJames Hogan #define MIPS_CPU_PCI		MBIT_ULL(22)	/* CPU has Perf Ctr Int indicator */
385*0c94fa33SJames Hogan #define MIPS_CPU_RIXI		MBIT_ULL(23)	/* CPU has TLB Read/eXec Inhibit */
386*0c94fa33SJames Hogan #define MIPS_CPU_MICROMIPS	MBIT_ULL(24)	/* CPU has microMIPS capability */
387*0c94fa33SJames Hogan #define MIPS_CPU_TLBINV		MBIT_ULL(25)	/* CPU supports TLBINV/F */
388*0c94fa33SJames Hogan #define MIPS_CPU_SEGMENTS	MBIT_ULL(26)	/* CPU supports Segmentation Control registers */
389*0c94fa33SJames Hogan #define MIPS_CPU_EVA		MBIT_ULL(27)	/* CPU supports Enhanced Virtual Addressing */
390*0c94fa33SJames Hogan #define MIPS_CPU_HTW		MBIT_ULL(28)	/* CPU support Hardware Page Table Walker */
391*0c94fa33SJames Hogan #define MIPS_CPU_RIXIEX		MBIT_ULL(29)	/* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
392*0c94fa33SJames Hogan #define MIPS_CPU_MAAR		MBIT_ULL(30)	/* MAAR(I) registers are present */
393*0c94fa33SJames Hogan #define MIPS_CPU_FRE		MBIT_ULL(31)	/* FRE & UFE bits implemented */
394*0c94fa33SJames Hogan #define MIPS_CPU_RW_LLB		MBIT_ULL(32)	/* LLADDR/LLB writes are allowed */
395*0c94fa33SJames Hogan #define MIPS_CPU_XPA		MBIT_ULL(33)	/* CPU supports Extended Physical Addressing */
396*0c94fa33SJames Hogan #define MIPS_CPU_CDMM		MBIT_ULL(34)	/* CPU has Common Device Memory Map */
397*0c94fa33SJames Hogan #define MIPS_CPU_BP_GHIST	MBIT_ULL(35)	/* R12K+ Branch Prediction Global History */
398*0c94fa33SJames Hogan #define MIPS_CPU_SP		MBIT_ULL(36)	/* Small (1KB) page support */
399*0c94fa33SJames Hogan #define MIPS_CPU_FTLB		MBIT_ULL(37)	/* CPU has Fixed-page-size TLB */
400*0c94fa33SJames Hogan #define MIPS_CPU_NAN_LEGACY	MBIT_ULL(38)	/* Legacy NaN implemented */
401*0c94fa33SJames Hogan #define MIPS_CPU_NAN_2008	MBIT_ULL(39)	/* 2008 NaN implemented */
402*0c94fa33SJames Hogan #define MIPS_CPU_VP		MBIT_ULL(40)	/* MIPSr6 Virtual Processors (multi-threading) */
403384740dcSRalf Baechle 
404384740dcSRalf Baechle /*
405384740dcSRalf Baechle  * CPU ASE encodings
406384740dcSRalf Baechle  */
407384740dcSRalf Baechle #define MIPS_ASE_MIPS16		0x00000001 /* code compression */
408384740dcSRalf Baechle #define MIPS_ASE_MDMX		0x00000002 /* MIPS digital media extension */
409384740dcSRalf Baechle #define MIPS_ASE_MIPS3D		0x00000004 /* MIPS-3D */
410384740dcSRalf Baechle #define MIPS_ASE_SMARTMIPS	0x00000008 /* SmartMIPS */
411384740dcSRalf Baechle #define MIPS_ASE_DSP		0x00000010 /* Signal Processing ASE */
412384740dcSRalf Baechle #define MIPS_ASE_MIPSMT		0x00000020 /* CPU supports MIPS MT */
413ee80f7c7SSteven J. Hill #define MIPS_ASE_DSP2P		0x00000040 /* Signal Processing ASE Rev 2 */
4141e7decdbSDavid Daney #define MIPS_ASE_VZ		0x00000080 /* Virtualization ASE */
415a5e9a69eSPaul Burton #define MIPS_ASE_MSA		0x00000100 /* MIPS SIMD Architecture */
416384740dcSRalf Baechle 
417384740dcSRalf Baechle #endif /* _ASM_CPU_H */
418