xref: /openbmc/linux/arch/mips/include/asm/compiler.h (revision cdd38c5f1ce4398ec58fec95904b75824daab7b5)
1384740dcSRalf Baechle /*
2384740dcSRalf Baechle  * Copyright (C) 2004, 2007  Maciej W. Rozycki
3384740dcSRalf Baechle  *
4384740dcSRalf Baechle  * This file is subject to the terms and conditions of the GNU General Public
5384740dcSRalf Baechle  * License.  See the file "COPYING" in the main directory of this archive
6384740dcSRalf Baechle  * for more details.
7384740dcSRalf Baechle  */
8384740dcSRalf Baechle #ifndef _ASM_COMPILER_H
9384740dcSRalf Baechle #define _ASM_COMPILER_H
10384740dcSRalf Baechle 
11906d441fSPaul Burton /*
12906d441fSPaul Burton  * With GCC 4.5 onwards we can use __builtin_unreachable to indicate to the
13906d441fSPaul Burton  * compiler that a particular code path will never be hit. This allows it to be
14906d441fSPaul Burton  * optimised out of the generated binary.
15906d441fSPaul Burton  *
16906d441fSPaul Burton  * Unfortunately at least GCC 4.6.3 through 7.3.0 inclusive suffer from a bug
17906d441fSPaul Burton  * that can lead to instructions from beyond an unreachable statement being
18906d441fSPaul Burton  * incorrectly reordered into earlier delay slots if the unreachable statement
19906d441fSPaul Burton  * is the only content of a case in a switch statement. This can lead to
20906d441fSPaul Burton  * seemingly random behaviour, such as invalid memory accesses from incorrectly
21906d441fSPaul Burton  * reordered loads or stores. See this potential GCC fix for details:
22906d441fSPaul Burton  *
23906d441fSPaul Burton  *   https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00360.html
24906d441fSPaul Burton  *
25906d441fSPaul Burton  * It is unclear whether GCC 8 onwards suffer from the same issue - nothing
26906d441fSPaul Burton  * relevant is mentioned in GCC 8 release notes and nothing obviously relevant
27906d441fSPaul Burton  * stands out in GCC commit logs, but these newer GCC versions generate very
28906d441fSPaul Burton  * different code for the testcase which doesn't exhibit the bug.
29906d441fSPaul Burton  *
30906d441fSPaul Burton  * GCC also handles stack allocation suboptimally when calling noreturn
31906d441fSPaul Burton  * functions or calling __builtin_unreachable():
32906d441fSPaul Burton  *
33906d441fSPaul Burton  *   https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82365
34906d441fSPaul Burton  *
35906d441fSPaul Burton  * We work around both of these issues by placing a volatile asm statement,
36906d441fSPaul Burton  * which GCC is prevented from reordering past, prior to __builtin_unreachable
37906d441fSPaul Burton  * calls.
38906d441fSPaul Burton  *
39906d441fSPaul Burton  * The .insn statement is required to ensure that any branches to the
40906d441fSPaul Burton  * statement, which sadly must be kept due to the asm statement, are known to
41906d441fSPaul Burton  * be branches to code and satisfy linker requirements for microMIPS kernels.
42906d441fSPaul Burton  */
43906d441fSPaul Burton #undef barrier_before_unreachable
44906d441fSPaul Burton #define barrier_before_unreachable() asm volatile(".insn")
45906d441fSPaul Burton 
46123e4b3bSMarkos Chandras #define GCC_OFF_SMALL_ASM() "ZC"
47b0984c43SMaciej W. Rozycki 
48be513698SMarkos Chandras #ifdef CONFIG_CPU_MIPSR6
49be513698SMarkos Chandras #define MIPS_ISA_LEVEL "mips64r6"
50be513698SMarkos Chandras #define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
51be513698SMarkos Chandras #define MIPS_ISA_LEVEL_RAW mips64r6
52be513698SMarkos Chandras #define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
53*ab7c01fdSSerge Semin #elif defined(CONFIG_CPU_MIPSR5)
54*ab7c01fdSSerge Semin #define MIPS_ISA_LEVEL "mips64r5"
55*ab7c01fdSSerge Semin #define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
56*ab7c01fdSSerge Semin #define MIPS_ISA_LEVEL_RAW mips64r5
57*ab7c01fdSSerge Semin #define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
58be513698SMarkos Chandras #else
59be513698SMarkos Chandras /* MIPS64 is a superset of MIPS32 */
60be513698SMarkos Chandras #define MIPS_ISA_LEVEL "mips64r2"
61be513698SMarkos Chandras #define MIPS_ISA_ARCH_LEVEL "arch=r4000"
62be513698SMarkos Chandras #define MIPS_ISA_LEVEL_RAW mips64r2
63be513698SMarkos Chandras #define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
64be513698SMarkos Chandras #endif /* CONFIG_CPU_MIPSR6 */
65be513698SMarkos Chandras 
66384740dcSRalf Baechle #endif /* _ASM_COMPILER_H */
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