1e7300d04SMaxime Bizon /* 2e7300d04SMaxime Bizon * This file is subject to the terms and conditions of the GNU General Public 3e7300d04SMaxime Bizon * License. See the file "COPYING" in the main directory of this archive 4e7300d04SMaxime Bizon * for more details. 5e7300d04SMaxime Bizon * 6e7300d04SMaxime Bizon * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 7e7300d04SMaxime Bizon */ 8e7300d04SMaxime Bizon 9e7300d04SMaxime Bizon #include <linux/module.h> 10e7300d04SMaxime Bizon #include <linux/mutex.h> 11e7300d04SMaxime Bizon #include <linux/err.h> 12e7300d04SMaxime Bizon #include <linux/clk.h> 13*04712f3fSMaxime Bizon #include <linux/delay.h> 14e7300d04SMaxime Bizon #include <bcm63xx_cpu.h> 15e7300d04SMaxime Bizon #include <bcm63xx_io.h> 16e7300d04SMaxime Bizon #include <bcm63xx_regs.h> 17e7300d04SMaxime Bizon #include <bcm63xx_clk.h> 18e7300d04SMaxime Bizon 19e7300d04SMaxime Bizon static DEFINE_MUTEX(clocks_mutex); 20e7300d04SMaxime Bizon 21e7300d04SMaxime Bizon 22e7300d04SMaxime Bizon static void clk_enable_unlocked(struct clk *clk) 23e7300d04SMaxime Bizon { 24e7300d04SMaxime Bizon if (clk->set && (clk->usage++) == 0) 25e7300d04SMaxime Bizon clk->set(clk, 1); 26e7300d04SMaxime Bizon } 27e7300d04SMaxime Bizon 28e7300d04SMaxime Bizon static void clk_disable_unlocked(struct clk *clk) 29e7300d04SMaxime Bizon { 30e7300d04SMaxime Bizon if (clk->set && (--clk->usage) == 0) 31e7300d04SMaxime Bizon clk->set(clk, 0); 32e7300d04SMaxime Bizon } 33e7300d04SMaxime Bizon 34e7300d04SMaxime Bizon static void bcm_hwclock_set(u32 mask, int enable) 35e7300d04SMaxime Bizon { 36e7300d04SMaxime Bizon u32 reg; 37e7300d04SMaxime Bizon 38e7300d04SMaxime Bizon reg = bcm_perf_readl(PERF_CKCTL_REG); 39e7300d04SMaxime Bizon if (enable) 40e7300d04SMaxime Bizon reg |= mask; 41e7300d04SMaxime Bizon else 42e7300d04SMaxime Bizon reg &= ~mask; 43e7300d04SMaxime Bizon bcm_perf_writel(reg, PERF_CKCTL_REG); 44e7300d04SMaxime Bizon } 45e7300d04SMaxime Bizon 46e7300d04SMaxime Bizon /* 47e7300d04SMaxime Bizon * Ethernet MAC "misc" clock: dma clocks and main clock on 6348 48e7300d04SMaxime Bizon */ 49e7300d04SMaxime Bizon static void enet_misc_set(struct clk *clk, int enable) 50e7300d04SMaxime Bizon { 51e7300d04SMaxime Bizon u32 mask; 52e7300d04SMaxime Bizon 53e7300d04SMaxime Bizon if (BCMCPU_IS_6338()) 54e7300d04SMaxime Bizon mask = CKCTL_6338_ENET_EN; 55e7300d04SMaxime Bizon else if (BCMCPU_IS_6345()) 56e7300d04SMaxime Bizon mask = CKCTL_6345_ENET_EN; 57e7300d04SMaxime Bizon else if (BCMCPU_IS_6348()) 58e7300d04SMaxime Bizon mask = CKCTL_6348_ENET_EN; 59e7300d04SMaxime Bizon else 60e7300d04SMaxime Bizon /* BCMCPU_IS_6358 */ 61e7300d04SMaxime Bizon mask = CKCTL_6358_EMUSB_EN; 62e7300d04SMaxime Bizon bcm_hwclock_set(mask, enable); 63e7300d04SMaxime Bizon } 64e7300d04SMaxime Bizon 65e7300d04SMaxime Bizon static struct clk clk_enet_misc = { 66e7300d04SMaxime Bizon .set = enet_misc_set, 67e7300d04SMaxime Bizon }; 68e7300d04SMaxime Bizon 69e7300d04SMaxime Bizon /* 70e7300d04SMaxime Bizon * Ethernet MAC clocks: only revelant on 6358, silently enable misc 71e7300d04SMaxime Bizon * clocks 72e7300d04SMaxime Bizon */ 73e7300d04SMaxime Bizon static void enetx_set(struct clk *clk, int enable) 74e7300d04SMaxime Bizon { 75e7300d04SMaxime Bizon if (enable) 76e7300d04SMaxime Bizon clk_enable_unlocked(&clk_enet_misc); 77e7300d04SMaxime Bizon else 78e7300d04SMaxime Bizon clk_disable_unlocked(&clk_enet_misc); 79e7300d04SMaxime Bizon 80e7300d04SMaxime Bizon if (BCMCPU_IS_6358()) { 81e7300d04SMaxime Bizon u32 mask; 82e7300d04SMaxime Bizon 83e7300d04SMaxime Bizon if (clk->id == 0) 84e7300d04SMaxime Bizon mask = CKCTL_6358_ENET0_EN; 85e7300d04SMaxime Bizon else 86e7300d04SMaxime Bizon mask = CKCTL_6358_ENET1_EN; 87e7300d04SMaxime Bizon bcm_hwclock_set(mask, enable); 88e7300d04SMaxime Bizon } 89e7300d04SMaxime Bizon } 90e7300d04SMaxime Bizon 91e7300d04SMaxime Bizon static struct clk clk_enet0 = { 92e7300d04SMaxime Bizon .id = 0, 93e7300d04SMaxime Bizon .set = enetx_set, 94e7300d04SMaxime Bizon }; 95e7300d04SMaxime Bizon 96e7300d04SMaxime Bizon static struct clk clk_enet1 = { 97e7300d04SMaxime Bizon .id = 1, 98e7300d04SMaxime Bizon .set = enetx_set, 99e7300d04SMaxime Bizon }; 100e7300d04SMaxime Bizon 101e7300d04SMaxime Bizon /* 102e7300d04SMaxime Bizon * Ethernet PHY clock 103e7300d04SMaxime Bizon */ 104e7300d04SMaxime Bizon static void ephy_set(struct clk *clk, int enable) 105e7300d04SMaxime Bizon { 106e7300d04SMaxime Bizon if (!BCMCPU_IS_6358()) 107e7300d04SMaxime Bizon return; 108e7300d04SMaxime Bizon bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable); 109e7300d04SMaxime Bizon } 110e7300d04SMaxime Bizon 111e7300d04SMaxime Bizon 112e7300d04SMaxime Bizon static struct clk clk_ephy = { 113e7300d04SMaxime Bizon .set = ephy_set, 114e7300d04SMaxime Bizon }; 115e7300d04SMaxime Bizon 116e7300d04SMaxime Bizon /* 117*04712f3fSMaxime Bizon * Ethernet switch clock 118*04712f3fSMaxime Bizon */ 119*04712f3fSMaxime Bizon static void enetsw_set(struct clk *clk, int enable) 120*04712f3fSMaxime Bizon { 121*04712f3fSMaxime Bizon if (!BCMCPU_IS_6368()) 122*04712f3fSMaxime Bizon return; 123*04712f3fSMaxime Bizon bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN | 124*04712f3fSMaxime Bizon CKCTL_6368_SWPKT_USB_EN | 125*04712f3fSMaxime Bizon CKCTL_6368_SWPKT_SAR_EN, enable); 126*04712f3fSMaxime Bizon if (enable) { 127*04712f3fSMaxime Bizon u32 val; 128*04712f3fSMaxime Bizon 129*04712f3fSMaxime Bizon /* reset switch core afer clock change */ 130*04712f3fSMaxime Bizon val = bcm_perf_readl(PERF_SOFTRESET_6368_REG); 131*04712f3fSMaxime Bizon val &= ~SOFTRESET_6368_ENETSW_MASK; 132*04712f3fSMaxime Bizon bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); 133*04712f3fSMaxime Bizon msleep(10); 134*04712f3fSMaxime Bizon val |= SOFTRESET_6368_ENETSW_MASK; 135*04712f3fSMaxime Bizon bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); 136*04712f3fSMaxime Bizon msleep(10); 137*04712f3fSMaxime Bizon } 138*04712f3fSMaxime Bizon } 139*04712f3fSMaxime Bizon 140*04712f3fSMaxime Bizon static struct clk clk_enetsw = { 141*04712f3fSMaxime Bizon .set = enetsw_set, 142*04712f3fSMaxime Bizon }; 143*04712f3fSMaxime Bizon 144*04712f3fSMaxime Bizon /* 145e7300d04SMaxime Bizon * PCM clock 146e7300d04SMaxime Bizon */ 147e7300d04SMaxime Bizon static void pcm_set(struct clk *clk, int enable) 148e7300d04SMaxime Bizon { 149e7300d04SMaxime Bizon if (!BCMCPU_IS_6358()) 150e7300d04SMaxime Bizon return; 151e7300d04SMaxime Bizon bcm_hwclock_set(CKCTL_6358_PCM_EN, enable); 152e7300d04SMaxime Bizon } 153e7300d04SMaxime Bizon 154e7300d04SMaxime Bizon static struct clk clk_pcm = { 155e7300d04SMaxime Bizon .set = pcm_set, 156e7300d04SMaxime Bizon }; 157e7300d04SMaxime Bizon 158e7300d04SMaxime Bizon /* 159e7300d04SMaxime Bizon * USB host clock 160e7300d04SMaxime Bizon */ 161e7300d04SMaxime Bizon static void usbh_set(struct clk *clk, int enable) 162e7300d04SMaxime Bizon { 163*04712f3fSMaxime Bizon if (BCMCPU_IS_6348()) 164e7300d04SMaxime Bizon bcm_hwclock_set(CKCTL_6348_USBH_EN, enable); 165*04712f3fSMaxime Bizon else if (BCMCPU_IS_6368()) 166*04712f3fSMaxime Bizon bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable); 167e7300d04SMaxime Bizon } 168e7300d04SMaxime Bizon 169e7300d04SMaxime Bizon static struct clk clk_usbh = { 170e7300d04SMaxime Bizon .set = usbh_set, 171e7300d04SMaxime Bizon }; 172e7300d04SMaxime Bizon 173e7300d04SMaxime Bizon /* 174e7300d04SMaxime Bizon * SPI clock 175e7300d04SMaxime Bizon */ 176e7300d04SMaxime Bizon static void spi_set(struct clk *clk, int enable) 177e7300d04SMaxime Bizon { 178e7300d04SMaxime Bizon u32 mask; 179e7300d04SMaxime Bizon 180e7300d04SMaxime Bizon if (BCMCPU_IS_6338()) 181e7300d04SMaxime Bizon mask = CKCTL_6338_SPI_EN; 182e7300d04SMaxime Bizon else if (BCMCPU_IS_6348()) 183e7300d04SMaxime Bizon mask = CKCTL_6348_SPI_EN; 184e7300d04SMaxime Bizon else 185e7300d04SMaxime Bizon /* BCMCPU_IS_6358 */ 186e7300d04SMaxime Bizon mask = CKCTL_6358_SPI_EN; 187e7300d04SMaxime Bizon bcm_hwclock_set(mask, enable); 188e7300d04SMaxime Bizon } 189e7300d04SMaxime Bizon 190e7300d04SMaxime Bizon static struct clk clk_spi = { 191e7300d04SMaxime Bizon .set = spi_set, 192e7300d04SMaxime Bizon }; 193e7300d04SMaxime Bizon 194e7300d04SMaxime Bizon /* 195*04712f3fSMaxime Bizon * XTM clock 196*04712f3fSMaxime Bizon */ 197*04712f3fSMaxime Bizon static void xtm_set(struct clk *clk, int enable) 198*04712f3fSMaxime Bizon { 199*04712f3fSMaxime Bizon if (!BCMCPU_IS_6368()) 200*04712f3fSMaxime Bizon return; 201*04712f3fSMaxime Bizon 202*04712f3fSMaxime Bizon bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN | 203*04712f3fSMaxime Bizon CKCTL_6368_SWPKT_SAR_EN, enable); 204*04712f3fSMaxime Bizon 205*04712f3fSMaxime Bizon if (enable) { 206*04712f3fSMaxime Bizon u32 val; 207*04712f3fSMaxime Bizon 208*04712f3fSMaxime Bizon /* reset sar core afer clock change */ 209*04712f3fSMaxime Bizon val = bcm_perf_readl(PERF_SOFTRESET_6368_REG); 210*04712f3fSMaxime Bizon val &= ~SOFTRESET_6368_SAR_MASK; 211*04712f3fSMaxime Bizon bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); 212*04712f3fSMaxime Bizon mdelay(1); 213*04712f3fSMaxime Bizon val |= SOFTRESET_6368_SAR_MASK; 214*04712f3fSMaxime Bizon bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); 215*04712f3fSMaxime Bizon mdelay(1); 216*04712f3fSMaxime Bizon } 217*04712f3fSMaxime Bizon } 218*04712f3fSMaxime Bizon 219*04712f3fSMaxime Bizon 220*04712f3fSMaxime Bizon static struct clk clk_xtm = { 221*04712f3fSMaxime Bizon .set = xtm_set, 222*04712f3fSMaxime Bizon }; 223*04712f3fSMaxime Bizon 224*04712f3fSMaxime Bizon /* 225e7300d04SMaxime Bizon * Internal peripheral clock 226e7300d04SMaxime Bizon */ 227e7300d04SMaxime Bizon static struct clk clk_periph = { 228e7300d04SMaxime Bizon .rate = (50 * 1000 * 1000), 229e7300d04SMaxime Bizon }; 230e7300d04SMaxime Bizon 231e7300d04SMaxime Bizon 232e7300d04SMaxime Bizon /* 233e7300d04SMaxime Bizon * Linux clock API implementation 234e7300d04SMaxime Bizon */ 235e7300d04SMaxime Bizon int clk_enable(struct clk *clk) 236e7300d04SMaxime Bizon { 237e7300d04SMaxime Bizon mutex_lock(&clocks_mutex); 238e7300d04SMaxime Bizon clk_enable_unlocked(clk); 239e7300d04SMaxime Bizon mutex_unlock(&clocks_mutex); 240e7300d04SMaxime Bizon return 0; 241e7300d04SMaxime Bizon } 242e7300d04SMaxime Bizon 243e7300d04SMaxime Bizon EXPORT_SYMBOL(clk_enable); 244e7300d04SMaxime Bizon 245e7300d04SMaxime Bizon void clk_disable(struct clk *clk) 246e7300d04SMaxime Bizon { 247e7300d04SMaxime Bizon mutex_lock(&clocks_mutex); 248e7300d04SMaxime Bizon clk_disable_unlocked(clk); 249e7300d04SMaxime Bizon mutex_unlock(&clocks_mutex); 250e7300d04SMaxime Bizon } 251e7300d04SMaxime Bizon 252e7300d04SMaxime Bizon EXPORT_SYMBOL(clk_disable); 253e7300d04SMaxime Bizon 254e7300d04SMaxime Bizon unsigned long clk_get_rate(struct clk *clk) 255e7300d04SMaxime Bizon { 256e7300d04SMaxime Bizon return clk->rate; 257e7300d04SMaxime Bizon } 258e7300d04SMaxime Bizon 259e7300d04SMaxime Bizon EXPORT_SYMBOL(clk_get_rate); 260e7300d04SMaxime Bizon 261e7300d04SMaxime Bizon struct clk *clk_get(struct device *dev, const char *id) 262e7300d04SMaxime Bizon { 263e7300d04SMaxime Bizon if (!strcmp(id, "enet0")) 264e7300d04SMaxime Bizon return &clk_enet0; 265e7300d04SMaxime Bizon if (!strcmp(id, "enet1")) 266e7300d04SMaxime Bizon return &clk_enet1; 267*04712f3fSMaxime Bizon if (!strcmp(id, "enetsw")) 268*04712f3fSMaxime Bizon return &clk_enetsw; 269e7300d04SMaxime Bizon if (!strcmp(id, "ephy")) 270e7300d04SMaxime Bizon return &clk_ephy; 271e7300d04SMaxime Bizon if (!strcmp(id, "usbh")) 272e7300d04SMaxime Bizon return &clk_usbh; 273e7300d04SMaxime Bizon if (!strcmp(id, "spi")) 274e7300d04SMaxime Bizon return &clk_spi; 275*04712f3fSMaxime Bizon if (!strcmp(id, "xtm")) 276*04712f3fSMaxime Bizon return &clk_xtm; 277e7300d04SMaxime Bizon if (!strcmp(id, "periph")) 278e7300d04SMaxime Bizon return &clk_periph; 279e7300d04SMaxime Bizon if (BCMCPU_IS_6358() && !strcmp(id, "pcm")) 280e7300d04SMaxime Bizon return &clk_pcm; 281e7300d04SMaxime Bizon return ERR_PTR(-ENOENT); 282e7300d04SMaxime Bizon } 283e7300d04SMaxime Bizon 284e7300d04SMaxime Bizon EXPORT_SYMBOL(clk_get); 285e7300d04SMaxime Bizon 286e7300d04SMaxime Bizon void clk_put(struct clk *clk) 287e7300d04SMaxime Bizon { 288e7300d04SMaxime Bizon } 289e7300d04SMaxime Bizon 290e7300d04SMaxime Bizon EXPORT_SYMBOL(clk_put); 291