1 /* 2 * arch/m68k/q40/config.c 3 * 4 * Copyright (C) 1999 Richard Zidlicky 5 * 6 * originally based on: 7 * 8 * linux/bvme/config.c 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file README.legal in the main directory of this archive 12 * for more details. 13 */ 14 15 #include <linux/config.h> 16 #include <linux/types.h> 17 #include <linux/kernel.h> 18 #include <linux/mm.h> 19 #include <linux/tty.h> 20 #include <linux/console.h> 21 #include <linux/linkage.h> 22 #include <linux/init.h> 23 #include <linux/major.h> 24 #include <linux/serial_reg.h> 25 #include <linux/rtc.h> 26 #include <linux/vt_kern.h> 27 28 #include <asm/io.h> 29 #include <asm/rtc.h> 30 #include <asm/bootinfo.h> 31 #include <asm/system.h> 32 #include <asm/pgtable.h> 33 #include <asm/setup.h> 34 #include <asm/irq.h> 35 #include <asm/traps.h> 36 #include <asm/machdep.h> 37 #include <asm/q40_master.h> 38 39 extern void floppy_setup(char *str, int *ints); 40 41 extern irqreturn_t q40_process_int (int level, struct pt_regs *regs); 42 extern irqreturn_t (*q40_default_handler[]) (int, void *, struct pt_regs *); /* added just for debugging */ 43 extern void q40_init_IRQ (void); 44 extern void q40_free_irq (unsigned int, void *); 45 extern int show_q40_interrupts (struct seq_file *, void *); 46 extern void q40_enable_irq (unsigned int); 47 extern void q40_disable_irq (unsigned int); 48 static void q40_get_model(char *model); 49 static int q40_get_hardware_list(char *buffer); 50 extern int q40_request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *), unsigned long flags, const char *devname, void *dev_id); 51 extern void q40_sched_init(irqreturn_t (*handler)(int, void *, struct pt_regs *)); 52 53 extern unsigned long q40_gettimeoffset (void); 54 extern int q40_hwclk (int, struct rtc_time *); 55 extern unsigned int q40_get_ss (void); 56 extern int q40_set_clock_mmss (unsigned long); 57 static int q40_get_rtc_pll(struct rtc_pll_info *pll); 58 static int q40_set_rtc_pll(struct rtc_pll_info *pll); 59 extern void q40_reset (void); 60 void q40_halt(void); 61 extern void q40_waitbut(void); 62 void q40_set_vectors (void); 63 64 extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/ ); 65 66 extern char m68k_debug_device[]; 67 static void q40_mem_console_write(struct console *co, const char *b, 68 unsigned int count); 69 70 extern int ql_ticks; 71 72 static struct console q40_console_driver = { 73 .name = "debug", 74 .flags = CON_PRINTBUFFER, 75 .index = -1, 76 }; 77 78 79 /* early debugging function:*/ 80 extern char *q40_mem_cptr; /*=(char *)0xff020000;*/ 81 static int _cpleft; 82 83 static void q40_mem_console_write(struct console *co, const char *s, 84 unsigned int count) 85 { 86 char *p=(char *)s; 87 88 if (count<_cpleft) 89 while (count-- >0){ 90 *q40_mem_cptr=*p++; 91 q40_mem_cptr+=4; 92 _cpleft--; 93 } 94 } 95 #if 0 96 void printq40(char *str) 97 { 98 int l=strlen(str); 99 char *p=q40_mem_cptr; 100 101 while (l-- >0 && _cpleft-- >0) 102 { 103 *p=*str++; 104 p+=4; 105 } 106 q40_mem_cptr=p; 107 } 108 #endif 109 110 static int halted=0; 111 112 #ifdef CONFIG_HEARTBEAT 113 static void q40_heartbeat(int on) 114 { 115 if (halted) return; 116 117 if (on) 118 Q40_LED_ON(); 119 else 120 Q40_LED_OFF(); 121 } 122 #endif 123 124 void q40_reset(void) 125 { 126 halted=1; 127 printk ("\n\n*******************************************\n" 128 "Called q40_reset : press the RESET button!! \n" 129 "*******************************************\n"); 130 Q40_LED_ON(); 131 while(1) ; 132 } 133 void q40_halt(void) 134 { 135 halted=1; 136 printk ("\n\n*******************\n" 137 " Called q40_halt\n" 138 "*******************\n"); 139 Q40_LED_ON(); 140 while(1) ; 141 } 142 143 static void q40_get_model(char *model) 144 { 145 sprintf(model, "Q40"); 146 } 147 148 /* No hardware options on Q40? */ 149 150 static int q40_get_hardware_list(char *buffer) 151 { 152 *buffer = '\0'; 153 return 0; 154 } 155 156 static unsigned int serports[]={0x3f8,0x2f8,0x3e8,0x2e8,0}; 157 void q40_disable_irqs(void) 158 { 159 unsigned i,j; 160 161 j=0; 162 while((i=serports[j++])) outb(0,i+UART_IER); 163 master_outb(0,EXT_ENABLE_REG); 164 master_outb(0,KEY_IRQ_ENABLE_REG); 165 } 166 167 void __init config_q40(void) 168 { 169 mach_sched_init = q40_sched_init; 170 171 mach_init_IRQ = q40_init_IRQ; 172 mach_gettimeoffset = q40_gettimeoffset; 173 mach_hwclk = q40_hwclk; 174 mach_get_ss = q40_get_ss; 175 mach_get_rtc_pll = q40_get_rtc_pll; 176 mach_set_rtc_pll = q40_set_rtc_pll; 177 mach_set_clock_mmss = q40_set_clock_mmss; 178 179 mach_reset = q40_reset; 180 mach_free_irq = q40_free_irq; 181 mach_process_int = q40_process_int; 182 mach_get_irq_list = show_q40_interrupts; 183 mach_request_irq = q40_request_irq; 184 enable_irq = q40_enable_irq; 185 disable_irq = q40_disable_irq; 186 mach_default_handler = &q40_default_handler; 187 mach_get_model = q40_get_model; 188 mach_get_hardware_list = q40_get_hardware_list; 189 190 #if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE) 191 mach_beep = q40_mksound; 192 #endif 193 #ifdef CONFIG_HEARTBEAT 194 mach_heartbeat = q40_heartbeat; 195 #endif 196 mach_halt = q40_halt; 197 #ifdef CONFIG_DUMMY_CONSOLE 198 conswitchp = &dummy_con; 199 #endif 200 201 /* disable a few things that SMSQ might have left enabled */ 202 q40_disable_irqs(); 203 204 /* no DMA at all, but ide-scsi requires it.. make sure 205 * all physical RAM fits into the boundary - otherwise 206 * allocator may play costly and useless tricks */ 207 mach_max_dma_address = 1024*1024*1024; 208 209 /* useful for early debugging stages - writes kernel messages into SRAM */ 210 if (!strncmp( m68k_debug_device,"mem",3 )) 211 { 212 /*printk("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/ 213 _cpleft=2000-((long)q40_mem_cptr-0xff020000)/4; 214 q40_console_driver.write = q40_mem_console_write; 215 register_console(&q40_console_driver); 216 } 217 } 218 219 220 int q40_parse_bootinfo(const struct bi_record *rec) 221 { 222 return 1; 223 } 224 225 226 static inline unsigned char bcd2bin (unsigned char b) 227 { 228 return ((b>>4)*10 + (b&15)); 229 } 230 231 static inline unsigned char bin2bcd (unsigned char b) 232 { 233 return (((b/10)*16) + (b%10)); 234 } 235 236 237 unsigned long q40_gettimeoffset (void) 238 { 239 return 5000*(ql_ticks!=0); 240 } 241 242 243 /* 244 * Looks like op is non-zero for setting the clock, and zero for 245 * reading the clock. 246 * 247 * struct hwclk_time { 248 * unsigned sec; 0..59 249 * unsigned min; 0..59 250 * unsigned hour; 0..23 251 * unsigned day; 1..31 252 * unsigned mon; 0..11 253 * unsigned year; 00... 254 * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set 255 * }; 256 */ 257 258 int q40_hwclk(int op, struct rtc_time *t) 259 { 260 if (op) 261 { /* Write.... */ 262 Q40_RTC_CTRL |= Q40_RTC_WRITE; 263 264 Q40_RTC_SECS = bin2bcd(t->tm_sec); 265 Q40_RTC_MINS = bin2bcd(t->tm_min); 266 Q40_RTC_HOUR = bin2bcd(t->tm_hour); 267 Q40_RTC_DATE = bin2bcd(t->tm_mday); 268 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1); 269 Q40_RTC_YEAR = bin2bcd(t->tm_year%100); 270 if (t->tm_wday >= 0) 271 Q40_RTC_DOW = bin2bcd(t->tm_wday+1); 272 273 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); 274 } 275 else 276 { /* Read.... */ 277 Q40_RTC_CTRL |= Q40_RTC_READ; 278 279 t->tm_year = bcd2bin (Q40_RTC_YEAR); 280 t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1; 281 t->tm_mday = bcd2bin (Q40_RTC_DATE); 282 t->tm_hour = bcd2bin (Q40_RTC_HOUR); 283 t->tm_min = bcd2bin (Q40_RTC_MINS); 284 t->tm_sec = bcd2bin (Q40_RTC_SECS); 285 286 Q40_RTC_CTRL &= ~(Q40_RTC_READ); 287 288 if (t->tm_year < 70) 289 t->tm_year += 100; 290 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1; 291 292 } 293 294 return 0; 295 } 296 297 unsigned int q40_get_ss(void) 298 { 299 return bcd2bin(Q40_RTC_SECS); 300 } 301 302 /* 303 * Set the minutes and seconds from seconds value 'nowtime'. Fail if 304 * clock is out by > 30 minutes. Logic lifted from atari code. 305 */ 306 307 int q40_set_clock_mmss (unsigned long nowtime) 308 { 309 int retval = 0; 310 short real_seconds = nowtime % 60, real_minutes = (nowtime / 60) % 60; 311 312 int rtc_minutes; 313 314 315 rtc_minutes = bcd2bin (Q40_RTC_MINS); 316 317 if ((rtc_minutes < real_minutes 318 ? real_minutes - rtc_minutes 319 : rtc_minutes - real_minutes) < 30) 320 { 321 Q40_RTC_CTRL |= Q40_RTC_WRITE; 322 Q40_RTC_MINS = bin2bcd(real_minutes); 323 Q40_RTC_SECS = bin2bcd(real_seconds); 324 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); 325 } 326 else 327 retval = -1; 328 329 330 return retval; 331 } 332 333 334 /* get and set PLL calibration of RTC clock */ 335 #define Q40_RTC_PLL_MASK ((1<<5)-1) 336 #define Q40_RTC_PLL_SIGN (1<<5) 337 338 static int q40_get_rtc_pll(struct rtc_pll_info *pll) 339 { 340 int tmp=Q40_RTC_CTRL; 341 pll->pll_value = tmp & Q40_RTC_PLL_MASK; 342 if (tmp & Q40_RTC_PLL_SIGN) 343 pll->pll_value = -pll->pll_value; 344 pll->pll_max=31; 345 pll->pll_min=-31; 346 pll->pll_posmult=512; 347 pll->pll_negmult=256; 348 pll->pll_clock=125829120; 349 return 0; 350 } 351 352 static int q40_set_rtc_pll(struct rtc_pll_info *pll) 353 { 354 if (!pll->pll_ctrl){ 355 /* the docs are a bit unclear so I am doublesetting */ 356 /* RTC_WRITE here ... */ 357 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) | 358 Q40_RTC_WRITE; 359 Q40_RTC_CTRL |= Q40_RTC_WRITE; 360 Q40_RTC_CTRL = tmp; 361 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); 362 return 0; 363 } else 364 return -EINVAL; 365 } 366