1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 249148020SSam Ravnborg /****************************************************************************/ 349148020SSam Ravnborg 449148020SSam Ravnborg /* 549148020SSam Ravnborg * nettel.h -- Lineo (formerly Moreton Bay) NETtel support. 649148020SSam Ravnborg * 749148020SSam Ravnborg * (C) Copyright 1999-2000, Moreton Bay (www.moretonbay.com) 849148020SSam Ravnborg * (C) Copyright 2000-2001, Lineo Inc. (www.lineo.com) 949148020SSam Ravnborg * (C) Copyright 2001-2002, SnapGear Inc., (www.snapgear.com) 1049148020SSam Ravnborg */ 1149148020SSam Ravnborg 1249148020SSam Ravnborg /****************************************************************************/ 1349148020SSam Ravnborg #ifndef nettel_h 1449148020SSam Ravnborg #define nettel_h 1549148020SSam Ravnborg /****************************************************************************/ 1649148020SSam Ravnborg 1749148020SSam Ravnborg 1849148020SSam Ravnborg /****************************************************************************/ 1949148020SSam Ravnborg #ifdef CONFIG_NETtel 2049148020SSam Ravnborg /****************************************************************************/ 2149148020SSam Ravnborg 2249148020SSam Ravnborg #ifdef CONFIG_COLDFIRE 2349148020SSam Ravnborg #include <asm/coldfire.h> 2449148020SSam Ravnborg #include <asm/mcfsim.h> 254fb62edeSGreg Ungerer #include <asm/io.h> 2649148020SSam Ravnborg #endif 2749148020SSam Ravnborg 2849148020SSam Ravnborg /*---------------------------------------------------------------------------*/ 2949148020SSam Ravnborg #if defined(CONFIG_M5307) 3049148020SSam Ravnborg /* 3149148020SSam Ravnborg * NETtel/5307 based hardware first. DTR/DCD lines are wired to 3249148020SSam Ravnborg * GPIO lines. Most of the LED's are driver through a latch 3349148020SSam Ravnborg * connected to CS2. 3449148020SSam Ravnborg */ 3549148020SSam Ravnborg #define MCFPP_DCD1 0x0001 3649148020SSam Ravnborg #define MCFPP_DCD0 0x0002 3749148020SSam Ravnborg #define MCFPP_DTR1 0x0004 3849148020SSam Ravnborg #define MCFPP_DTR0 0x0008 3949148020SSam Ravnborg 4049148020SSam Ravnborg #define NETtel_LEDADDR 0x30400000 4149148020SSam Ravnborg 4249148020SSam Ravnborg #ifndef __ASSEMBLY__ 4349148020SSam Ravnborg 4449148020SSam Ravnborg extern volatile unsigned short ppdata; 4549148020SSam Ravnborg 4649148020SSam Ravnborg /* 4749148020SSam Ravnborg * These functions defined to give quasi generic access to the 4849148020SSam Ravnborg * PPIO bits used for DTR/DCD. 4949148020SSam Ravnborg */ mcf_getppdata(void)5049148020SSam Ravnborgstatic __inline__ unsigned int mcf_getppdata(void) 5149148020SSam Ravnborg { 5249148020SSam Ravnborg volatile unsigned short *pp; 53732c611eSsfking@fdwdc.com pp = (volatile unsigned short *) MCFSIM_PADAT; 5449148020SSam Ravnborg return((unsigned int) *pp); 5549148020SSam Ravnborg } 5649148020SSam Ravnborg mcf_setppdata(unsigned int mask,unsigned int bits)5749148020SSam Ravnborgstatic __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) 5849148020SSam Ravnborg { 5949148020SSam Ravnborg volatile unsigned short *pp; 60732c611eSsfking@fdwdc.com pp = (volatile unsigned short *) MCFSIM_PADAT; 6149148020SSam Ravnborg ppdata = (ppdata & ~mask) | bits; 6249148020SSam Ravnborg *pp = ppdata; 6349148020SSam Ravnborg } 6449148020SSam Ravnborg #endif 6549148020SSam Ravnborg 6649148020SSam Ravnborg /*---------------------------------------------------------------------------*/ 6749148020SSam Ravnborg #elif defined(CONFIG_M5206e) 6849148020SSam Ravnborg /* 6949148020SSam Ravnborg * NETtel/5206e based hardware has leds on latch on CS3. 7049148020SSam Ravnborg * No support modem for lines?? 7149148020SSam Ravnborg */ 7249148020SSam Ravnborg #define NETtel_LEDADDR 0x50000000 7349148020SSam Ravnborg 7449148020SSam Ravnborg /*---------------------------------------------------------------------------*/ 7549148020SSam Ravnborg #elif defined(CONFIG_M5272) 7649148020SSam Ravnborg /* 7749148020SSam Ravnborg * NETtel/5272 based hardware. DTR/DCD lines are wired to GPB lines. 7849148020SSam Ravnborg */ 7949148020SSam Ravnborg #define MCFPP_DCD0 0x0080 8049148020SSam Ravnborg #define MCFPP_DCD1 0x0000 /* Port 1 no DCD support */ 8149148020SSam Ravnborg #define MCFPP_DTR0 0x0040 8249148020SSam Ravnborg #define MCFPP_DTR1 0x0000 /* Port 1 no DTR support */ 8349148020SSam Ravnborg 8449148020SSam Ravnborg #ifndef __ASSEMBLY__ 8549148020SSam Ravnborg /* 8649148020SSam Ravnborg * These functions defined to give quasi generic access to the 8749148020SSam Ravnborg * PPIO bits used for DTR/DCD. 8849148020SSam Ravnborg */ mcf_getppdata(void)8949148020SSam Ravnborgstatic __inline__ unsigned int mcf_getppdata(void) 9049148020SSam Ravnborg { 914fb62edeSGreg Ungerer return readw(MCFSIM_PBDAT); 9249148020SSam Ravnborg } 9349148020SSam Ravnborg mcf_setppdata(unsigned int mask,unsigned int bits)9449148020SSam Ravnborgstatic __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) 9549148020SSam Ravnborg { 9636d050d9SGreg Ungerer writew((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT); 9749148020SSam Ravnborg } 9849148020SSam Ravnborg #endif 9949148020SSam Ravnborg 10049148020SSam Ravnborg #endif 10149148020SSam Ravnborg /*---------------------------------------------------------------------------*/ 10249148020SSam Ravnborg 10349148020SSam Ravnborg /****************************************************************************/ 10449148020SSam Ravnborg #endif /* CONFIG_NETtel */ 10549148020SSam Ravnborg /****************************************************************************/ 10649148020SSam Ravnborg #endif /* nettel_h */ 107