1 | 2 | fpsp.h 3.3 3.3 3 | 4 5 | Copyright (C) Motorola, Inc. 1990 6 | All Rights Reserved 7 | 8 | THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA 9 | The copyright notice above does not evidence any 10 | actual or intended publication of such source code. 11 12 | fpsp.h --- stack frame offsets during FPSP exception handling 13 | 14 | These equates are used to access the exception frame, the fsave 15 | frame and any local variables needed by the FPSP package. 16 | 17 | All FPSP handlers begin by executing: 18 | 19 | link a6,#-LOCAL_SIZE 20 | fsave -(a7) 21 | movem.l d0-d1/a0-a1,USER_DA(a6) 22 | fmovem.x fp0-fp3,USER_FP0(a6) 23 | fmove.l fpsr/fpcr/fpiar,USER_FPSR(a6) 24 | 25 | After initialization, the stack looks like this: 26 | 27 | A7 ---> +-------------------------------+ 28 | | | 29 | | FPU fsave area | 30 | | | 31 | +-------------------------------+ 32 | | | 33 | | FPSP Local Variables | 34 | | including | 35 | | saved registers | 36 | | | 37 | +-------------------------------+ 38 | A6 ---> | Saved A6 | 39 | +-------------------------------+ 40 | | | 41 | | Exception Frame | 42 | | | 43 | | | 44 | 45 | Positive offsets from A6 refer to the exception frame. Negative 46 | offsets refer to the Local Variable area and the fsave area. 47 | The fsave frame is also accessible from the top via A7. 48 | 49 | On exit, the handlers execute: 50 | 51 | movem.l USER_DA(a6),d0-d1/a0-a1 52 | fmovem.x USER_FP0(a6),fp0-fp3 53 | fmove.l USER_FPSR(a6),fpsr/fpcr/fpiar 54 | frestore (a7)+ 55 | unlk a6 56 | 57 | and then either "bra fpsp_done" if the exception was completely 58 | handled by the package, or "bra real_xxxx" which is an external 59 | label to a routine that will process a real exception of the 60 | type that was generated. Some handlers may omit the "frestore" 61 | if the FPU state after the exception is idle. 62 | 63 | Sometimes the exception handler will transform the fsave area 64 | because it needs to report an exception back to the user. This 65 | can happen if the package is entered for an unimplemented float 66 | instruction that generates (say) an underflow. Alternatively, 67 | a second fsave frame can be pushed onto the stack and the 68 | handler exit code will reload the new frame and discard the old. 69 | 70 | The registers d0, d1, a0, a1 and fp0-fp3 are always saved and 71 | restored from the "local variable" area and can be used as 72 | temporaries. If a routine needs to change any 73 | of these registers, it should modify the saved copy and let 74 | the handler exit code restore the value. 75 | 76 |---------------------------------------------------------------------- 77 | 78 | Local Variables on the stack 79 | 80 .set LOCAL_SIZE,192 | bytes needed for local variables 81 .set LV,-LOCAL_SIZE | convenient base value 82 | 83 .set USER_DA,LV+0 | save space for D0-D1,A0-A1 84 .set USER_D0,LV+0 | saved user D0 85 .set USER_D1,LV+4 | saved user D1 86 .set USER_A0,LV+8 | saved user A0 87 .set USER_A1,LV+12 | saved user A1 88 .set USER_FP0,LV+16 | saved user FP0 89 .set USER_FP1,LV+28 | saved user FP1 90 .set USER_FP2,LV+40 | saved user FP2 91 .set USER_FP3,LV+52 | saved user FP3 92 .set USER_FPCR,LV+64 | saved user FPCR 93 .set FPCR_ENABLE,USER_FPCR+2 | FPCR exception enable 94 .set FPCR_MODE,USER_FPCR+3 | FPCR rounding mode control 95 .set USER_FPSR,LV+68 | saved user FPSR 96 .set FPSR_CC,USER_FPSR+0 | FPSR condition code 97 .set FPSR_QBYTE,USER_FPSR+1 | FPSR quotient 98 .set FPSR_EXCEPT,USER_FPSR+2 | FPSR exception 99 .set FPSR_AEXCEPT,USER_FPSR+3 | FPSR accrued exception 100 .set USER_FPIAR,LV+72 | saved user FPIAR 101 .set FP_SCR1,LV+76 | room for a temporary float value 102 .set FP_SCR2,LV+92 | room for a temporary float value 103 .set L_SCR1,LV+108 | room for a temporary long value 104 .set L_SCR2,LV+112 | room for a temporary long value 105 .set STORE_FLG,LV+116 106 .set BINDEC_FLG,LV+117 | used in bindec 107 .set DNRM_FLG,LV+118 | used in res_func 108 .set RES_FLG,LV+119 | used in res_func 109 .set DY_MO_FLG,LV+120 | dyadic/monadic flag 110 .set UFLG_TMP,LV+121 | temporary for uflag errata 111 .set CU_ONLY,LV+122 | cu-only flag 112 .set VER_TMP,LV+123 | temp holding for version number 113 .set L_SCR3,LV+124 | room for a temporary long value 114 .set FP_SCR3,LV+128 | room for a temporary float value 115 .set FP_SCR4,LV+144 | room for a temporary float value 116 .set FP_SCR5,LV+160 | room for a temporary float value 117 .set FP_SCR6,LV+176 118 | 119 |NEXT equ LV+192 ;need to increase LOCAL_SIZE 120 | 121 |-------------------------------------------------------------------------- 122 | 123 | fsave offsets and bit definitions 124 | 125 | Offsets are defined from the end of an fsave because the last 10 126 | words of a busy frame are the same as the unimplemented frame. 127 | 128 .set CU_SAVEPC,LV-92 | micro-pc for CU (1 byte) 129 .set FPR_DIRTY_BITS,LV-91 | fpr dirty bits 130 | 131 .set WBTEMP,LV-76 | write back temp (12 bytes) 132 .set WBTEMP_EX,WBTEMP | wbtemp sign and exponent (2 bytes) 133 .set WBTEMP_HI,WBTEMP+4 | wbtemp mantissa [63:32] (4 bytes) 134 .set WBTEMP_LO,WBTEMP+8 | wbtemp mantissa [31:00] (4 bytes) 135 | 136 .set WBTEMP_SGN,WBTEMP+2 | used to store sign 137 | 138 .set FPSR_SHADOW,LV-64 | fpsr shadow reg 139 | 140 .set FPIARCU,LV-60 | Instr. addr. reg. for CU (4 bytes) 141 | 142 .set CMDREG2B,LV-52 | cmd reg for machine 2 143 .set CMDREG3B,LV-48 | cmd reg for E3 exceptions (2 bytes) 144 | 145 .set NMNEXC,LV-44 | NMNEXC (unsup,snan bits only) 146 .set nmn_unsup_bit,1 | 147 .set nmn_snan_bit,0 | 148 | 149 .set NMCEXC,LV-43 | NMNEXC & NMCEXC 150 .set nmn_operr_bit,7 151 .set nmn_ovfl_bit,6 152 .set nmn_unfl_bit,5 153 .set nmc_unsup_bit,4 154 .set nmc_snan_bit,3 155 .set nmc_operr_bit,2 156 .set nmc_ovfl_bit,1 157 .set nmc_unfl_bit,0 158 | 159 .set STAG,LV-40 | source tag (1 byte) 160 .set WBTEMP_GRS,LV-40 | alias wbtemp guard, round, sticky 161 .set guard_bit,1 | guard bit is bit number 1 162 .set round_bit,0 | round bit is bit number 0 163 .set stag_mask,0xE0 | upper 3 bits are source tag type 164 .set denorm_bit,7 | bit determines if denorm or unnorm 165 .set etemp15_bit,4 | etemp exponent bit #15 166 .set wbtemp66_bit,2 | wbtemp mantissa bit #66 167 .set wbtemp1_bit,1 | wbtemp mantissa bit #1 168 .set wbtemp0_bit,0 | wbtemp mantissa bit #0 169 | 170 .set STICKY,LV-39 | holds sticky bit 171 .set sticky_bit,7 172 | 173 .set CMDREG1B,LV-36 | cmd reg for E1 exceptions (2 bytes) 174 .set kfact_bit,12 | distinguishes static/dynamic k-factor 175 | ;on packed move outs. NOTE: this 176 | ;equate only works when CMDREG1B is in 177 | ;a register. 178 | 179 .set CMDWORD,LV-35 | command word in cmd1b 180 .set direction_bit,5 | bit 0 in opclass 181 .set size_bit2,12 | bit 2 in size field 182 | 183 .set DTAG,LV-32 | dest tag (1 byte) 184 .set dtag_mask,0xE0 | upper 3 bits are dest type tag 185 .set fptemp15_bit,4 | fptemp exponent bit #15 186 | 187 .set WB_BYTE,LV-31 | holds WBTE15 bit (1 byte) 188 .set wbtemp15_bit,4 | wbtemp exponent bit #15 189 | 190 .set E_BYTE,LV-28 | holds E1 and E3 bits (1 byte) 191 .set E1,2 | which bit is E1 flag 192 .set E3,1 | which bit is E3 flag 193 .set SFLAG,0 | which bit is S flag 194 | 195 .set T_BYTE,LV-27 | holds T and U bits (1 byte) 196 .set XFLAG,7 | which bit is X flag 197 .set UFLAG,5 | which bit is U flag 198 .set TFLAG,4 | which bit is T flag 199 | 200 .set FPTEMP,LV-24 | fptemp (12 bytes) 201 .set FPTEMP_EX,FPTEMP | fptemp sign and exponent (2 bytes) 202 .set FPTEMP_HI,FPTEMP+4 | fptemp mantissa [63:32] (4 bytes) 203 .set FPTEMP_LO,FPTEMP+8 | fptemp mantissa [31:00] (4 bytes) 204 | 205 .set FPTEMP_SGN,FPTEMP+2 | used to store sign 206 | 207 .set ETEMP,LV-12 | etemp (12 bytes) 208 .set ETEMP_EX,ETEMP | etemp sign and exponent (2 bytes) 209 .set ETEMP_HI,ETEMP+4 | etemp mantissa [63:32] (4 bytes) 210 .set ETEMP_LO,ETEMP+8 | etemp mantissa [31:00] (4 bytes) 211 | 212 .set ETEMP_SGN,ETEMP+2 | used to store sign 213 | 214 .set EXC_SR,4 | exception frame status register 215 .set EXC_PC,6 | exception frame program counter 216 .set EXC_VEC,10 | exception frame vector (format+vector#) 217 .set EXC_EA,12 | exception frame effective address 218 | 219 |-------------------------------------------------------------------------- 220 | 221 | FPSR/FPCR bits 222 | 223 .set neg_bit,3 | negative result 224 .set z_bit,2 | zero result 225 .set inf_bit,1 | infinity result 226 .set nan_bit,0 | not-a-number result 227 | 228 .set q_sn_bit,7 | sign bit of quotient byte 229 | 230 .set bsun_bit,7 | branch on unordered 231 .set snan_bit,6 | signalling nan 232 .set operr_bit,5 | operand error 233 .set ovfl_bit,4 | overflow 234 .set unfl_bit,3 | underflow 235 .set dz_bit,2 | divide by zero 236 .set inex2_bit,1 | inexact result 2 237 .set inex1_bit,0 | inexact result 1 238 | 239 .set aiop_bit,7 | accrued illegal operation 240 .set aovfl_bit,6 | accrued overflow 241 .set aunfl_bit,5 | accrued underflow 242 .set adz_bit,4 | accrued divide by zero 243 .set ainex_bit,3 | accrued inexact 244 | 245 | FPSR individual bit masks 246 | 247 .set neg_mask,0x08000000 248 .set z_mask,0x04000000 249 .set inf_mask,0x02000000 250 .set nan_mask,0x01000000 251 | 252 .set bsun_mask,0x00008000 | 253 .set snan_mask,0x00004000 254 .set operr_mask,0x00002000 255 .set ovfl_mask,0x00001000 256 .set unfl_mask,0x00000800 257 .set dz_mask,0x00000400 258 .set inex2_mask,0x00000200 259 .set inex1_mask,0x00000100 260 | 261 .set aiop_mask,0x00000080 | accrued illegal operation 262 .set aovfl_mask,0x00000040 | accrued overflow 263 .set aunfl_mask,0x00000020 | accrued underflow 264 .set adz_mask,0x00000010 | accrued divide by zero 265 .set ainex_mask,0x00000008 | accrued inexact 266 | 267 | FPSR combinations used in the FPSP 268 | 269 .set dzinf_mask,inf_mask+dz_mask+adz_mask 270 .set opnan_mask,nan_mask+operr_mask+aiop_mask 271 .set nzi_mask,0x01ffffff | clears N, Z, and I 272 .set unfinx_mask,unfl_mask+inex2_mask+aunfl_mask+ainex_mask 273 .set unf2inx_mask,unfl_mask+inex2_mask+ainex_mask 274 .set ovfinx_mask,ovfl_mask+inex2_mask+aovfl_mask+ainex_mask 275 .set inx1a_mask,inex1_mask+ainex_mask 276 .set inx2a_mask,inex2_mask+ainex_mask 277 .set snaniop_mask,nan_mask+snan_mask+aiop_mask 278 .set naniop_mask,nan_mask+aiop_mask 279 .set neginf_mask,neg_mask+inf_mask 280 .set infaiop_mask,inf_mask+aiop_mask 281 .set negz_mask,neg_mask+z_mask 282 .set opaop_mask,operr_mask+aiop_mask 283 .set unfl_inx_mask,unfl_mask+aunfl_mask+ainex_mask 284 .set ovfl_inx_mask,ovfl_mask+aovfl_mask+ainex_mask 285 | 286 |-------------------------------------------------------------------------- 287 | 288 | FPCR rounding modes 289 | 290 .set x_mode,0x00 | round to extended 291 .set s_mode,0x40 | round to single 292 .set d_mode,0x80 | round to double 293 | 294 .set rn_mode,0x00 | round nearest 295 .set rz_mode,0x10 | round to zero 296 .set rm_mode,0x20 | round to minus infinity 297 .set rp_mode,0x30 | round to plus infinity 298 | 299 |-------------------------------------------------------------------------- 300 | 301 | Miscellaneous equates 302 | 303 .set signan_bit,6 | signalling nan bit in mantissa 304 .set sign_bit,7 305 | 306 .set rnd_stky_bit,29 | round/sticky bit of mantissa 307 | this can only be used if in a data register 308 .set sx_mask,0x01800000 | set s and x bits in word $48 309 | 310 .set LOCAL_EX,0 311 .set LOCAL_SGN,2 312 .set LOCAL_HI,4 313 .set LOCAL_LO,8 314 .set LOCAL_GRS,12 | valid ONLY for FP_SCR1, FP_SCR2 315 | 316 | 317 .set norm_tag,0x00 | tag bits in {7:5} position 318 .set zero_tag,0x20 319 .set inf_tag,0x40 320 .set nan_tag,0x60 321 .set dnrm_tag,0x80 322 | 323 | fsave sizes and formats 324 | 325 .set VER_4,0x40 | fpsp compatible version numbers 326 | are in the $40s {$40-$4f} 327 .set VER_40,0x40 | original version number 328 .set VER_41,0x41 | revision version number 329 | 330 .set BUSY_SIZE,100 | size of busy frame 331 .set BUSY_FRAME,LV-BUSY_SIZE | start of busy frame 332 | 333 .set UNIMP_40_SIZE,44 | size of orig unimp frame 334 .set UNIMP_41_SIZE,52 | size of rev unimp frame 335 | 336 .set IDLE_SIZE,4 | size of idle frame 337 .set IDLE_FRAME,LV-IDLE_SIZE | start of idle frame 338 | 339 | exception vectors 340 | 341 .set TRACE_VEC,0x2024 | trace trap 342 .set FLINE_VEC,0x002C | real F-line 343 .set UNIMP_VEC,0x202C | unimplemented 344 .set INEX_VEC,0x00C4 345 | 346 .set dbl_thresh,0x3C01 347 .set sgl_thresh,0x3F81 348 | 349