1803b0fc5SHuacai Chen /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ 2803b0fc5SHuacai Chen /* 3803b0fc5SHuacai Chen * Author: Hanlu Li <lihanlu@loongson.cn> 4803b0fc5SHuacai Chen * Huacai Chen <chenhuacai@loongson.cn> 5803b0fc5SHuacai Chen * 6803b0fc5SHuacai Chen * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 7803b0fc5SHuacai Chen */ 8803b0fc5SHuacai Chen #ifndef _UAPI_ASM_PTRACE_H 9803b0fc5SHuacai Chen #define _UAPI_ASM_PTRACE_H 10803b0fc5SHuacai Chen 11803b0fc5SHuacai Chen #include <linux/types.h> 12803b0fc5SHuacai Chen 13803b0fc5SHuacai Chen #ifndef __KERNEL__ 14803b0fc5SHuacai Chen #include <stdint.h> 15803b0fc5SHuacai Chen #endif 16803b0fc5SHuacai Chen 17803b0fc5SHuacai Chen /* 18803b0fc5SHuacai Chen * For PTRACE_{POKE,PEEK}USR. 0 - 31 are GPRs, 19803b0fc5SHuacai Chen * 32 is syscall's original ARG0, 33 is PC, 34 is BADVADDR. 20803b0fc5SHuacai Chen */ 21803b0fc5SHuacai Chen #define GPR_BASE 0 22803b0fc5SHuacai Chen #define GPR_NUM 32 23803b0fc5SHuacai Chen #define GPR_END (GPR_BASE + GPR_NUM - 1) 24803b0fc5SHuacai Chen #define ARG0 (GPR_END + 1) 25803b0fc5SHuacai Chen #define PC (GPR_END + 2) 26803b0fc5SHuacai Chen #define BADVADDR (GPR_END + 3) 27803b0fc5SHuacai Chen 28803b0fc5SHuacai Chen #define NUM_FPU_REGS 32 29803b0fc5SHuacai Chen 30803b0fc5SHuacai Chen struct user_pt_regs { 31803b0fc5SHuacai Chen /* Main processor registers. */ 32803b0fc5SHuacai Chen unsigned long regs[32]; 33803b0fc5SHuacai Chen 34803b0fc5SHuacai Chen /* Original syscall arg0. */ 35803b0fc5SHuacai Chen unsigned long orig_a0; 36803b0fc5SHuacai Chen 37803b0fc5SHuacai Chen /* Special CSR registers. */ 38803b0fc5SHuacai Chen unsigned long csr_era; 39803b0fc5SHuacai Chen unsigned long csr_badv; 40803b0fc5SHuacai Chen unsigned long reserved[10]; 41803b0fc5SHuacai Chen } __attribute__((aligned(8))); 42803b0fc5SHuacai Chen 43803b0fc5SHuacai Chen struct user_fp_state { 44803b0fc5SHuacai Chen uint64_t fpr[32]; 45803b0fc5SHuacai Chen uint64_t fcc; 46803b0fc5SHuacai Chen uint32_t fcsr; 4761650023SHuacai Chen }; 4861650023SHuacai Chen 4961650023SHuacai Chen struct user_lsx_state { 5061650023SHuacai Chen /* 32 registers, 128 bits width per register. */ 5161650023SHuacai Chen uint64_t vregs[32*2]; 5261650023SHuacai Chen }; 5361650023SHuacai Chen 5461650023SHuacai Chen struct user_lasx_state { 5561650023SHuacai Chen /* 32 registers, 256 bits width per register. */ 5661650023SHuacai Chen uint64_t vregs[32*4]; 57803b0fc5SHuacai Chen }; 58803b0fc5SHuacai Chen 59bd3c5798SQi Hu struct user_lbt_state { 60bd3c5798SQi Hu uint64_t scr[4]; 61bd3c5798SQi Hu uint32_t eflags; 62bd3c5798SQi Hu uint32_t ftop; 63bd3c5798SQi Hu }; 64bd3c5798SQi Hu 651a69f7a1SQing Zhang struct user_watch_state { 66ff9f3d7aSQing Zhang uint64_t dbg_info; 671a69f7a1SQing Zhang struct { 681a69f7a1SQing Zhang uint64_t addr; 691a69f7a1SQing Zhang uint64_t mask; 701a69f7a1SQing Zhang uint32_t ctrl; 71ff9f3d7aSQing Zhang uint32_t pad; 721a69f7a1SQing Zhang } dbg_regs[8]; 731a69f7a1SQing Zhang }; 741a69f7a1SQing Zhang 75*cfa6d942STiezhu Yang struct user_watch_state_v2 { 76*cfa6d942STiezhu Yang uint64_t dbg_info; 77*cfa6d942STiezhu Yang struct { 78*cfa6d942STiezhu Yang uint64_t addr; 79*cfa6d942STiezhu Yang uint64_t mask; 80*cfa6d942STiezhu Yang uint32_t ctrl; 81*cfa6d942STiezhu Yang uint32_t pad; 82*cfa6d942STiezhu Yang } dbg_regs[14]; 83*cfa6d942STiezhu Yang }; 84*cfa6d942STiezhu Yang 85803b0fc5SHuacai Chen #define PTRACE_SYSEMU 0x1f 86803b0fc5SHuacai Chen #define PTRACE_SYSEMU_SINGLESTEP 0x20 87803b0fc5SHuacai Chen 88803b0fc5SHuacai Chen #endif /* _UAPI_ASM_PTRACE_H */ 89