1 #include <linux/config.h> 2 3 #include <asm/cache.h> 4 5 #include "entry.h" 6 7 /* 8 * For ivt.s we want to access the stack virtually so we don't have to disable translation 9 * on interrupts. 10 * 11 * On entry: 12 * r1: pointer to current task (ar.k6) 13 */ 14 #define MINSTATE_START_SAVE_MIN_VIRT \ 15 (pUStk) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \ 16 ;; \ 17 (pUStk) mov.m r24=ar.rnat; \ 18 (pUStk) addl r22=IA64_RBS_OFFSET,r1; /* compute base of RBS */ \ 19 (pKStk) mov r1=sp; /* get sp */ \ 20 ;; \ 21 (pUStk) lfetch.fault.excl.nt1 [r22]; \ 22 (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \ 23 (pUStk) mov r23=ar.bspstore; /* save ar.bspstore */ \ 24 ;; \ 25 (pUStk) mov ar.bspstore=r22; /* switch to kernel RBS */ \ 26 (pKStk) addl r1=-IA64_PT_REGS_SIZE,r1; /* if in kernel mode, use sp (r12) */ \ 27 ;; \ 28 (pUStk) mov r18=ar.bsp; \ 29 (pUStk) mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ 30 31 #define MINSTATE_END_SAVE_MIN_VIRT \ 32 bsw.1; /* switch back to bank 1 (must be last in insn group) */ \ 33 ;; 34 35 /* 36 * For mca_asm.S we want to access the stack physically since the state is saved before we 37 * go virtual and don't want to destroy the iip or ipsr. 38 */ 39 #define MINSTATE_START_SAVE_MIN_PHYS \ 40 (pKStk) mov r3=IA64_KR(PER_CPU_DATA);; \ 41 (pKStk) addl r3=THIS_CPU(ia64_mca_data),r3;; \ 42 (pKStk) ld8 r3 = [r3];; \ 43 (pKStk) addl r3=IA64_MCA_CPU_INIT_STACK_OFFSET,r3;; \ 44 (pKStk) addl sp=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r3; \ 45 (pUStk) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \ 46 (pUStk) addl r22=IA64_RBS_OFFSET,r1; /* compute base of register backing store */ \ 47 ;; \ 48 (pUStk) mov r24=ar.rnat; \ 49 (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \ 50 (pUStk) mov r23=ar.bspstore; /* save ar.bspstore */ \ 51 (pUStk) dep r22=-1,r22,61,3; /* compute kernel virtual addr of RBS */ \ 52 ;; \ 53 (pKStk) addl r1=-IA64_PT_REGS_SIZE,r1; /* if in kernel mode, use sp (r12) */ \ 54 (pUStk) mov ar.bspstore=r22; /* switch to kernel RBS */ \ 55 ;; \ 56 (pUStk) mov r18=ar.bsp; \ 57 (pUStk) mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ \ 58 59 #define MINSTATE_END_SAVE_MIN_PHYS \ 60 dep r12=-1,r12,61,3; /* make sp a kernel virtual address */ \ 61 ;; 62 63 #ifdef MINSTATE_VIRT 64 # define MINSTATE_GET_CURRENT(reg) mov reg=IA64_KR(CURRENT) 65 # define MINSTATE_START_SAVE_MIN MINSTATE_START_SAVE_MIN_VIRT 66 # define MINSTATE_END_SAVE_MIN MINSTATE_END_SAVE_MIN_VIRT 67 #endif 68 69 #ifdef MINSTATE_PHYS 70 # define MINSTATE_GET_CURRENT(reg) mov reg=IA64_KR(CURRENT);; tpa reg=reg 71 # define MINSTATE_START_SAVE_MIN MINSTATE_START_SAVE_MIN_PHYS 72 # define MINSTATE_END_SAVE_MIN MINSTATE_END_SAVE_MIN_PHYS 73 #endif 74 75 /* 76 * DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves 77 * the minimum state necessary that allows us to turn psr.ic back 78 * on. 79 * 80 * Assumed state upon entry: 81 * psr.ic: off 82 * r31: contains saved predicates (pr) 83 * 84 * Upon exit, the state is as follows: 85 * psr.ic: off 86 * r2 = points to &pt_regs.r16 87 * r8 = contents of ar.ccv 88 * r9 = contents of ar.csd 89 * r10 = contents of ar.ssd 90 * r11 = FPSR_DEFAULT 91 * r12 = kernel sp (kernel virtual address) 92 * r13 = points to current task_struct (kernel virtual address) 93 * p15 = TRUE if psr.i is set in cr.ipsr 94 * predicate registers (other than p2, p3, and p15), b6, r3, r14, r15: 95 * preserved 96 * 97 * Note that psr.ic is NOT turned on by this macro. This is so that 98 * we can pass interruption state as arguments to a handler. 99 */ 100 #define DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA) \ 101 MINSTATE_GET_CURRENT(r16); /* M (or M;;I) */ \ 102 mov r27=ar.rsc; /* M */ \ 103 mov r20=r1; /* A */ \ 104 mov r25=ar.unat; /* M */ \ 105 mov r29=cr.ipsr; /* M */ \ 106 mov r26=ar.pfs; /* I */ \ 107 mov r28=cr.iip; /* M */ \ 108 mov r21=ar.fpsr; /* M */ \ 109 COVER; /* B;; (or nothing) */ \ 110 ;; \ 111 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16; \ 112 ;; \ 113 ld1 r17=[r16]; /* load current->thread.on_ustack flag */ \ 114 st1 [r16]=r0; /* clear current->thread.on_ustack flag */ \ 115 adds r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 \ 116 /* switch from user to kernel RBS: */ \ 117 ;; \ 118 invala; /* M */ \ 119 SAVE_IFS; \ 120 cmp.eq pKStk,pUStk=r0,r17; /* are we in kernel mode already? */ \ 121 ;; \ 122 MINSTATE_START_SAVE_MIN \ 123 adds r17=2*L1_CACHE_BYTES,r1; /* really: biggest cache-line size */ \ 124 adds r16=PT(CR_IPSR),r1; \ 125 ;; \ 126 lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES; \ 127 st8 [r16]=r29; /* save cr.ipsr */ \ 128 ;; \ 129 lfetch.fault.excl.nt1 [r17]; \ 130 tbit.nz p15,p0=r29,IA64_PSR_I_BIT; \ 131 mov r29=b0 \ 132 ;; \ 133 adds r16=PT(R8),r1; /* initialize first base pointer */ \ 134 adds r17=PT(R9),r1; /* initialize second base pointer */ \ 135 (pKStk) mov r18=r0; /* make sure r18 isn't NaT */ \ 136 ;; \ 137 .mem.offset 0,0; st8.spill [r16]=r8,16; \ 138 .mem.offset 8,0; st8.spill [r17]=r9,16; \ 139 ;; \ 140 .mem.offset 0,0; st8.spill [r16]=r10,24; \ 141 .mem.offset 8,0; st8.spill [r17]=r11,24; \ 142 ;; \ 143 st8 [r16]=r28,16; /* save cr.iip */ \ 144 st8 [r17]=r30,16; /* save cr.ifs */ \ 145 (pUStk) sub r18=r18,r22; /* r18=RSE.ndirty*8 */ \ 146 mov r8=ar.ccv; \ 147 mov r9=ar.csd; \ 148 mov r10=ar.ssd; \ 149 movl r11=FPSR_DEFAULT; /* L-unit */ \ 150 ;; \ 151 st8 [r16]=r25,16; /* save ar.unat */ \ 152 st8 [r17]=r26,16; /* save ar.pfs */ \ 153 shl r18=r18,16; /* compute ar.rsc to be used for "loadrs" */ \ 154 ;; \ 155 st8 [r16]=r27,16; /* save ar.rsc */ \ 156 (pUStk) st8 [r17]=r24,16; /* save ar.rnat */ \ 157 (pKStk) adds r17=16,r17; /* skip over ar_rnat field */ \ 158 ;; /* avoid RAW on r16 & r17 */ \ 159 (pUStk) st8 [r16]=r23,16; /* save ar.bspstore */ \ 160 st8 [r17]=r31,16; /* save predicates */ \ 161 (pKStk) adds r16=16,r16; /* skip over ar_bspstore field */ \ 162 ;; \ 163 st8 [r16]=r29,16; /* save b0 */ \ 164 st8 [r17]=r18,16; /* save ar.rsc value for "loadrs" */ \ 165 cmp.eq pNonSys,pSys=r0,r0 /* initialize pSys=0, pNonSys=1 */ \ 166 ;; \ 167 .mem.offset 0,0; st8.spill [r16]=r20,16; /* save original r1 */ \ 168 .mem.offset 8,0; st8.spill [r17]=r12,16; \ 169 adds r12=-16,r1; /* switch to kernel memory stack (with 16 bytes of scratch) */ \ 170 ;; \ 171 .mem.offset 0,0; st8.spill [r16]=r13,16; \ 172 .mem.offset 8,0; st8.spill [r17]=r21,16; /* save ar.fpsr */ \ 173 mov r13=IA64_KR(CURRENT); /* establish `current' */ \ 174 ;; \ 175 .mem.offset 0,0; st8.spill [r16]=r15,16; \ 176 .mem.offset 8,0; st8.spill [r17]=r14,16; \ 177 ;; \ 178 .mem.offset 0,0; st8.spill [r16]=r2,16; \ 179 .mem.offset 8,0; st8.spill [r17]=r3,16; \ 180 adds r2=IA64_PT_REGS_R16_OFFSET,r1; \ 181 ;; \ 182 EXTRA; \ 183 movl r1=__gp; /* establish kernel global pointer */ \ 184 ;; \ 185 MINSTATE_END_SAVE_MIN 186 187 /* 188 * SAVE_REST saves the remainder of pt_regs (with psr.ic on). 189 * 190 * Assumed state upon entry: 191 * psr.ic: on 192 * r2: points to &pt_regs.r16 193 * r3: points to &pt_regs.r17 194 * r8: contents of ar.ccv 195 * r9: contents of ar.csd 196 * r10: contents of ar.ssd 197 * r11: FPSR_DEFAULT 198 * 199 * Registers r14 and r15 are guaranteed not to be touched by SAVE_REST. 200 */ 201 #define SAVE_REST \ 202 .mem.offset 0,0; st8.spill [r2]=r16,16; \ 203 .mem.offset 8,0; st8.spill [r3]=r17,16; \ 204 ;; \ 205 .mem.offset 0,0; st8.spill [r2]=r18,16; \ 206 .mem.offset 8,0; st8.spill [r3]=r19,16; \ 207 ;; \ 208 .mem.offset 0,0; st8.spill [r2]=r20,16; \ 209 .mem.offset 8,0; st8.spill [r3]=r21,16; \ 210 mov r18=b6; \ 211 ;; \ 212 .mem.offset 0,0; st8.spill [r2]=r22,16; \ 213 .mem.offset 8,0; st8.spill [r3]=r23,16; \ 214 mov r19=b7; \ 215 ;; \ 216 .mem.offset 0,0; st8.spill [r2]=r24,16; \ 217 .mem.offset 8,0; st8.spill [r3]=r25,16; \ 218 ;; \ 219 .mem.offset 0,0; st8.spill [r2]=r26,16; \ 220 .mem.offset 8,0; st8.spill [r3]=r27,16; \ 221 ;; \ 222 .mem.offset 0,0; st8.spill [r2]=r28,16; \ 223 .mem.offset 8,0; st8.spill [r3]=r29,16; \ 224 ;; \ 225 .mem.offset 0,0; st8.spill [r2]=r30,16; \ 226 .mem.offset 8,0; st8.spill [r3]=r31,32; \ 227 ;; \ 228 mov ar.fpsr=r11; /* M-unit */ \ 229 st8 [r2]=r8,8; /* ar.ccv */ \ 230 adds r24=PT(B6)-PT(F7),r3; \ 231 ;; \ 232 stf.spill [r2]=f6,32; \ 233 stf.spill [r3]=f7,32; \ 234 ;; \ 235 stf.spill [r2]=f8,32; \ 236 stf.spill [r3]=f9,32; \ 237 ;; \ 238 stf.spill [r2]=f10; \ 239 stf.spill [r3]=f11; \ 240 adds r25=PT(B7)-PT(F11),r3; \ 241 ;; \ 242 st8 [r24]=r18,16; /* b6 */ \ 243 st8 [r25]=r19,16; /* b7 */ \ 244 ;; \ 245 st8 [r24]=r9; /* ar.csd */ \ 246 st8 [r25]=r10; /* ar.ssd */ \ 247 ;; 248 249 #define SAVE_MIN_WITH_COVER DO_SAVE_MIN(cover, mov r30=cr.ifs,) 250 #define SAVE_MIN_WITH_COVER_R19 DO_SAVE_MIN(cover, mov r30=cr.ifs, mov r15=r19) 251 #define SAVE_MIN DO_SAVE_MIN( , mov r30=r0, ) 252