xref: /openbmc/linux/arch/ia64/kernel/mca.c (revision d5cb9783536a41df9f9cba5b0a1d78047ed787f7)
1 /*
2  * File:	mca.c
3  * Purpose:	Generic MCA handling layer
4  *
5  * Updated for latest kernel
6  * Copyright (C) 2003 Hewlett-Packard Co
7  *	David Mosberger-Tang <davidm@hpl.hp.com>
8  *
9  * Copyright (C) 2002 Dell Inc.
10  * Copyright (C) Matt Domsch (Matt_Domsch@dell.com)
11  *
12  * Copyright (C) 2002 Intel
13  * Copyright (C) Jenna Hall (jenna.s.hall@intel.com)
14  *
15  * Copyright (C) 2001 Intel
16  * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com)
17  *
18  * Copyright (C) 2000 Intel
19  * Copyright (C) Chuck Fleckenstein (cfleck@co.intel.com)
20  *
21  * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
22  * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
23  *
24  * 03/04/15 D. Mosberger Added INIT backtrace support.
25  * 02/03/25 M. Domsch	GUID cleanups
26  *
27  * 02/01/04 J. Hall	Aligned MCA stack to 16 bytes, added platform vs. CPU
28  *			error flag, set SAL default return values, changed
29  *			error record structure to linked list, added init call
30  *			to sal_get_state_info_size().
31  *
32  * 01/01/03 F. Lewis    Added setup of CMCI and CPEI IRQs, logging of corrected
33  *                      platform errors, completed code for logging of
34  *                      corrected & uncorrected machine check errors, and
35  *                      updated for conformance with Nov. 2000 revision of the
36  *                      SAL 3.0 spec.
37  * 00/03/29 C. Fleckenstein  Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
38  *                           added min save state dump, added INIT handler.
39  *
40  * 2003-12-08 Keith Owens <kaos@sgi.com>
41  *            smp_call_function() must not be called from interrupt context (can
42  *            deadlock on tasklist_lock).  Use keventd to call smp_call_function().
43  *
44  * 2004-02-01 Keith Owens <kaos@sgi.com>
45  *            Avoid deadlock when using printk() for MCA and INIT records.
46  *            Delete all record printing code, moved to salinfo_decode in user space.
47  *            Mark variables and functions static where possible.
48  *            Delete dead variables and functions.
49  *            Reorder to remove the need for forward declarations and to consolidate
50  *            related code.
51  *
52  * 2005-08-12 Keith Owens <kaos@sgi.com>
53  *	      Convert MCA/INIT handlers to use per event stacks and SAL/OS state.
54  */
55 #include <linux/config.h>
56 #include <linux/types.h>
57 #include <linux/init.h>
58 #include <linux/sched.h>
59 #include <linux/interrupt.h>
60 #include <linux/irq.h>
61 #include <linux/kallsyms.h>
62 #include <linux/smp_lock.h>
63 #include <linux/bootmem.h>
64 #include <linux/acpi.h>
65 #include <linux/timer.h>
66 #include <linux/module.h>
67 #include <linux/kernel.h>
68 #include <linux/smp.h>
69 #include <linux/workqueue.h>
70 
71 #include <asm/delay.h>
72 #include <asm/machvec.h>
73 #include <asm/meminit.h>
74 #include <asm/page.h>
75 #include <asm/ptrace.h>
76 #include <asm/system.h>
77 #include <asm/sal.h>
78 #include <asm/mca.h>
79 
80 #include <asm/irq.h>
81 #include <asm/hw_irq.h>
82 
83 #include "entry.h"
84 
85 #if defined(IA64_MCA_DEBUG_INFO)
86 # define IA64_MCA_DEBUG(fmt...)	printk(fmt)
87 #else
88 # define IA64_MCA_DEBUG(fmt...)
89 #endif
90 
91 /* Used by mca_asm.S */
92 u32				ia64_mca_serialize;
93 DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
94 DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
95 DEFINE_PER_CPU(u64, ia64_mca_pal_pte);	    /* PTE to map PAL code */
96 DEFINE_PER_CPU(u64, ia64_mca_pal_base);    /* vaddr PAL code granule */
97 
98 unsigned long __per_cpu_mca[NR_CPUS];
99 
100 /* In mca_asm.S */
101 extern void			ia64_os_init_dispatch_monarch (void);
102 extern void			ia64_os_init_dispatch_slave (void);
103 
104 static int monarch_cpu = -1;
105 
106 static ia64_mc_info_t		ia64_mc_info;
107 
108 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
109 #define MIN_CPE_POLL_INTERVAL (2*60*HZ)  /* 2 minutes */
110 #define CMC_POLL_INTERVAL     (1*60*HZ)  /* 1 minute */
111 #define CPE_HISTORY_LENGTH    5
112 #define CMC_HISTORY_LENGTH    5
113 
114 static struct timer_list cpe_poll_timer;
115 static struct timer_list cmc_poll_timer;
116 /*
117  * This variable tells whether we are currently in polling mode.
118  * Start with this in the wrong state so we won't play w/ timers
119  * before the system is ready.
120  */
121 static int cmc_polling_enabled = 1;
122 
123 /*
124  * Clearing this variable prevents CPE polling from getting activated
125  * in mca_late_init.  Use it if your system doesn't provide a CPEI,
126  * but encounters problems retrieving CPE logs.  This should only be
127  * necessary for debugging.
128  */
129 static int cpe_poll_enabled = 1;
130 
131 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
132 
133 static int mca_init;
134 
135 /*
136  * IA64_MCA log support
137  */
138 #define IA64_MAX_LOGS		2	/* Double-buffering for nested MCAs */
139 #define IA64_MAX_LOG_TYPES      4   /* MCA, INIT, CMC, CPE */
140 
141 typedef struct ia64_state_log_s
142 {
143 	spinlock_t	isl_lock;
144 	int		isl_index;
145 	unsigned long	isl_count;
146 	ia64_err_rec_t  *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
147 } ia64_state_log_t;
148 
149 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
150 
151 #define IA64_LOG_ALLOCATE(it, size) \
152 	{ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
153 		(ia64_err_rec_t *)alloc_bootmem(size); \
154 	ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
155 		(ia64_err_rec_t *)alloc_bootmem(size);}
156 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
157 #define IA64_LOG_LOCK(it)      spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
158 #define IA64_LOG_UNLOCK(it)    spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
159 #define IA64_LOG_NEXT_INDEX(it)    ia64_state_log[it].isl_index
160 #define IA64_LOG_CURR_INDEX(it)    1 - ia64_state_log[it].isl_index
161 #define IA64_LOG_INDEX_INC(it) \
162     {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
163     ia64_state_log[it].isl_count++;}
164 #define IA64_LOG_INDEX_DEC(it) \
165     ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
166 #define IA64_LOG_NEXT_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
167 #define IA64_LOG_CURR_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
168 #define IA64_LOG_COUNT(it)         ia64_state_log[it].isl_count
169 
170 /*
171  * ia64_log_init
172  *	Reset the OS ia64 log buffer
173  * Inputs   :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
174  * Outputs	:	None
175  */
176 static void
177 ia64_log_init(int sal_info_type)
178 {
179 	u64	max_size = 0;
180 
181 	IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
182 	IA64_LOG_LOCK_INIT(sal_info_type);
183 
184 	// SAL will tell us the maximum size of any error record of this type
185 	max_size = ia64_sal_get_state_info_size(sal_info_type);
186 	if (!max_size)
187 		/* alloc_bootmem() doesn't like zero-sized allocations! */
188 		return;
189 
190 	// set up OS data structures to hold error info
191 	IA64_LOG_ALLOCATE(sal_info_type, max_size);
192 	memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
193 	memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
194 }
195 
196 /*
197  * ia64_log_get
198  *
199  *	Get the current MCA log from SAL and copy it into the OS log buffer.
200  *
201  *  Inputs  :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
202  *              irq_safe    whether you can use printk at this point
203  *  Outputs :   size        (total record length)
204  *              *buffer     (ptr to error record)
205  *
206  */
207 static u64
208 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
209 {
210 	sal_log_record_header_t     *log_buffer;
211 	u64                         total_len = 0;
212 	int                         s;
213 
214 	IA64_LOG_LOCK(sal_info_type);
215 
216 	/* Get the process state information */
217 	log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
218 
219 	total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
220 
221 	if (total_len) {
222 		IA64_LOG_INDEX_INC(sal_info_type);
223 		IA64_LOG_UNLOCK(sal_info_type);
224 		if (irq_safe) {
225 			IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. "
226 				       "Record length = %ld\n", __FUNCTION__, sal_info_type, total_len);
227 		}
228 		*buffer = (u8 *) log_buffer;
229 		return total_len;
230 	} else {
231 		IA64_LOG_UNLOCK(sal_info_type);
232 		return 0;
233 	}
234 }
235 
236 /*
237  *  ia64_mca_log_sal_error_record
238  *
239  *  This function retrieves a specified error record type from SAL
240  *  and wakes up any processes waiting for error records.
241  *
242  *  Inputs  :   sal_info_type   (Type of error record MCA/CMC/CPE)
243  *              FIXME: remove MCA and irq_safe.
244  */
245 static void
246 ia64_mca_log_sal_error_record(int sal_info_type)
247 {
248 	u8 *buffer;
249 	sal_log_record_header_t *rh;
250 	u64 size;
251 	int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA;
252 #ifdef IA64_MCA_DEBUG_INFO
253 	static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
254 #endif
255 
256 	size = ia64_log_get(sal_info_type, &buffer, irq_safe);
257 	if (!size)
258 		return;
259 
260 	salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
261 
262 	if (irq_safe)
263 		IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
264 			smp_processor_id(),
265 			sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
266 
267 	/* Clear logs from corrected errors in case there's no user-level logger */
268 	rh = (sal_log_record_header_t *)buffer;
269 	if (rh->severity == sal_log_severity_corrected)
270 		ia64_sal_clear_state_info(sal_info_type);
271 }
272 
273 /*
274  * platform dependent error handling
275  */
276 #ifndef PLATFORM_MCA_HANDLERS
277 
278 #ifdef CONFIG_ACPI
279 
280 int cpe_vector = -1;
281 
282 static irqreturn_t
283 ia64_mca_cpe_int_handler (int cpe_irq, void *arg, struct pt_regs *ptregs)
284 {
285 	static unsigned long	cpe_history[CPE_HISTORY_LENGTH];
286 	static int		index;
287 	static DEFINE_SPINLOCK(cpe_history_lock);
288 
289 	IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
290 		       __FUNCTION__, cpe_irq, smp_processor_id());
291 
292 	/* SAL spec states this should run w/ interrupts enabled */
293 	local_irq_enable();
294 
295 	/* Get the CPE error record and log it */
296 	ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
297 
298 	spin_lock(&cpe_history_lock);
299 	if (!cpe_poll_enabled && cpe_vector >= 0) {
300 
301 		int i, count = 1; /* we know 1 happened now */
302 		unsigned long now = jiffies;
303 
304 		for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
305 			if (now - cpe_history[i] <= HZ)
306 				count++;
307 		}
308 
309 		IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
310 		if (count >= CPE_HISTORY_LENGTH) {
311 
312 			cpe_poll_enabled = 1;
313 			spin_unlock(&cpe_history_lock);
314 			disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
315 
316 			/*
317 			 * Corrected errors will still be corrected, but
318 			 * make sure there's a log somewhere that indicates
319 			 * something is generating more than we can handle.
320 			 */
321 			printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
322 
323 			mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
324 
325 			/* lock already released, get out now */
326 			return IRQ_HANDLED;
327 		} else {
328 			cpe_history[index++] = now;
329 			if (index == CPE_HISTORY_LENGTH)
330 				index = 0;
331 		}
332 	}
333 	spin_unlock(&cpe_history_lock);
334 	return IRQ_HANDLED;
335 }
336 
337 #endif /* CONFIG_ACPI */
338 
339 #ifdef CONFIG_ACPI
340 /*
341  * ia64_mca_register_cpev
342  *
343  *  Register the corrected platform error vector with SAL.
344  *
345  *  Inputs
346  *      cpev        Corrected Platform Error Vector number
347  *
348  *  Outputs
349  *      None
350  */
351 static void
352 ia64_mca_register_cpev (int cpev)
353 {
354 	/* Register the CPE interrupt vector with SAL */
355 	struct ia64_sal_retval isrv;
356 
357 	isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
358 	if (isrv.status) {
359 		printk(KERN_ERR "Failed to register Corrected Platform "
360 		       "Error interrupt vector with SAL (status %ld)\n", isrv.status);
361 		return;
362 	}
363 
364 	IA64_MCA_DEBUG("%s: corrected platform error "
365 		       "vector %#x registered\n", __FUNCTION__, cpev);
366 }
367 #endif /* CONFIG_ACPI */
368 
369 #endif /* PLATFORM_MCA_HANDLERS */
370 
371 /*
372  * ia64_mca_cmc_vector_setup
373  *
374  *  Setup the corrected machine check vector register in the processor.
375  *  (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
376  *  This function is invoked on a per-processor basis.
377  *
378  * Inputs
379  *      None
380  *
381  * Outputs
382  *	None
383  */
384 void
385 ia64_mca_cmc_vector_setup (void)
386 {
387 	cmcv_reg_t	cmcv;
388 
389 	cmcv.cmcv_regval	= 0;
390 	cmcv.cmcv_mask		= 1;        /* Mask/disable interrupt at first */
391 	cmcv.cmcv_vector	= IA64_CMC_VECTOR;
392 	ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
393 
394 	IA64_MCA_DEBUG("%s: CPU %d corrected "
395 		       "machine check vector %#x registered.\n",
396 		       __FUNCTION__, smp_processor_id(), IA64_CMC_VECTOR);
397 
398 	IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
399 		       __FUNCTION__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
400 }
401 
402 /*
403  * ia64_mca_cmc_vector_disable
404  *
405  *  Mask the corrected machine check vector register in the processor.
406  *  This function is invoked on a per-processor basis.
407  *
408  * Inputs
409  *      dummy(unused)
410  *
411  * Outputs
412  *	None
413  */
414 static void
415 ia64_mca_cmc_vector_disable (void *dummy)
416 {
417 	cmcv_reg_t	cmcv;
418 
419 	cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
420 
421 	cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
422 	ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
423 
424 	IA64_MCA_DEBUG("%s: CPU %d corrected "
425 		       "machine check vector %#x disabled.\n",
426 		       __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
427 }
428 
429 /*
430  * ia64_mca_cmc_vector_enable
431  *
432  *  Unmask the corrected machine check vector register in the processor.
433  *  This function is invoked on a per-processor basis.
434  *
435  * Inputs
436  *      dummy(unused)
437  *
438  * Outputs
439  *	None
440  */
441 static void
442 ia64_mca_cmc_vector_enable (void *dummy)
443 {
444 	cmcv_reg_t	cmcv;
445 
446 	cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
447 
448 	cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
449 	ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
450 
451 	IA64_MCA_DEBUG("%s: CPU %d corrected "
452 		       "machine check vector %#x enabled.\n",
453 		       __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
454 }
455 
456 /*
457  * ia64_mca_cmc_vector_disable_keventd
458  *
459  * Called via keventd (smp_call_function() is not safe in interrupt context) to
460  * disable the cmc interrupt vector.
461  */
462 static void
463 ia64_mca_cmc_vector_disable_keventd(void *unused)
464 {
465 	on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 1, 0);
466 }
467 
468 /*
469  * ia64_mca_cmc_vector_enable_keventd
470  *
471  * Called via keventd (smp_call_function() is not safe in interrupt context) to
472  * enable the cmc interrupt vector.
473  */
474 static void
475 ia64_mca_cmc_vector_enable_keventd(void *unused)
476 {
477 	on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 1, 0);
478 }
479 
480 /*
481  * ia64_mca_wakeup
482  *
483  *	Send an inter-cpu interrupt to wake-up a particular cpu
484  *	and mark that cpu to be out of rendez.
485  *
486  *  Inputs  :   cpuid
487  *  Outputs :   None
488  */
489 static void
490 ia64_mca_wakeup(int cpu)
491 {
492 	platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
493 	ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
494 
495 }
496 
497 /*
498  * ia64_mca_wakeup_all
499  *
500  *	Wakeup all the cpus which have rendez'ed previously.
501  *
502  *  Inputs  :   None
503  *  Outputs :   None
504  */
505 static void
506 ia64_mca_wakeup_all(void)
507 {
508 	int cpu;
509 
510 	/* Clear the Rendez checkin flag for all cpus */
511 	for_each_online_cpu(cpu) {
512 		if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
513 			ia64_mca_wakeup(cpu);
514 	}
515 
516 }
517 
518 /*
519  * ia64_mca_rendez_interrupt_handler
520  *
521  *	This is handler used to put slave processors into spinloop
522  *	while the monarch processor does the mca handling and later
523  *	wake each slave up once the monarch is done.
524  *
525  *  Inputs  :   None
526  *  Outputs :   None
527  */
528 static irqreturn_t
529 ia64_mca_rendez_int_handler(int rendez_irq, void *arg, struct pt_regs *ptregs)
530 {
531 	unsigned long flags;
532 	int cpu = smp_processor_id();
533 
534 	/* Mask all interrupts */
535 	local_irq_save(flags);
536 
537 	ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
538 	/* Register with the SAL monarch that the slave has
539 	 * reached SAL
540 	 */
541 	ia64_sal_mc_rendez();
542 
543 	/* Wait for the monarch cpu to exit. */
544 	while (monarch_cpu != -1)
545 	       cpu_relax();	/* spin until monarch leaves */
546 
547 	/* Enable all interrupts */
548 	local_irq_restore(flags);
549 	return IRQ_HANDLED;
550 }
551 
552 /*
553  * ia64_mca_wakeup_int_handler
554  *
555  *	The interrupt handler for processing the inter-cpu interrupt to the
556  *	slave cpu which was spinning in the rendez loop.
557  *	Since this spinning is done by turning off the interrupts and
558  *	polling on the wakeup-interrupt bit in the IRR, there is
559  *	nothing useful to be done in the handler.
560  *
561  *  Inputs  :   wakeup_irq  (Wakeup-interrupt bit)
562  *	arg		(Interrupt handler specific argument)
563  *	ptregs		(Exception frame at the time of the interrupt)
564  *  Outputs :   None
565  *
566  */
567 static irqreturn_t
568 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg, struct pt_regs *ptregs)
569 {
570 	return IRQ_HANDLED;
571 }
572 
573 /* Function pointer for extra MCA recovery */
574 int (*ia64_mca_ucmc_extension)
575 	(void*,struct ia64_sal_os_state*)
576 	= NULL;
577 
578 int
579 ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *))
580 {
581 	if (ia64_mca_ucmc_extension)
582 		return 1;
583 
584 	ia64_mca_ucmc_extension = fn;
585 	return 0;
586 }
587 
588 void
589 ia64_unreg_MCA_extension(void)
590 {
591 	if (ia64_mca_ucmc_extension)
592 		ia64_mca_ucmc_extension = NULL;
593 }
594 
595 EXPORT_SYMBOL(ia64_reg_MCA_extension);
596 EXPORT_SYMBOL(ia64_unreg_MCA_extension);
597 
598 
599 static inline void
600 copy_reg(const u64 *fr, u64 fnat, u64 *tr, u64 *tnat)
601 {
602 	u64 fslot, tslot, nat;
603 	*tr = *fr;
604 	fslot = ((unsigned long)fr >> 3) & 63;
605 	tslot = ((unsigned long)tr >> 3) & 63;
606 	*tnat &= ~(1UL << tslot);
607 	nat = (fnat >> fslot) & 1;
608 	*tnat |= (nat << tslot);
609 }
610 
611 /* On entry to this routine, we are running on the per cpu stack, see
612  * mca_asm.h.  The original stack has not been touched by this event.  Some of
613  * the original stack's registers will be in the RBS on this stack.  This stack
614  * also contains a partial pt_regs and switch_stack, the rest of the data is in
615  * PAL minstate.
616  *
617  * The first thing to do is modify the original stack to look like a blocked
618  * task so we can run backtrace on the original task.  Also mark the per cpu
619  * stack as current to ensure that we use the correct task state, it also means
620  * that we can do backtrace on the MCA/INIT handler code itself.
621  */
622 
623 static task_t *
624 ia64_mca_modify_original_stack(struct pt_regs *regs,
625 		const struct switch_stack *sw,
626 		struct ia64_sal_os_state *sos,
627 		const char *type)
628 {
629 	char *p, comm[sizeof(current->comm)];
630 	ia64_va va;
631 	extern char ia64_leave_kernel[];	/* Need asm address, not function descriptor */
632 	const pal_min_state_area_t *ms = sos->pal_min_state;
633 	task_t *previous_current;
634 	struct pt_regs *old_regs;
635 	struct switch_stack *old_sw;
636 	unsigned size = sizeof(struct pt_regs) +
637 			sizeof(struct switch_stack) + 16;
638 	u64 *old_bspstore, *old_bsp;
639 	u64 *new_bspstore, *new_bsp;
640 	u64 old_unat, old_rnat, new_rnat, nat;
641 	u64 slots, loadrs = regs->loadrs;
642 	u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1];
643 	u64 ar_bspstore = regs->ar_bspstore;
644 	u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16);
645 	const u64 *bank;
646 	const char *msg;
647 	int cpu = smp_processor_id();
648 
649 	previous_current = curr_task(cpu);
650 	set_curr_task(cpu, current);
651 	if ((p = strchr(current->comm, ' ')))
652 		*p = '\0';
653 
654 	/* Best effort attempt to cope with MCA/INIT delivered while in
655 	 * physical mode.
656 	 */
657 	regs->cr_ipsr = ms->pmsa_ipsr;
658 	if (ia64_psr(regs)->dt == 0) {
659 		va.l = r12;
660 		if (va.f.reg == 0) {
661 			va.f.reg = 7;
662 			r12 = va.l;
663 		}
664 		va.l = r13;
665 		if (va.f.reg == 0) {
666 			va.f.reg = 7;
667 			r13 = va.l;
668 		}
669 	}
670 	if (ia64_psr(regs)->rt == 0) {
671 		va.l = ar_bspstore;
672 		if (va.f.reg == 0) {
673 			va.f.reg = 7;
674 			ar_bspstore = va.l;
675 		}
676 		va.l = ar_bsp;
677 		if (va.f.reg == 0) {
678 			va.f.reg = 7;
679 			ar_bsp = va.l;
680 		}
681 	}
682 
683 	/* mca_asm.S ia64_old_stack() cannot assume that the dirty registers
684 	 * have been copied to the old stack, the old stack may fail the
685 	 * validation tests below.  So ia64_old_stack() must restore the dirty
686 	 * registers from the new stack.  The old and new bspstore probably
687 	 * have different alignments, so loadrs calculated on the old bsp
688 	 * cannot be used to restore from the new bsp.  Calculate a suitable
689 	 * loadrs for the new stack and save it in the new pt_regs, where
690 	 * ia64_old_stack() can get it.
691 	 */
692 	old_bspstore = (u64 *)ar_bspstore;
693 	old_bsp = (u64 *)ar_bsp;
694 	slots = ia64_rse_num_regs(old_bspstore, old_bsp);
695 	new_bspstore = (u64 *)((u64)current + IA64_RBS_OFFSET);
696 	new_bsp = ia64_rse_skip_regs(new_bspstore, slots);
697 	regs->loadrs = (new_bsp - new_bspstore) * 8 << 16;
698 
699 	/* Verify the previous stack state before we change it */
700 	if (user_mode(regs)) {
701 		msg = "occurred in user space";
702 		goto no_mod;
703 	}
704 	if (r13 != sos->prev_IA64_KR_CURRENT) {
705 		msg = "inconsistent previous current and r13";
706 		goto no_mod;
707 	}
708 	if ((r12 - r13) >= KERNEL_STACK_SIZE) {
709 		msg = "inconsistent r12 and r13";
710 		goto no_mod;
711 	}
712 	if ((ar_bspstore - r13) >= KERNEL_STACK_SIZE) {
713 		msg = "inconsistent ar.bspstore and r13";
714 		goto no_mod;
715 	}
716 	va.p = old_bspstore;
717 	if (va.f.reg < 5) {
718 		msg = "old_bspstore is in the wrong region";
719 		goto no_mod;
720 	}
721 	if ((ar_bsp - r13) >= KERNEL_STACK_SIZE) {
722 		msg = "inconsistent ar.bsp and r13";
723 		goto no_mod;
724 	}
725 	size += (ia64_rse_skip_regs(old_bspstore, slots) - old_bspstore) * 8;
726 	if (ar_bspstore + size > r12) {
727 		msg = "no room for blocked state";
728 		goto no_mod;
729 	}
730 
731 	/* Change the comm field on the MCA/INT task to include the pid that
732 	 * was interrupted, it makes for easier debugging.  If that pid was 0
733 	 * (swapper or nested MCA/INIT) then use the start of the previous comm
734 	 * field suffixed with its cpu.
735 	 */
736 	if (previous_current->pid)
737 		snprintf(comm, sizeof(comm), "%s %d",
738 			current->comm, previous_current->pid);
739 	else {
740 		int l;
741 		if ((p = strchr(previous_current->comm, ' ')))
742 			l = p - previous_current->comm;
743 		else
744 			l = strlen(previous_current->comm);
745 		snprintf(comm, sizeof(comm), "%s %*s %d",
746 			current->comm, l, previous_current->comm,
747 			previous_current->thread_info->cpu);
748 	}
749 	memcpy(current->comm, comm, sizeof(current->comm));
750 
751 	/* Make the original task look blocked.  First stack a struct pt_regs,
752 	 * describing the state at the time of interrupt.  mca_asm.S built a
753 	 * partial pt_regs, copy it and fill in the blanks using minstate.
754 	 */
755 	p = (char *)r12 - sizeof(*regs);
756 	old_regs = (struct pt_regs *)p;
757 	memcpy(old_regs, regs, sizeof(*regs));
758 	/* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
759 	 * pmsa_{xip,xpsr,xfs}
760 	 */
761 	if (ia64_psr(regs)->ic) {
762 		old_regs->cr_iip = ms->pmsa_iip;
763 		old_regs->cr_ipsr = ms->pmsa_ipsr;
764 		old_regs->cr_ifs = ms->pmsa_ifs;
765 	} else {
766 		old_regs->cr_iip = ms->pmsa_xip;
767 		old_regs->cr_ipsr = ms->pmsa_xpsr;
768 		old_regs->cr_ifs = ms->pmsa_xfs;
769 	}
770 	old_regs->pr = ms->pmsa_pr;
771 	old_regs->b0 = ms->pmsa_br0;
772 	old_regs->loadrs = loadrs;
773 	old_regs->ar_rsc = ms->pmsa_rsc;
774 	old_unat = old_regs->ar_unat;
775 	copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, &old_regs->r1, &old_unat);
776 	copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, &old_regs->r2, &old_unat);
777 	copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, &old_regs->r3, &old_unat);
778 	copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, &old_regs->r8, &old_unat);
779 	copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, &old_regs->r9, &old_unat);
780 	copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, &old_regs->r10, &old_unat);
781 	copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, &old_regs->r11, &old_unat);
782 	copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, &old_regs->r12, &old_unat);
783 	copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, &old_regs->r13, &old_unat);
784 	copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, &old_regs->r14, &old_unat);
785 	copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, &old_regs->r15, &old_unat);
786 	if (ia64_psr(old_regs)->bn)
787 		bank = ms->pmsa_bank1_gr;
788 	else
789 		bank = ms->pmsa_bank0_gr;
790 	copy_reg(&bank[16-16], ms->pmsa_nat_bits, &old_regs->r16, &old_unat);
791 	copy_reg(&bank[17-16], ms->pmsa_nat_bits, &old_regs->r17, &old_unat);
792 	copy_reg(&bank[18-16], ms->pmsa_nat_bits, &old_regs->r18, &old_unat);
793 	copy_reg(&bank[19-16], ms->pmsa_nat_bits, &old_regs->r19, &old_unat);
794 	copy_reg(&bank[20-16], ms->pmsa_nat_bits, &old_regs->r20, &old_unat);
795 	copy_reg(&bank[21-16], ms->pmsa_nat_bits, &old_regs->r21, &old_unat);
796 	copy_reg(&bank[22-16], ms->pmsa_nat_bits, &old_regs->r22, &old_unat);
797 	copy_reg(&bank[23-16], ms->pmsa_nat_bits, &old_regs->r23, &old_unat);
798 	copy_reg(&bank[24-16], ms->pmsa_nat_bits, &old_regs->r24, &old_unat);
799 	copy_reg(&bank[25-16], ms->pmsa_nat_bits, &old_regs->r25, &old_unat);
800 	copy_reg(&bank[26-16], ms->pmsa_nat_bits, &old_regs->r26, &old_unat);
801 	copy_reg(&bank[27-16], ms->pmsa_nat_bits, &old_regs->r27, &old_unat);
802 	copy_reg(&bank[28-16], ms->pmsa_nat_bits, &old_regs->r28, &old_unat);
803 	copy_reg(&bank[29-16], ms->pmsa_nat_bits, &old_regs->r29, &old_unat);
804 	copy_reg(&bank[30-16], ms->pmsa_nat_bits, &old_regs->r30, &old_unat);
805 	copy_reg(&bank[31-16], ms->pmsa_nat_bits, &old_regs->r31, &old_unat);
806 
807 	/* Next stack a struct switch_stack.  mca_asm.S built a partial
808 	 * switch_stack, copy it and fill in the blanks using pt_regs and
809 	 * minstate.
810 	 *
811 	 * In the synthesized switch_stack, b0 points to ia64_leave_kernel,
812 	 * ar.pfs is set to 0.
813 	 *
814 	 * unwind.c::unw_unwind() does special processing for interrupt frames.
815 	 * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate
816 	 * is clear then unw_unwind() does _not_ adjust bsp over pt_regs.  Not
817 	 * that this is documented, of course.  Set PRED_NON_SYSCALL in the
818 	 * switch_stack on the original stack so it will unwind correctly when
819 	 * unwind.c reads pt_regs.
820 	 *
821 	 * thread.ksp is updated to point to the synthesized switch_stack.
822 	 */
823 	p -= sizeof(struct switch_stack);
824 	old_sw = (struct switch_stack *)p;
825 	memcpy(old_sw, sw, sizeof(*sw));
826 	old_sw->caller_unat = old_unat;
827 	old_sw->ar_fpsr = old_regs->ar_fpsr;
828 	copy_reg(&ms->pmsa_gr[4-1], ms->pmsa_nat_bits, &old_sw->r4, &old_unat);
829 	copy_reg(&ms->pmsa_gr[5-1], ms->pmsa_nat_bits, &old_sw->r5, &old_unat);
830 	copy_reg(&ms->pmsa_gr[6-1], ms->pmsa_nat_bits, &old_sw->r6, &old_unat);
831 	copy_reg(&ms->pmsa_gr[7-1], ms->pmsa_nat_bits, &old_sw->r7, &old_unat);
832 	old_sw->b0 = (u64)ia64_leave_kernel;
833 	old_sw->b1 = ms->pmsa_br1;
834 	old_sw->ar_pfs = 0;
835 	old_sw->ar_unat = old_unat;
836 	old_sw->pr = old_regs->pr | (1UL << PRED_NON_SYSCALL);
837 	previous_current->thread.ksp = (u64)p - 16;
838 
839 	/* Finally copy the original stack's registers back to its RBS.
840 	 * Registers from ar.bspstore through ar.bsp at the time of the event
841 	 * are in the current RBS, copy them back to the original stack.  The
842 	 * copy must be done register by register because the original bspstore
843 	 * and the current one have different alignments, so the saved RNAT
844 	 * data occurs at different places.
845 	 *
846 	 * mca_asm does cover, so the old_bsp already includes all registers at
847 	 * the time of MCA/INIT.  It also does flushrs, so all registers before
848 	 * this function have been written to backing store on the MCA/INIT
849 	 * stack.
850 	 */
851 	new_rnat = ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore));
852 	old_rnat = regs->ar_rnat;
853 	while (slots--) {
854 		if (ia64_rse_is_rnat_slot(new_bspstore)) {
855 			new_rnat = ia64_get_rnat(new_bspstore++);
856 		}
857 		if (ia64_rse_is_rnat_slot(old_bspstore)) {
858 			*old_bspstore++ = old_rnat;
859 			old_rnat = 0;
860 		}
861 		nat = (new_rnat >> ia64_rse_slot_num(new_bspstore)) & 1UL;
862 		old_rnat &= ~(1UL << ia64_rse_slot_num(old_bspstore));
863 		old_rnat |= (nat << ia64_rse_slot_num(old_bspstore));
864 		*old_bspstore++ = *new_bspstore++;
865 	}
866 	old_sw->ar_bspstore = (unsigned long)old_bspstore;
867 	old_sw->ar_rnat = old_rnat;
868 
869 	sos->prev_task = previous_current;
870 	return previous_current;
871 
872 no_mod:
873 	printk(KERN_INFO "cpu %d, %s %s, original stack not modified\n",
874 			smp_processor_id(), type, msg);
875 	return previous_current;
876 }
877 
878 /* The monarch/slave interaction is based on monarch_cpu and requires that all
879  * slaves have entered rendezvous before the monarch leaves.  If any cpu has
880  * not entered rendezvous yet then wait a bit.  The assumption is that any
881  * slave that has not rendezvoused after a reasonable time is never going to do
882  * so.  In this context, slave includes cpus that respond to the MCA rendezvous
883  * interrupt, as well as cpus that receive the INIT slave event.
884  */
885 
886 static void
887 ia64_wait_for_slaves(int monarch)
888 {
889 	int c, wait = 0;
890 	for_each_online_cpu(c) {
891 		if (c == monarch)
892 			continue;
893 		if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
894 			udelay(1000);		/* short wait first */
895 			wait = 1;
896 			break;
897 		}
898 	}
899 	if (!wait)
900 		return;
901 	for_each_online_cpu(c) {
902 		if (c == monarch)
903 			continue;
904 		if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
905 			udelay(5*1000000);	/* wait 5 seconds for slaves (arbitrary) */
906 			break;
907 		}
908 	}
909 }
910 
911 /*
912  * ia64_mca_handler
913  *
914  *	This is uncorrectable machine check handler called from OS_MCA
915  *	dispatch code which is in turn called from SAL_CHECK().
916  *	This is the place where the core of OS MCA handling is done.
917  *	Right now the logs are extracted and displayed in a well-defined
918  *	format. This handler code is supposed to be run only on the
919  *	monarch processor. Once the monarch is done with MCA handling
920  *	further MCA logging is enabled by clearing logs.
921  *	Monarch also has the duty of sending wakeup-IPIs to pull the
922  *	slave processors out of rendezvous spinloop.
923  */
924 void
925 ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw,
926 		 struct ia64_sal_os_state *sos)
927 {
928 	pal_processor_state_info_t *psp = (pal_processor_state_info_t *)
929 		&sos->proc_state_param;
930 	int recover, cpu = smp_processor_id();
931 	task_t *previous_current;
932 
933 	oops_in_progress = 1;	/* FIXME: make printk NMI/MCA/INIT safe */
934 	previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA");
935 	monarch_cpu = cpu;
936 	ia64_wait_for_slaves(cpu);
937 
938 	/* Wakeup all the processors which are spinning in the rendezvous loop.
939 	 * They will leave SAL, then spin in the OS with interrupts disabled
940 	 * until this monarch cpu leaves the MCA handler.  That gets control
941 	 * back to the OS so we can backtrace the other cpus, backtrace when
942 	 * spinning in SAL does not work.
943 	 */
944 	ia64_mca_wakeup_all();
945 
946 	/* Get the MCA error record and log it */
947 	ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
948 
949 	/* TLB error is only exist in this SAL error record */
950 	recover = (psp->tc && !(psp->cc || psp->bc || psp->rc || psp->uc))
951 	/* other error recovery */
952 	   || (ia64_mca_ucmc_extension
953 		&& ia64_mca_ucmc_extension(
954 			IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA),
955 			sos));
956 
957 	if (recover) {
958 		sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA);
959 		rh->severity = sal_log_severity_corrected;
960 		ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA);
961 		sos->os_status = IA64_MCA_CORRECTED;
962 	}
963 
964 	set_curr_task(cpu, previous_current);
965 	monarch_cpu = -1;
966 }
967 
968 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd, NULL);
969 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd, NULL);
970 
971 /*
972  * ia64_mca_cmc_int_handler
973  *
974  *  This is corrected machine check interrupt handler.
975  *	Right now the logs are extracted and displayed in a well-defined
976  *	format.
977  *
978  * Inputs
979  *      interrupt number
980  *      client data arg ptr
981  *      saved registers ptr
982  *
983  * Outputs
984  *	None
985  */
986 static irqreturn_t
987 ia64_mca_cmc_int_handler(int cmc_irq, void *arg, struct pt_regs *ptregs)
988 {
989 	static unsigned long	cmc_history[CMC_HISTORY_LENGTH];
990 	static int		index;
991 	static DEFINE_SPINLOCK(cmc_history_lock);
992 
993 	IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
994 		       __FUNCTION__, cmc_irq, smp_processor_id());
995 
996 	/* SAL spec states this should run w/ interrupts enabled */
997 	local_irq_enable();
998 
999 	/* Get the CMC error record and log it */
1000 	ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
1001 
1002 	spin_lock(&cmc_history_lock);
1003 	if (!cmc_polling_enabled) {
1004 		int i, count = 1; /* we know 1 happened now */
1005 		unsigned long now = jiffies;
1006 
1007 		for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
1008 			if (now - cmc_history[i] <= HZ)
1009 				count++;
1010 		}
1011 
1012 		IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
1013 		if (count >= CMC_HISTORY_LENGTH) {
1014 
1015 			cmc_polling_enabled = 1;
1016 			spin_unlock(&cmc_history_lock);
1017 			/* If we're being hit with CMC interrupts, we won't
1018 			 * ever execute the schedule_work() below.  Need to
1019 			 * disable CMC interrupts on this processor now.
1020 			 */
1021 			ia64_mca_cmc_vector_disable(NULL);
1022 			schedule_work(&cmc_disable_work);
1023 
1024 			/*
1025 			 * Corrected errors will still be corrected, but
1026 			 * make sure there's a log somewhere that indicates
1027 			 * something is generating more than we can handle.
1028 			 */
1029 			printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
1030 
1031 			mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1032 
1033 			/* lock already released, get out now */
1034 			return IRQ_HANDLED;
1035 		} else {
1036 			cmc_history[index++] = now;
1037 			if (index == CMC_HISTORY_LENGTH)
1038 				index = 0;
1039 		}
1040 	}
1041 	spin_unlock(&cmc_history_lock);
1042 	return IRQ_HANDLED;
1043 }
1044 
1045 /*
1046  *  ia64_mca_cmc_int_caller
1047  *
1048  * 	Triggered by sw interrupt from CMC polling routine.  Calls
1049  * 	real interrupt handler and either triggers a sw interrupt
1050  * 	on the next cpu or does cleanup at the end.
1051  *
1052  * Inputs
1053  *	interrupt number
1054  *	client data arg ptr
1055  *	saved registers ptr
1056  * Outputs
1057  * 	handled
1058  */
1059 static irqreturn_t
1060 ia64_mca_cmc_int_caller(int cmc_irq, void *arg, struct pt_regs *ptregs)
1061 {
1062 	static int start_count = -1;
1063 	unsigned int cpuid;
1064 
1065 	cpuid = smp_processor_id();
1066 
1067 	/* If first cpu, update count */
1068 	if (start_count == -1)
1069 		start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
1070 
1071 	ia64_mca_cmc_int_handler(cmc_irq, arg, ptregs);
1072 
1073 	for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1074 
1075 	if (cpuid < NR_CPUS) {
1076 		platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1077 	} else {
1078 		/* If no log record, switch out of polling mode */
1079 		if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
1080 
1081 			printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
1082 			schedule_work(&cmc_enable_work);
1083 			cmc_polling_enabled = 0;
1084 
1085 		} else {
1086 
1087 			mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1088 		}
1089 
1090 		start_count = -1;
1091 	}
1092 
1093 	return IRQ_HANDLED;
1094 }
1095 
1096 /*
1097  *  ia64_mca_cmc_poll
1098  *
1099  *	Poll for Corrected Machine Checks (CMCs)
1100  *
1101  * Inputs   :   dummy(unused)
1102  * Outputs  :   None
1103  *
1104  */
1105 static void
1106 ia64_mca_cmc_poll (unsigned long dummy)
1107 {
1108 	/* Trigger a CMC interrupt cascade  */
1109 	platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1110 }
1111 
1112 /*
1113  *  ia64_mca_cpe_int_caller
1114  *
1115  * 	Triggered by sw interrupt from CPE polling routine.  Calls
1116  * 	real interrupt handler and either triggers a sw interrupt
1117  * 	on the next cpu or does cleanup at the end.
1118  *
1119  * Inputs
1120  *	interrupt number
1121  *	client data arg ptr
1122  *	saved registers ptr
1123  * Outputs
1124  * 	handled
1125  */
1126 #ifdef CONFIG_ACPI
1127 
1128 static irqreturn_t
1129 ia64_mca_cpe_int_caller(int cpe_irq, void *arg, struct pt_regs *ptregs)
1130 {
1131 	static int start_count = -1;
1132 	static int poll_time = MIN_CPE_POLL_INTERVAL;
1133 	unsigned int cpuid;
1134 
1135 	cpuid = smp_processor_id();
1136 
1137 	/* If first cpu, update count */
1138 	if (start_count == -1)
1139 		start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
1140 
1141 	ia64_mca_cpe_int_handler(cpe_irq, arg, ptregs);
1142 
1143 	for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1144 
1145 	if (cpuid < NR_CPUS) {
1146 		platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1147 	} else {
1148 		/*
1149 		 * If a log was recorded, increase our polling frequency,
1150 		 * otherwise, backoff or return to interrupt mode.
1151 		 */
1152 		if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
1153 			poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
1154 		} else if (cpe_vector < 0) {
1155 			poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1156 		} else {
1157 			poll_time = MIN_CPE_POLL_INTERVAL;
1158 
1159 			printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
1160 			enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
1161 			cpe_poll_enabled = 0;
1162 		}
1163 
1164 		if (cpe_poll_enabled)
1165 			mod_timer(&cpe_poll_timer, jiffies + poll_time);
1166 		start_count = -1;
1167 	}
1168 
1169 	return IRQ_HANDLED;
1170 }
1171 
1172 /*
1173  *  ia64_mca_cpe_poll
1174  *
1175  *	Poll for Corrected Platform Errors (CPEs), trigger interrupt
1176  *	on first cpu, from there it will trickle through all the cpus.
1177  *
1178  * Inputs   :   dummy(unused)
1179  * Outputs  :   None
1180  *
1181  */
1182 static void
1183 ia64_mca_cpe_poll (unsigned long dummy)
1184 {
1185 	/* Trigger a CPE interrupt cascade  */
1186 	platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1187 }
1188 
1189 #endif /* CONFIG_ACPI */
1190 
1191 /*
1192  * C portion of the OS INIT handler
1193  *
1194  * Called from ia64_os_init_dispatch
1195  *
1196  * Inputs: pointer to pt_regs where processor info was saved.  SAL/OS state for
1197  * this event.  This code is used for both monarch and slave INIT events, see
1198  * sos->monarch.
1199  *
1200  * All INIT events switch to the INIT stack and change the previous process to
1201  * blocked status.  If one of the INIT events is the monarch then we are
1202  * probably processing the nmi button/command.  Use the monarch cpu to dump all
1203  * the processes.  The slave INIT events all spin until the monarch cpu
1204  * returns.  We can also get INIT slave events for MCA, in which case the MCA
1205  * process is the monarch.
1206  */
1207 
1208 void
1209 ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw,
1210 		  struct ia64_sal_os_state *sos)
1211 {
1212 	static atomic_t slaves;
1213 	static atomic_t monarchs;
1214 	task_t *previous_current;
1215 	int cpu = smp_processor_id(), c;
1216 	struct task_struct *g, *t;
1217 
1218 	oops_in_progress = 1;	/* FIXME: make printk NMI/MCA/INIT safe */
1219 	console_loglevel = 15;	/* make sure printks make it to console */
1220 
1221 	printk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
1222 		sos->proc_state_param, cpu, sos->monarch);
1223 	salinfo_log_wakeup(SAL_INFO_TYPE_INIT, NULL, 0, 0);
1224 
1225 	previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "INIT");
1226 	sos->os_status = IA64_INIT_RESUME;
1227 
1228 	/* FIXME: Workaround for broken proms that drive all INIT events as
1229 	 * slaves.  The last slave that enters is promoted to be a monarch.
1230 	 * Remove this code in September 2006, that gives platforms a year to
1231 	 * fix their proms and get their customers updated.
1232 	 */
1233 	if (!sos->monarch && atomic_add_return(1, &slaves) == num_online_cpus()) {
1234 		printk(KERN_WARNING "%s: Promoting cpu %d to monarch.\n",
1235 		       __FUNCTION__, cpu);
1236 		atomic_dec(&slaves);
1237 		sos->monarch = 1;
1238 	}
1239 
1240 	/* FIXME: Workaround for broken proms that drive all INIT events as
1241 	 * monarchs.  Second and subsequent monarchs are demoted to slaves.
1242 	 * Remove this code in September 2006, that gives platforms a year to
1243 	 * fix their proms and get their customers updated.
1244 	 */
1245 	if (sos->monarch && atomic_add_return(1, &monarchs) > 1) {
1246 		printk(KERN_WARNING "%s: Demoting cpu %d to slave.\n",
1247 			       __FUNCTION__, cpu);
1248 		atomic_dec(&monarchs);
1249 		sos->monarch = 0;
1250 	}
1251 
1252 	if (!sos->monarch) {
1253 		ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT;
1254 		while (monarch_cpu == -1)
1255 		       cpu_relax();	/* spin until monarch enters */
1256 		while (monarch_cpu != -1)
1257 		       cpu_relax();	/* spin until monarch leaves */
1258 		printk("Slave on cpu %d returning to normal service.\n", cpu);
1259 		set_curr_task(cpu, previous_current);
1260 		ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1261 		atomic_dec(&slaves);
1262 		return;
1263 	}
1264 
1265 	monarch_cpu = cpu;
1266 
1267 	/*
1268 	 * Wait for a bit.  On some machines (e.g., HP's zx2000 and zx6000, INIT can be
1269 	 * generated via the BMC's command-line interface, but since the console is on the
1270 	 * same serial line, the user will need some time to switch out of the BMC before
1271 	 * the dump begins.
1272 	 */
1273 	printk("Delaying for 5 seconds...\n");
1274 	udelay(5*1000000);
1275 	ia64_wait_for_slaves(cpu);
1276 	printk(KERN_ERR "Processes interrupted by INIT -");
1277 	for_each_online_cpu(c) {
1278 		struct ia64_sal_os_state *s;
1279 		t = __va(__per_cpu_mca[c] + IA64_MCA_CPU_INIT_STACK_OFFSET);
1280 		s = (struct ia64_sal_os_state *)((char *)t + MCA_SOS_OFFSET);
1281 		g = s->prev_task;
1282 		if (g) {
1283 			if (g->pid)
1284 				printk(" %d", g->pid);
1285 			else
1286 				printk(" %d (cpu %d task 0x%p)", g->pid, task_cpu(g), g);
1287 		}
1288 	}
1289 	printk("\n\n");
1290 	if (read_trylock(&tasklist_lock)) {
1291 		do_each_thread (g, t) {
1292 			printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
1293 			show_stack(t, NULL);
1294 		} while_each_thread (g, t);
1295 		read_unlock(&tasklist_lock);
1296 	}
1297 	printk("\nINIT dump complete.  Monarch on cpu %d returning to normal service.\n", cpu);
1298 	atomic_dec(&monarchs);
1299 	set_curr_task(cpu, previous_current);
1300 	monarch_cpu = -1;
1301 	return;
1302 }
1303 
1304 static int __init
1305 ia64_mca_disable_cpe_polling(char *str)
1306 {
1307 	cpe_poll_enabled = 0;
1308 	return 1;
1309 }
1310 
1311 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1312 
1313 static struct irqaction cmci_irqaction = {
1314 	.handler =	ia64_mca_cmc_int_handler,
1315 	.flags =	SA_INTERRUPT,
1316 	.name =		"cmc_hndlr"
1317 };
1318 
1319 static struct irqaction cmcp_irqaction = {
1320 	.handler =	ia64_mca_cmc_int_caller,
1321 	.flags =	SA_INTERRUPT,
1322 	.name =		"cmc_poll"
1323 };
1324 
1325 static struct irqaction mca_rdzv_irqaction = {
1326 	.handler =	ia64_mca_rendez_int_handler,
1327 	.flags =	SA_INTERRUPT,
1328 	.name =		"mca_rdzv"
1329 };
1330 
1331 static struct irqaction mca_wkup_irqaction = {
1332 	.handler =	ia64_mca_wakeup_int_handler,
1333 	.flags =	SA_INTERRUPT,
1334 	.name =		"mca_wkup"
1335 };
1336 
1337 #ifdef CONFIG_ACPI
1338 static struct irqaction mca_cpe_irqaction = {
1339 	.handler =	ia64_mca_cpe_int_handler,
1340 	.flags =	SA_INTERRUPT,
1341 	.name =		"cpe_hndlr"
1342 };
1343 
1344 static struct irqaction mca_cpep_irqaction = {
1345 	.handler =	ia64_mca_cpe_int_caller,
1346 	.flags =	SA_INTERRUPT,
1347 	.name =		"cpe_poll"
1348 };
1349 #endif /* CONFIG_ACPI */
1350 
1351 /* Minimal format of the MCA/INIT stacks.  The pseudo processes that run on
1352  * these stacks can never sleep, they cannot return from the kernel to user
1353  * space, they do not appear in a normal ps listing.  So there is no need to
1354  * format most of the fields.
1355  */
1356 
1357 static void
1358 format_mca_init_stack(void *mca_data, unsigned long offset,
1359 		const char *type, int cpu)
1360 {
1361 	struct task_struct *p = (struct task_struct *)((char *)mca_data + offset);
1362 	struct thread_info *ti;
1363 	memset(p, 0, KERNEL_STACK_SIZE);
1364 	ti = (struct thread_info *)((char *)p + IA64_TASK_SIZE);
1365 	ti->flags = _TIF_MCA_INIT;
1366 	ti->preempt_count = 1;
1367 	ti->task = p;
1368 	ti->cpu = cpu;
1369 	p->thread_info = ti;
1370 	p->state = TASK_UNINTERRUPTIBLE;
1371 	__set_bit(cpu, &p->cpus_allowed);
1372 	INIT_LIST_HEAD(&p->tasks);
1373 	p->parent = p->real_parent = p->group_leader = p;
1374 	INIT_LIST_HEAD(&p->children);
1375 	INIT_LIST_HEAD(&p->sibling);
1376 	strncpy(p->comm, type, sizeof(p->comm)-1);
1377 }
1378 
1379 /* Do per-CPU MCA-related initialization.  */
1380 
1381 void __devinit
1382 ia64_mca_cpu_init(void *cpu_data)
1383 {
1384 	void *pal_vaddr;
1385 
1386 	if (smp_processor_id() == 0) {
1387 		void *mca_data;
1388 		int cpu;
1389 
1390 		mca_data = alloc_bootmem(sizeof(struct ia64_mca_cpu)
1391 					 * NR_CPUS + KERNEL_STACK_SIZE);
1392 		mca_data = (void *)(((unsigned long)mca_data +
1393 					KERNEL_STACK_SIZE - 1) &
1394 				(-KERNEL_STACK_SIZE));
1395 		for (cpu = 0; cpu < NR_CPUS; cpu++) {
1396 			format_mca_init_stack(mca_data,
1397 					offsetof(struct ia64_mca_cpu, mca_stack),
1398 					"MCA", cpu);
1399 			format_mca_init_stack(mca_data,
1400 					offsetof(struct ia64_mca_cpu, init_stack),
1401 					"INIT", cpu);
1402 			__per_cpu_mca[cpu] = __pa(mca_data);
1403 			mca_data += sizeof(struct ia64_mca_cpu);
1404 		}
1405 	}
1406 
1407 	/*
1408 	 * The MCA info structure was allocated earlier and its
1409 	 * physical address saved in __per_cpu_mca[cpu].  Copy that
1410 	 * address * to ia64_mca_data so we can access it as a per-CPU
1411 	 * variable.
1412 	 */
1413 	__get_cpu_var(ia64_mca_data) = __per_cpu_mca[smp_processor_id()];
1414 
1415 	/*
1416 	 * Stash away a copy of the PTE needed to map the per-CPU page.
1417 	 * We may need it during MCA recovery.
1418 	 */
1419 	__get_cpu_var(ia64_mca_per_cpu_pte) =
1420 		pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL));
1421 
1422 	/*
1423 	 * Also, stash away a copy of the PAL address and the PTE
1424 	 * needed to map it.
1425 	 */
1426 	pal_vaddr = efi_get_pal_addr();
1427 	if (!pal_vaddr)
1428 		return;
1429 	__get_cpu_var(ia64_mca_pal_base) =
1430 		GRANULEROUNDDOWN((unsigned long) pal_vaddr);
1431 	__get_cpu_var(ia64_mca_pal_pte) = pte_val(mk_pte_phys(__pa(pal_vaddr),
1432 							      PAGE_KERNEL));
1433 }
1434 
1435 /*
1436  * ia64_mca_init
1437  *
1438  *  Do all the system level mca specific initialization.
1439  *
1440  *	1. Register spinloop and wakeup request interrupt vectors
1441  *
1442  *	2. Register OS_MCA handler entry point
1443  *
1444  *	3. Register OS_INIT handler entry point
1445  *
1446  *  4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1447  *
1448  *  Note that this initialization is done very early before some kernel
1449  *  services are available.
1450  *
1451  *  Inputs  :   None
1452  *
1453  *  Outputs :   None
1454  */
1455 void __init
1456 ia64_mca_init(void)
1457 {
1458 	ia64_fptr_t *init_hldlr_ptr_monarch = (ia64_fptr_t *)ia64_os_init_dispatch_monarch;
1459 	ia64_fptr_t *init_hldlr_ptr_slave = (ia64_fptr_t *)ia64_os_init_dispatch_slave;
1460 	ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1461 	int i;
1462 	s64 rc;
1463 	struct ia64_sal_retval isrv;
1464 	u64 timeout = IA64_MCA_RENDEZ_TIMEOUT;	/* platform specific */
1465 
1466 	IA64_MCA_DEBUG("%s: begin\n", __FUNCTION__);
1467 
1468 	/* Clear the Rendez checkin flag for all cpus */
1469 	for(i = 0 ; i < NR_CPUS; i++)
1470 		ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1471 
1472 	/*
1473 	 * Register the rendezvous spinloop and wakeup mechanism with SAL
1474 	 */
1475 
1476 	/* Register the rendezvous interrupt vector with SAL */
1477 	while (1) {
1478 		isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1479 					      SAL_MC_PARAM_MECHANISM_INT,
1480 					      IA64_MCA_RENDEZ_VECTOR,
1481 					      timeout,
1482 					      SAL_MC_PARAM_RZ_ALWAYS);
1483 		rc = isrv.status;
1484 		if (rc == 0)
1485 			break;
1486 		if (rc == -2) {
1487 			printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1488 				"%ld to %ld milliseconds\n", timeout, isrv.v0);
1489 			timeout = isrv.v0;
1490 			continue;
1491 		}
1492 		printk(KERN_ERR "Failed to register rendezvous interrupt "
1493 		       "with SAL (status %ld)\n", rc);
1494 		return;
1495 	}
1496 
1497 	/* Register the wakeup interrupt vector with SAL */
1498 	isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1499 				      SAL_MC_PARAM_MECHANISM_INT,
1500 				      IA64_MCA_WAKEUP_VECTOR,
1501 				      0, 0);
1502 	rc = isrv.status;
1503 	if (rc) {
1504 		printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1505 		       "(status %ld)\n", rc);
1506 		return;
1507 	}
1508 
1509 	IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __FUNCTION__);
1510 
1511 	ia64_mc_info.imi_mca_handler        = ia64_tpa(mca_hldlr_ptr->fp);
1512 	/*
1513 	 * XXX - disable SAL checksum by setting size to 0; should be
1514 	 *	ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1515 	 */
1516 	ia64_mc_info.imi_mca_handler_size	= 0;
1517 
1518 	/* Register the os mca handler with SAL */
1519 	if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
1520 				       ia64_mc_info.imi_mca_handler,
1521 				       ia64_tpa(mca_hldlr_ptr->gp),
1522 				       ia64_mc_info.imi_mca_handler_size,
1523 				       0, 0, 0)))
1524 	{
1525 		printk(KERN_ERR "Failed to register OS MCA handler with SAL "
1526 		       "(status %ld)\n", rc);
1527 		return;
1528 	}
1529 
1530 	IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __FUNCTION__,
1531 		       ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
1532 
1533 	/*
1534 	 * XXX - disable SAL checksum by setting size to 0, should be
1535 	 * size of the actual init handler in mca_asm.S.
1536 	 */
1537 	ia64_mc_info.imi_monarch_init_handler		= ia64_tpa(init_hldlr_ptr_monarch->fp);
1538 	ia64_mc_info.imi_monarch_init_handler_size	= 0;
1539 	ia64_mc_info.imi_slave_init_handler		= ia64_tpa(init_hldlr_ptr_slave->fp);
1540 	ia64_mc_info.imi_slave_init_handler_size	= 0;
1541 
1542 	IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __FUNCTION__,
1543 		       ia64_mc_info.imi_monarch_init_handler);
1544 
1545 	/* Register the os init handler with SAL */
1546 	if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
1547 				       ia64_mc_info.imi_monarch_init_handler,
1548 				       ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1549 				       ia64_mc_info.imi_monarch_init_handler_size,
1550 				       ia64_mc_info.imi_slave_init_handler,
1551 				       ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1552 				       ia64_mc_info.imi_slave_init_handler_size)))
1553 	{
1554 		printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
1555 		       "(status %ld)\n", rc);
1556 		return;
1557 	}
1558 
1559 	IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __FUNCTION__);
1560 
1561 	/*
1562 	 *  Configure the CMCI/P vector and handler. Interrupts for CMC are
1563 	 *  per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
1564 	 */
1565 	register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
1566 	register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
1567 	ia64_mca_cmc_vector_setup();       /* Setup vector on BSP */
1568 
1569 	/* Setup the MCA rendezvous interrupt vector */
1570 	register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
1571 
1572 	/* Setup the MCA wakeup interrupt vector */
1573 	register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
1574 
1575 #ifdef CONFIG_ACPI
1576 	/* Setup the CPEI/P handler */
1577 	register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
1578 #endif
1579 
1580 	/* Initialize the areas set aside by the OS to buffer the
1581 	 * platform/processor error states for MCA/INIT/CMC
1582 	 * handling.
1583 	 */
1584 	ia64_log_init(SAL_INFO_TYPE_MCA);
1585 	ia64_log_init(SAL_INFO_TYPE_INIT);
1586 	ia64_log_init(SAL_INFO_TYPE_CMC);
1587 	ia64_log_init(SAL_INFO_TYPE_CPE);
1588 
1589 	mca_init = 1;
1590 	printk(KERN_INFO "MCA related initialization done\n");
1591 }
1592 
1593 /*
1594  * ia64_mca_late_init
1595  *
1596  *	Opportunity to setup things that require initialization later
1597  *	than ia64_mca_init.  Setup a timer to poll for CPEs if the
1598  *	platform doesn't support an interrupt driven mechanism.
1599  *
1600  *  Inputs  :   None
1601  *  Outputs :   Status
1602  */
1603 static int __init
1604 ia64_mca_late_init(void)
1605 {
1606 	if (!mca_init)
1607 		return 0;
1608 
1609 	/* Setup the CMCI/P vector and handler */
1610 	init_timer(&cmc_poll_timer);
1611 	cmc_poll_timer.function = ia64_mca_cmc_poll;
1612 
1613 	/* Unmask/enable the vector */
1614 	cmc_polling_enabled = 0;
1615 	schedule_work(&cmc_enable_work);
1616 
1617 	IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __FUNCTION__);
1618 
1619 #ifdef CONFIG_ACPI
1620 	/* Setup the CPEI/P vector and handler */
1621 	cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
1622 	init_timer(&cpe_poll_timer);
1623 	cpe_poll_timer.function = ia64_mca_cpe_poll;
1624 
1625 	{
1626 		irq_desc_t *desc;
1627 		unsigned int irq;
1628 
1629 		if (cpe_vector >= 0) {
1630 			/* If platform supports CPEI, enable the irq. */
1631 			cpe_poll_enabled = 0;
1632 			for (irq = 0; irq < NR_IRQS; ++irq)
1633 				if (irq_to_vector(irq) == cpe_vector) {
1634 					desc = irq_descp(irq);
1635 					desc->status |= IRQ_PER_CPU;
1636 					setup_irq(irq, &mca_cpe_irqaction);
1637 				}
1638 			ia64_mca_register_cpev(cpe_vector);
1639 			IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n", __FUNCTION__);
1640 		} else {
1641 			/* If platform doesn't support CPEI, get the timer going. */
1642 			if (cpe_poll_enabled) {
1643 				ia64_mca_cpe_poll(0UL);
1644 				IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __FUNCTION__);
1645 			}
1646 		}
1647 	}
1648 #endif
1649 
1650 	return 0;
1651 }
1652 
1653 device_initcall(ia64_mca_late_init);
1654