1 /* 2 * linux/arch/ia64/kernel/irq_ia64.c 3 * 4 * Copyright (C) 1998-2001 Hewlett-Packard Co 5 * Stephane Eranian <eranian@hpl.hp.com> 6 * David Mosberger-Tang <davidm@hpl.hp.com> 7 * 8 * 6/10/99: Updated to bring in sync with x86 version to facilitate 9 * support for SMP and different interrupt controllers. 10 * 11 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector 12 * PCI to vector allocation routine. 13 * 04/14/2004 Ashok Raj <ashok.raj@intel.com> 14 * Added CPU Hotplug handling for IPF. 15 */ 16 17 #include <linux/module.h> 18 19 #include <linux/jiffies.h> 20 #include <linux/errno.h> 21 #include <linux/init.h> 22 #include <linux/interrupt.h> 23 #include <linux/ioport.h> 24 #include <linux/kernel_stat.h> 25 #include <linux/ptrace.h> 26 #include <linux/signal.h> 27 #include <linux/smp.h> 28 #include <linux/threads.h> 29 #include <linux/bitops.h> 30 #include <linux/irq.h> 31 #include <linux/ratelimit.h> 32 #include <linux/acpi.h> 33 #include <linux/sched.h> 34 35 #include <asm/delay.h> 36 #include <asm/intrinsics.h> 37 #include <asm/io.h> 38 #include <asm/hw_irq.h> 39 #include <asm/machvec.h> 40 #include <asm/pgtable.h> 41 #include <asm/tlbflush.h> 42 43 #ifdef CONFIG_PERFMON 44 # include <asm/perfmon.h> 45 #endif 46 47 #define IRQ_DEBUG 0 48 49 #define IRQ_VECTOR_UNASSIGNED (0) 50 51 #define IRQ_UNUSED (0) 52 #define IRQ_USED (1) 53 #define IRQ_RSVD (2) 54 55 /* These can be overridden in platform_irq_init */ 56 int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR; 57 int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR; 58 59 /* default base addr of IPI table */ 60 void __iomem *ipi_base_addr = ((void __iomem *) 61 (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR)); 62 63 static cpumask_t vector_allocation_domain(int cpu); 64 65 /* 66 * Legacy IRQ to IA-64 vector translation table. 67 */ 68 __u8 isa_irq_to_vector_map[16] = { 69 /* 8259 IRQ translation, first 16 entries */ 70 0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 71 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21 72 }; 73 EXPORT_SYMBOL(isa_irq_to_vector_map); 74 75 DEFINE_SPINLOCK(vector_lock); 76 77 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = { 78 [0 ... NR_IRQS - 1] = { 79 .vector = IRQ_VECTOR_UNASSIGNED, 80 .domain = CPU_MASK_NONE 81 } 82 }; 83 84 DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = { 85 [0 ... IA64_NUM_VECTORS - 1] = -1 86 }; 87 88 static cpumask_t vector_table[IA64_NUM_VECTORS] = { 89 [0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE 90 }; 91 92 static int irq_status[NR_IRQS] = { 93 [0 ... NR_IRQS -1] = IRQ_UNUSED 94 }; 95 96 static inline int find_unassigned_irq(void) 97 { 98 int irq; 99 100 for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++) 101 if (irq_status[irq] == IRQ_UNUSED) 102 return irq; 103 return -ENOSPC; 104 } 105 106 static inline int find_unassigned_vector(cpumask_t domain) 107 { 108 cpumask_t mask; 109 int pos, vector; 110 111 cpumask_and(&mask, &domain, cpu_online_mask); 112 if (cpus_empty(mask)) 113 return -EINVAL; 114 115 for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) { 116 vector = IA64_FIRST_DEVICE_VECTOR + pos; 117 cpus_and(mask, domain, vector_table[vector]); 118 if (!cpus_empty(mask)) 119 continue; 120 return vector; 121 } 122 return -ENOSPC; 123 } 124 125 static int __bind_irq_vector(int irq, int vector, cpumask_t domain) 126 { 127 cpumask_t mask; 128 int cpu; 129 struct irq_cfg *cfg = &irq_cfg[irq]; 130 131 BUG_ON((unsigned)irq >= NR_IRQS); 132 BUG_ON((unsigned)vector >= IA64_NUM_VECTORS); 133 134 cpumask_and(&mask, &domain, cpu_online_mask); 135 if (cpus_empty(mask)) 136 return -EINVAL; 137 if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain)) 138 return 0; 139 if (cfg->vector != IRQ_VECTOR_UNASSIGNED) 140 return -EBUSY; 141 for_each_cpu_mask(cpu, mask) 142 per_cpu(vector_irq, cpu)[vector] = irq; 143 cfg->vector = vector; 144 cfg->domain = domain; 145 irq_status[irq] = IRQ_USED; 146 cpus_or(vector_table[vector], vector_table[vector], domain); 147 return 0; 148 } 149 150 int bind_irq_vector(int irq, int vector, cpumask_t domain) 151 { 152 unsigned long flags; 153 int ret; 154 155 spin_lock_irqsave(&vector_lock, flags); 156 ret = __bind_irq_vector(irq, vector, domain); 157 spin_unlock_irqrestore(&vector_lock, flags); 158 return ret; 159 } 160 161 static void __clear_irq_vector(int irq) 162 { 163 int vector, cpu; 164 cpumask_t mask; 165 cpumask_t domain; 166 struct irq_cfg *cfg = &irq_cfg[irq]; 167 168 BUG_ON((unsigned)irq >= NR_IRQS); 169 BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED); 170 vector = cfg->vector; 171 domain = cfg->domain; 172 cpumask_and(&mask, &cfg->domain, cpu_online_mask); 173 for_each_cpu_mask(cpu, mask) 174 per_cpu(vector_irq, cpu)[vector] = -1; 175 cfg->vector = IRQ_VECTOR_UNASSIGNED; 176 cfg->domain = CPU_MASK_NONE; 177 irq_status[irq] = IRQ_UNUSED; 178 cpus_andnot(vector_table[vector], vector_table[vector], domain); 179 } 180 181 static void clear_irq_vector(int irq) 182 { 183 unsigned long flags; 184 185 spin_lock_irqsave(&vector_lock, flags); 186 __clear_irq_vector(irq); 187 spin_unlock_irqrestore(&vector_lock, flags); 188 } 189 190 int 191 ia64_native_assign_irq_vector (int irq) 192 { 193 unsigned long flags; 194 int vector, cpu; 195 cpumask_t domain = CPU_MASK_NONE; 196 197 vector = -ENOSPC; 198 199 spin_lock_irqsave(&vector_lock, flags); 200 for_each_online_cpu(cpu) { 201 domain = vector_allocation_domain(cpu); 202 vector = find_unassigned_vector(domain); 203 if (vector >= 0) 204 break; 205 } 206 if (vector < 0) 207 goto out; 208 if (irq == AUTO_ASSIGN) 209 irq = vector; 210 BUG_ON(__bind_irq_vector(irq, vector, domain)); 211 out: 212 spin_unlock_irqrestore(&vector_lock, flags); 213 return vector; 214 } 215 216 void 217 ia64_native_free_irq_vector (int vector) 218 { 219 if (vector < IA64_FIRST_DEVICE_VECTOR || 220 vector > IA64_LAST_DEVICE_VECTOR) 221 return; 222 clear_irq_vector(vector); 223 } 224 225 int 226 reserve_irq_vector (int vector) 227 { 228 if (vector < IA64_FIRST_DEVICE_VECTOR || 229 vector > IA64_LAST_DEVICE_VECTOR) 230 return -EINVAL; 231 return !!bind_irq_vector(vector, vector, CPU_MASK_ALL); 232 } 233 234 /* 235 * Initialize vector_irq on a new cpu. This function must be called 236 * with vector_lock held. 237 */ 238 void __setup_vector_irq(int cpu) 239 { 240 int irq, vector; 241 242 /* Clear vector_irq */ 243 for (vector = 0; vector < IA64_NUM_VECTORS; ++vector) 244 per_cpu(vector_irq, cpu)[vector] = -1; 245 /* Mark the inuse vectors */ 246 for (irq = 0; irq < NR_IRQS; ++irq) { 247 if (!cpu_isset(cpu, irq_cfg[irq].domain)) 248 continue; 249 vector = irq_to_vector(irq); 250 per_cpu(vector_irq, cpu)[vector] = irq; 251 } 252 } 253 254 #if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG)) 255 256 static enum vector_domain_type { 257 VECTOR_DOMAIN_NONE, 258 VECTOR_DOMAIN_PERCPU 259 } vector_domain_type = VECTOR_DOMAIN_NONE; 260 261 static cpumask_t vector_allocation_domain(int cpu) 262 { 263 if (vector_domain_type == VECTOR_DOMAIN_PERCPU) 264 return cpumask_of_cpu(cpu); 265 return CPU_MASK_ALL; 266 } 267 268 static int __irq_prepare_move(int irq, int cpu) 269 { 270 struct irq_cfg *cfg = &irq_cfg[irq]; 271 int vector; 272 cpumask_t domain; 273 274 if (cfg->move_in_progress || cfg->move_cleanup_count) 275 return -EBUSY; 276 if (cfg->vector == IRQ_VECTOR_UNASSIGNED || !cpu_online(cpu)) 277 return -EINVAL; 278 if (cpu_isset(cpu, cfg->domain)) 279 return 0; 280 domain = vector_allocation_domain(cpu); 281 vector = find_unassigned_vector(domain); 282 if (vector < 0) 283 return -ENOSPC; 284 cfg->move_in_progress = 1; 285 cfg->old_domain = cfg->domain; 286 cfg->vector = IRQ_VECTOR_UNASSIGNED; 287 cfg->domain = CPU_MASK_NONE; 288 BUG_ON(__bind_irq_vector(irq, vector, domain)); 289 return 0; 290 } 291 292 int irq_prepare_move(int irq, int cpu) 293 { 294 unsigned long flags; 295 int ret; 296 297 spin_lock_irqsave(&vector_lock, flags); 298 ret = __irq_prepare_move(irq, cpu); 299 spin_unlock_irqrestore(&vector_lock, flags); 300 return ret; 301 } 302 303 void irq_complete_move(unsigned irq) 304 { 305 struct irq_cfg *cfg = &irq_cfg[irq]; 306 cpumask_t cleanup_mask; 307 int i; 308 309 if (likely(!cfg->move_in_progress)) 310 return; 311 312 if (unlikely(cpu_isset(smp_processor_id(), cfg->old_domain))) 313 return; 314 315 cpumask_and(&cleanup_mask, &cfg->old_domain, cpu_online_mask); 316 cfg->move_cleanup_count = cpus_weight(cleanup_mask); 317 for_each_cpu_mask(i, cleanup_mask) 318 platform_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0); 319 cfg->move_in_progress = 0; 320 } 321 322 static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id) 323 { 324 int me = smp_processor_id(); 325 ia64_vector vector; 326 unsigned long flags; 327 328 for (vector = IA64_FIRST_DEVICE_VECTOR; 329 vector < IA64_LAST_DEVICE_VECTOR; vector++) { 330 int irq; 331 struct irq_desc *desc; 332 struct irq_cfg *cfg; 333 irq = __get_cpu_var(vector_irq)[vector]; 334 if (irq < 0) 335 continue; 336 337 desc = irq_to_desc(irq); 338 cfg = irq_cfg + irq; 339 raw_spin_lock(&desc->lock); 340 if (!cfg->move_cleanup_count) 341 goto unlock; 342 343 if (!cpu_isset(me, cfg->old_domain)) 344 goto unlock; 345 346 spin_lock_irqsave(&vector_lock, flags); 347 __get_cpu_var(vector_irq)[vector] = -1; 348 cpu_clear(me, vector_table[vector]); 349 spin_unlock_irqrestore(&vector_lock, flags); 350 cfg->move_cleanup_count--; 351 unlock: 352 raw_spin_unlock(&desc->lock); 353 } 354 return IRQ_HANDLED; 355 } 356 357 static struct irqaction irq_move_irqaction = { 358 .handler = smp_irq_move_cleanup_interrupt, 359 .name = "irq_move" 360 }; 361 362 static int __init parse_vector_domain(char *arg) 363 { 364 if (!arg) 365 return -EINVAL; 366 if (!strcmp(arg, "percpu")) { 367 vector_domain_type = VECTOR_DOMAIN_PERCPU; 368 no_int_routing = 1; 369 } 370 return 0; 371 } 372 early_param("vector", parse_vector_domain); 373 #else 374 static cpumask_t vector_allocation_domain(int cpu) 375 { 376 return CPU_MASK_ALL; 377 } 378 #endif 379 380 381 void destroy_and_reserve_irq(unsigned int irq) 382 { 383 unsigned long flags; 384 385 dynamic_irq_cleanup(irq); 386 387 spin_lock_irqsave(&vector_lock, flags); 388 __clear_irq_vector(irq); 389 irq_status[irq] = IRQ_RSVD; 390 spin_unlock_irqrestore(&vector_lock, flags); 391 } 392 393 /* 394 * Dynamic irq allocate and deallocation for MSI 395 */ 396 int create_irq(void) 397 { 398 unsigned long flags; 399 int irq, vector, cpu; 400 cpumask_t domain = CPU_MASK_NONE; 401 402 irq = vector = -ENOSPC; 403 spin_lock_irqsave(&vector_lock, flags); 404 for_each_online_cpu(cpu) { 405 domain = vector_allocation_domain(cpu); 406 vector = find_unassigned_vector(domain); 407 if (vector >= 0) 408 break; 409 } 410 if (vector < 0) 411 goto out; 412 irq = find_unassigned_irq(); 413 if (irq < 0) 414 goto out; 415 BUG_ON(__bind_irq_vector(irq, vector, domain)); 416 out: 417 spin_unlock_irqrestore(&vector_lock, flags); 418 if (irq >= 0) 419 dynamic_irq_init(irq); 420 return irq; 421 } 422 423 void destroy_irq(unsigned int irq) 424 { 425 dynamic_irq_cleanup(irq); 426 clear_irq_vector(irq); 427 } 428 429 #ifdef CONFIG_SMP 430 # define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE) 431 # define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH) 432 #else 433 # define IS_RESCHEDULE(vec) (0) 434 # define IS_LOCAL_TLB_FLUSH(vec) (0) 435 #endif 436 /* 437 * That's where the IVT branches when we get an external 438 * interrupt. This branches to the correct hardware IRQ handler via 439 * function ptr. 440 */ 441 void 442 ia64_handle_irq (ia64_vector vector, struct pt_regs *regs) 443 { 444 struct pt_regs *old_regs = set_irq_regs(regs); 445 unsigned long saved_tpr; 446 447 #if IRQ_DEBUG 448 { 449 unsigned long bsp, sp; 450 451 /* 452 * Note: if the interrupt happened while executing in 453 * the context switch routine (ia64_switch_to), we may 454 * get a spurious stack overflow here. This is 455 * because the register and the memory stack are not 456 * switched atomically. 457 */ 458 bsp = ia64_getreg(_IA64_REG_AR_BSP); 459 sp = ia64_getreg(_IA64_REG_SP); 460 461 if ((sp - bsp) < 1024) { 462 static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5); 463 464 if (__ratelimit(&ratelimit)) { 465 printk("ia64_handle_irq: DANGER: less than " 466 "1KB of free stack space!!\n" 467 "(bsp=0x%lx, sp=%lx)\n", bsp, sp); 468 } 469 } 470 } 471 #endif /* IRQ_DEBUG */ 472 473 /* 474 * Always set TPR to limit maximum interrupt nesting depth to 475 * 16 (without this, it would be ~240, which could easily lead 476 * to kernel stack overflows). 477 */ 478 irq_enter(); 479 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR); 480 ia64_srlz_d(); 481 while (vector != IA64_SPURIOUS_INT_VECTOR) { 482 int irq = local_vector_to_irq(vector); 483 484 if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) { 485 smp_local_flush_tlb(); 486 kstat_incr_irq_this_cpu(irq); 487 } else if (unlikely(IS_RESCHEDULE(vector))) { 488 scheduler_ipi(); 489 kstat_incr_irq_this_cpu(irq); 490 } else { 491 ia64_setreg(_IA64_REG_CR_TPR, vector); 492 ia64_srlz_d(); 493 494 if (unlikely(irq < 0)) { 495 printk(KERN_ERR "%s: Unexpected interrupt " 496 "vector %d on CPU %d is not mapped " 497 "to any IRQ!\n", __func__, vector, 498 smp_processor_id()); 499 } else 500 generic_handle_irq(irq); 501 502 /* 503 * Disable interrupts and send EOI: 504 */ 505 local_irq_disable(); 506 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr); 507 } 508 ia64_eoi(); 509 vector = ia64_get_ivr(); 510 } 511 /* 512 * This must be done *after* the ia64_eoi(). For example, the keyboard softirq 513 * handler needs to be able to wait for further keyboard interrupts, which can't 514 * come through until ia64_eoi() has been done. 515 */ 516 irq_exit(); 517 set_irq_regs(old_regs); 518 } 519 520 #ifdef CONFIG_HOTPLUG_CPU 521 /* 522 * This function emulates a interrupt processing when a cpu is about to be 523 * brought down. 524 */ 525 void ia64_process_pending_intr(void) 526 { 527 ia64_vector vector; 528 unsigned long saved_tpr; 529 extern unsigned int vectors_in_migration[NR_IRQS]; 530 531 vector = ia64_get_ivr(); 532 533 irq_enter(); 534 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR); 535 ia64_srlz_d(); 536 537 /* 538 * Perform normal interrupt style processing 539 */ 540 while (vector != IA64_SPURIOUS_INT_VECTOR) { 541 int irq = local_vector_to_irq(vector); 542 543 if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) { 544 smp_local_flush_tlb(); 545 kstat_incr_irq_this_cpu(irq); 546 } else if (unlikely(IS_RESCHEDULE(vector))) { 547 kstat_incr_irq_this_cpu(irq); 548 } else { 549 struct pt_regs *old_regs = set_irq_regs(NULL); 550 551 ia64_setreg(_IA64_REG_CR_TPR, vector); 552 ia64_srlz_d(); 553 554 /* 555 * Now try calling normal ia64_handle_irq as it would have got called 556 * from a real intr handler. Try passing null for pt_regs, hopefully 557 * it will work. I hope it works!. 558 * Probably could shared code. 559 */ 560 if (unlikely(irq < 0)) { 561 printk(KERN_ERR "%s: Unexpected interrupt " 562 "vector %d on CPU %d not being mapped " 563 "to any IRQ!!\n", __func__, vector, 564 smp_processor_id()); 565 } else { 566 vectors_in_migration[irq]=0; 567 generic_handle_irq(irq); 568 } 569 set_irq_regs(old_regs); 570 571 /* 572 * Disable interrupts and send EOI 573 */ 574 local_irq_disable(); 575 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr); 576 } 577 ia64_eoi(); 578 vector = ia64_get_ivr(); 579 } 580 irq_exit(); 581 } 582 #endif 583 584 585 #ifdef CONFIG_SMP 586 587 static irqreturn_t dummy_handler (int irq, void *dev_id) 588 { 589 BUG(); 590 } 591 592 static struct irqaction ipi_irqaction = { 593 .handler = handle_IPI, 594 .name = "IPI" 595 }; 596 597 /* 598 * KVM uses this interrupt to force a cpu out of guest mode 599 */ 600 static struct irqaction resched_irqaction = { 601 .handler = dummy_handler, 602 .name = "resched" 603 }; 604 605 static struct irqaction tlb_irqaction = { 606 .handler = dummy_handler, 607 .name = "tlb_flush" 608 }; 609 610 #endif 611 612 void 613 ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action) 614 { 615 unsigned int irq; 616 617 irq = vec; 618 BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL)); 619 irq_set_status_flags(irq, IRQ_PER_CPU); 620 irq_set_chip(irq, &irq_type_ia64_lsapic); 621 if (action) 622 setup_irq(irq, action); 623 irq_set_handler(irq, handle_percpu_irq); 624 } 625 626 void __init 627 ia64_native_register_ipi(void) 628 { 629 #ifdef CONFIG_SMP 630 register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction); 631 register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction); 632 register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction); 633 #endif 634 } 635 636 void __init 637 init_IRQ (void) 638 { 639 #ifdef CONFIG_ACPI 640 acpi_boot_init(); 641 #endif 642 ia64_register_ipi(); 643 register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL); 644 #ifdef CONFIG_SMP 645 #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG) 646 if (vector_domain_type != VECTOR_DOMAIN_NONE) 647 register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction); 648 #endif 649 #endif 650 #ifdef CONFIG_PERFMON 651 pfm_init_percpu(); 652 #endif 653 platform_irq_init(); 654 } 655 656 void 657 ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect) 658 { 659 void __iomem *ipi_addr; 660 unsigned long ipi_data; 661 unsigned long phys_cpu_id; 662 663 phys_cpu_id = cpu_physical_id(cpu); 664 665 /* 666 * cpu number is in 8bit ID and 8bit EID 667 */ 668 669 ipi_data = (delivery_mode << 8) | (vector & 0xff); 670 ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3)); 671 672 writeq(ipi_data, ipi_addr); 673 } 674