1c1cc1552SCatalin Marinas /* 2c1cc1552SCatalin Marinas * Based on arch/arm/mm/mmu.c 3c1cc1552SCatalin Marinas * 4c1cc1552SCatalin Marinas * Copyright (C) 1995-2005 Russell King 5c1cc1552SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 6c1cc1552SCatalin Marinas * 7c1cc1552SCatalin Marinas * This program is free software; you can redistribute it and/or modify 8c1cc1552SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 9c1cc1552SCatalin Marinas * published by the Free Software Foundation. 10c1cc1552SCatalin Marinas * 11c1cc1552SCatalin Marinas * This program is distributed in the hope that it will be useful, 12c1cc1552SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 13c1cc1552SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14c1cc1552SCatalin Marinas * GNU General Public License for more details. 15c1cc1552SCatalin Marinas * 16c1cc1552SCatalin Marinas * You should have received a copy of the GNU General Public License 17c1cc1552SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 18c1cc1552SCatalin Marinas */ 19c1cc1552SCatalin Marinas 20c1cc1552SCatalin Marinas #include <linux/export.h> 21c1cc1552SCatalin Marinas #include <linux/kernel.h> 22c1cc1552SCatalin Marinas #include <linux/errno.h> 23c1cc1552SCatalin Marinas #include <linux/init.h> 24c1cc1552SCatalin Marinas #include <linux/mman.h> 25c1cc1552SCatalin Marinas #include <linux/nodemask.h> 26c1cc1552SCatalin Marinas #include <linux/memblock.h> 27c1cc1552SCatalin Marinas #include <linux/fs.h> 282475ff9dSCatalin Marinas #include <linux/io.h> 29c1cc1552SCatalin Marinas 30c1cc1552SCatalin Marinas #include <asm/cputype.h> 31c1cc1552SCatalin Marinas #include <asm/sections.h> 32c1cc1552SCatalin Marinas #include <asm/setup.h> 33c1cc1552SCatalin Marinas #include <asm/sizes.h> 34c1cc1552SCatalin Marinas #include <asm/tlb.h> 35c1cc1552SCatalin Marinas #include <asm/mmu_context.h> 36c1cc1552SCatalin Marinas 37c1cc1552SCatalin Marinas #include "mm.h" 38c1cc1552SCatalin Marinas 39c1cc1552SCatalin Marinas /* 40c1cc1552SCatalin Marinas * Empty_zero_page is a special page that is used for zero-initialized data 41c1cc1552SCatalin Marinas * and COW. 42c1cc1552SCatalin Marinas */ 43c1cc1552SCatalin Marinas struct page *empty_zero_page; 44c1cc1552SCatalin Marinas EXPORT_SYMBOL(empty_zero_page); 45c1cc1552SCatalin Marinas 46c1cc1552SCatalin Marinas pgprot_t pgprot_default; 47c1cc1552SCatalin Marinas EXPORT_SYMBOL(pgprot_default); 48c1cc1552SCatalin Marinas 49c1cc1552SCatalin Marinas static pmdval_t prot_sect_kernel; 50c1cc1552SCatalin Marinas 51c1cc1552SCatalin Marinas struct cachepolicy { 52c1cc1552SCatalin Marinas const char policy[16]; 53c1cc1552SCatalin Marinas u64 mair; 54c1cc1552SCatalin Marinas u64 tcr; 55c1cc1552SCatalin Marinas }; 56c1cc1552SCatalin Marinas 57c1cc1552SCatalin Marinas static struct cachepolicy cache_policies[] __initdata = { 58c1cc1552SCatalin Marinas { 59c1cc1552SCatalin Marinas .policy = "uncached", 60c1cc1552SCatalin Marinas .mair = 0x44, /* inner, outer non-cacheable */ 61c1cc1552SCatalin Marinas .tcr = TCR_IRGN_NC | TCR_ORGN_NC, 62c1cc1552SCatalin Marinas }, { 63c1cc1552SCatalin Marinas .policy = "writethrough", 64c1cc1552SCatalin Marinas .mair = 0xaa, /* inner, outer write-through, read-allocate */ 65c1cc1552SCatalin Marinas .tcr = TCR_IRGN_WT | TCR_ORGN_WT, 66c1cc1552SCatalin Marinas }, { 67c1cc1552SCatalin Marinas .policy = "writeback", 68c1cc1552SCatalin Marinas .mair = 0xee, /* inner, outer write-back, read-allocate */ 69c1cc1552SCatalin Marinas .tcr = TCR_IRGN_WBnWA | TCR_ORGN_WBnWA, 70c1cc1552SCatalin Marinas } 71c1cc1552SCatalin Marinas }; 72c1cc1552SCatalin Marinas 73c1cc1552SCatalin Marinas /* 74c1cc1552SCatalin Marinas * These are useful for identifying cache coherency problems by allowing the 75c1cc1552SCatalin Marinas * cache or the cache and writebuffer to be turned off. It changes the Normal 76c1cc1552SCatalin Marinas * memory caching attributes in the MAIR_EL1 register. 77c1cc1552SCatalin Marinas */ 78c1cc1552SCatalin Marinas static int __init early_cachepolicy(char *p) 79c1cc1552SCatalin Marinas { 80c1cc1552SCatalin Marinas int i; 81c1cc1552SCatalin Marinas u64 tmp; 82c1cc1552SCatalin Marinas 83c1cc1552SCatalin Marinas for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { 84c1cc1552SCatalin Marinas int len = strlen(cache_policies[i].policy); 85c1cc1552SCatalin Marinas 86c1cc1552SCatalin Marinas if (memcmp(p, cache_policies[i].policy, len) == 0) 87c1cc1552SCatalin Marinas break; 88c1cc1552SCatalin Marinas } 89c1cc1552SCatalin Marinas if (i == ARRAY_SIZE(cache_policies)) { 90c1cc1552SCatalin Marinas pr_err("ERROR: unknown or unsupported cache policy: %s\n", p); 91c1cc1552SCatalin Marinas return 0; 92c1cc1552SCatalin Marinas } 93c1cc1552SCatalin Marinas 94c1cc1552SCatalin Marinas flush_cache_all(); 95c1cc1552SCatalin Marinas 96c1cc1552SCatalin Marinas /* 97c1cc1552SCatalin Marinas * Modify MT_NORMAL attributes in MAIR_EL1. 98c1cc1552SCatalin Marinas */ 99c1cc1552SCatalin Marinas asm volatile( 100c1cc1552SCatalin Marinas " mrs %0, mair_el1\n" 101c1cc1552SCatalin Marinas " bfi %0, %1, #%2, #8\n" 102c1cc1552SCatalin Marinas " msr mair_el1, %0\n" 103c1cc1552SCatalin Marinas " isb\n" 104c1cc1552SCatalin Marinas : "=&r" (tmp) 105c1cc1552SCatalin Marinas : "r" (cache_policies[i].mair), "i" (MT_NORMAL * 8)); 106c1cc1552SCatalin Marinas 107c1cc1552SCatalin Marinas /* 108c1cc1552SCatalin Marinas * Modify TCR PTW cacheability attributes. 109c1cc1552SCatalin Marinas */ 110c1cc1552SCatalin Marinas asm volatile( 111c1cc1552SCatalin Marinas " mrs %0, tcr_el1\n" 112c1cc1552SCatalin Marinas " bic %0, %0, %2\n" 113c1cc1552SCatalin Marinas " orr %0, %0, %1\n" 114c1cc1552SCatalin Marinas " msr tcr_el1, %0\n" 115c1cc1552SCatalin Marinas " isb\n" 116c1cc1552SCatalin Marinas : "=&r" (tmp) 117c1cc1552SCatalin Marinas : "r" (cache_policies[i].tcr), "r" (TCR_IRGN_MASK | TCR_ORGN_MASK)); 118c1cc1552SCatalin Marinas 119c1cc1552SCatalin Marinas flush_cache_all(); 120c1cc1552SCatalin Marinas 121c1cc1552SCatalin Marinas return 0; 122c1cc1552SCatalin Marinas } 123c1cc1552SCatalin Marinas early_param("cachepolicy", early_cachepolicy); 124c1cc1552SCatalin Marinas 125c1cc1552SCatalin Marinas /* 126c1cc1552SCatalin Marinas * Adjust the PMD section entries according to the CPU in use. 127c1cc1552SCatalin Marinas */ 1280bf757c7SMark Salter void __init init_mem_pgprot(void) 129c1cc1552SCatalin Marinas { 130c1cc1552SCatalin Marinas pteval_t default_pgprot; 131c1cc1552SCatalin Marinas int i; 132c1cc1552SCatalin Marinas 133c1cc1552SCatalin Marinas default_pgprot = PTE_ATTRINDX(MT_NORMAL); 134c1cc1552SCatalin Marinas prot_sect_kernel = PMD_TYPE_SECT | PMD_SECT_AF | PMD_ATTRINDX(MT_NORMAL); 135c1cc1552SCatalin Marinas 136c1cc1552SCatalin Marinas #ifdef CONFIG_SMP 137c1cc1552SCatalin Marinas /* 138c1cc1552SCatalin Marinas * Mark memory with the "shared" attribute for SMP systems 139c1cc1552SCatalin Marinas */ 140c1cc1552SCatalin Marinas default_pgprot |= PTE_SHARED; 141c1cc1552SCatalin Marinas prot_sect_kernel |= PMD_SECT_S; 142c1cc1552SCatalin Marinas #endif 143c1cc1552SCatalin Marinas 144c1cc1552SCatalin Marinas for (i = 0; i < 16; i++) { 145c1cc1552SCatalin Marinas unsigned long v = pgprot_val(protection_map[i]); 146c1cc1552SCatalin Marinas protection_map[i] = __pgprot(v | default_pgprot); 147c1cc1552SCatalin Marinas } 148c1cc1552SCatalin Marinas 149c1cc1552SCatalin Marinas pgprot_default = __pgprot(PTE_TYPE_PAGE | PTE_AF | default_pgprot); 150c1cc1552SCatalin Marinas } 151c1cc1552SCatalin Marinas 152c1cc1552SCatalin Marinas pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 153c1cc1552SCatalin Marinas unsigned long size, pgprot_t vma_prot) 154c1cc1552SCatalin Marinas { 155c1cc1552SCatalin Marinas if (!pfn_valid(pfn)) 156c1cc1552SCatalin Marinas return pgprot_noncached(vma_prot); 157c1cc1552SCatalin Marinas else if (file->f_flags & O_SYNC) 158c1cc1552SCatalin Marinas return pgprot_writecombine(vma_prot); 159c1cc1552SCatalin Marinas return vma_prot; 160c1cc1552SCatalin Marinas } 161c1cc1552SCatalin Marinas EXPORT_SYMBOL(phys_mem_access_prot); 162c1cc1552SCatalin Marinas 163c1cc1552SCatalin Marinas static void __init *early_alloc(unsigned long sz) 164c1cc1552SCatalin Marinas { 165c1cc1552SCatalin Marinas void *ptr = __va(memblock_alloc(sz, sz)); 166c1cc1552SCatalin Marinas memset(ptr, 0, sz); 167c1cc1552SCatalin Marinas return ptr; 168c1cc1552SCatalin Marinas } 169c1cc1552SCatalin Marinas 170c1cc1552SCatalin Marinas static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, 171*d7ecbddfSMark Salter unsigned long end, unsigned long pfn, 172*d7ecbddfSMark Salter pgprot_t prot) 173c1cc1552SCatalin Marinas { 174c1cc1552SCatalin Marinas pte_t *pte; 175c1cc1552SCatalin Marinas 176c1cc1552SCatalin Marinas if (pmd_none(*pmd)) { 177c1cc1552SCatalin Marinas pte = early_alloc(PTRS_PER_PTE * sizeof(pte_t)); 178c1cc1552SCatalin Marinas __pmd_populate(pmd, __pa(pte), PMD_TYPE_TABLE); 179c1cc1552SCatalin Marinas } 180c1cc1552SCatalin Marinas BUG_ON(pmd_bad(*pmd)); 181c1cc1552SCatalin Marinas 182c1cc1552SCatalin Marinas pte = pte_offset_kernel(pmd, addr); 183c1cc1552SCatalin Marinas do { 184*d7ecbddfSMark Salter set_pte(pte, pfn_pte(pfn, prot)); 185c1cc1552SCatalin Marinas pfn++; 186c1cc1552SCatalin Marinas } while (pte++, addr += PAGE_SIZE, addr != end); 187c1cc1552SCatalin Marinas } 188c1cc1552SCatalin Marinas 189c1cc1552SCatalin Marinas static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, 190*d7ecbddfSMark Salter unsigned long end, phys_addr_t phys, 191*d7ecbddfSMark Salter int map_io) 192c1cc1552SCatalin Marinas { 193c1cc1552SCatalin Marinas pmd_t *pmd; 194c1cc1552SCatalin Marinas unsigned long next; 195*d7ecbddfSMark Salter pmdval_t prot_sect; 196*d7ecbddfSMark Salter pgprot_t prot_pte; 197*d7ecbddfSMark Salter 198*d7ecbddfSMark Salter if (map_io) { 199*d7ecbddfSMark Salter prot_sect = PMD_TYPE_SECT | PMD_SECT_AF | 200*d7ecbddfSMark Salter PMD_ATTRINDX(MT_DEVICE_nGnRE); 201*d7ecbddfSMark Salter prot_pte = __pgprot(PROT_DEVICE_nGnRE); 202*d7ecbddfSMark Salter } else { 203*d7ecbddfSMark Salter prot_sect = prot_sect_kernel; 204*d7ecbddfSMark Salter prot_pte = PAGE_KERNEL_EXEC; 205*d7ecbddfSMark Salter } 206c1cc1552SCatalin Marinas 207c1cc1552SCatalin Marinas /* 208c1cc1552SCatalin Marinas * Check for initial section mappings in the pgd/pud and remove them. 209c1cc1552SCatalin Marinas */ 210c1cc1552SCatalin Marinas if (pud_none(*pud) || pud_bad(*pud)) { 211c1cc1552SCatalin Marinas pmd = early_alloc(PTRS_PER_PMD * sizeof(pmd_t)); 212c1cc1552SCatalin Marinas pud_populate(&init_mm, pud, pmd); 213c1cc1552SCatalin Marinas } 214c1cc1552SCatalin Marinas 215c1cc1552SCatalin Marinas pmd = pmd_offset(pud, addr); 216c1cc1552SCatalin Marinas do { 217c1cc1552SCatalin Marinas next = pmd_addr_end(addr, end); 218c1cc1552SCatalin Marinas /* try section mapping first */ 219a55f9929SCatalin Marinas if (((addr | next | phys) & ~SECTION_MASK) == 0) { 220a55f9929SCatalin Marinas pmd_t old_pmd =*pmd; 221*d7ecbddfSMark Salter set_pmd(pmd, __pmd(phys | prot_sect)); 222a55f9929SCatalin Marinas /* 223a55f9929SCatalin Marinas * Check for previous table entries created during 224a55f9929SCatalin Marinas * boot (__create_page_tables) and flush them. 225a55f9929SCatalin Marinas */ 226a55f9929SCatalin Marinas if (!pmd_none(old_pmd)) 227a55f9929SCatalin Marinas flush_tlb_all(); 228a55f9929SCatalin Marinas } else { 229*d7ecbddfSMark Salter alloc_init_pte(pmd, addr, next, __phys_to_pfn(phys), 230*d7ecbddfSMark Salter prot_pte); 231a55f9929SCatalin Marinas } 232c1cc1552SCatalin Marinas phys += next - addr; 233c1cc1552SCatalin Marinas } while (pmd++, addr = next, addr != end); 234c1cc1552SCatalin Marinas } 235c1cc1552SCatalin Marinas 236c1cc1552SCatalin Marinas static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, 237*d7ecbddfSMark Salter unsigned long end, unsigned long phys, 238*d7ecbddfSMark Salter int map_io) 239c1cc1552SCatalin Marinas { 240c1cc1552SCatalin Marinas pud_t *pud = pud_offset(pgd, addr); 241c1cc1552SCatalin Marinas unsigned long next; 242c1cc1552SCatalin Marinas 243c1cc1552SCatalin Marinas do { 244c1cc1552SCatalin Marinas next = pud_addr_end(addr, end); 245*d7ecbddfSMark Salter alloc_init_pmd(pud, addr, next, phys, map_io); 246c1cc1552SCatalin Marinas phys += next - addr; 247c1cc1552SCatalin Marinas } while (pud++, addr = next, addr != end); 248c1cc1552SCatalin Marinas } 249c1cc1552SCatalin Marinas 250c1cc1552SCatalin Marinas /* 251c1cc1552SCatalin Marinas * Create the page directory entries and any necessary page tables for the 252c1cc1552SCatalin Marinas * mapping specified by 'md'. 253c1cc1552SCatalin Marinas */ 254*d7ecbddfSMark Salter static void __init __create_mapping(pgd_t *pgd, phys_addr_t phys, 255*d7ecbddfSMark Salter unsigned long virt, phys_addr_t size, 256*d7ecbddfSMark Salter int map_io) 257c1cc1552SCatalin Marinas { 258c1cc1552SCatalin Marinas unsigned long addr, length, end, next; 259c1cc1552SCatalin Marinas 260c1cc1552SCatalin Marinas addr = virt & PAGE_MASK; 261c1cc1552SCatalin Marinas length = PAGE_ALIGN(size + (virt & ~PAGE_MASK)); 262c1cc1552SCatalin Marinas 263c1cc1552SCatalin Marinas end = addr + length; 264c1cc1552SCatalin Marinas do { 265c1cc1552SCatalin Marinas next = pgd_addr_end(addr, end); 266*d7ecbddfSMark Salter alloc_init_pud(pgd, addr, next, phys, map_io); 267c1cc1552SCatalin Marinas phys += next - addr; 268c1cc1552SCatalin Marinas } while (pgd++, addr = next, addr != end); 269c1cc1552SCatalin Marinas } 270c1cc1552SCatalin Marinas 271*d7ecbddfSMark Salter static void __init create_mapping(phys_addr_t phys, unsigned long virt, 272*d7ecbddfSMark Salter phys_addr_t size) 273*d7ecbddfSMark Salter { 274*d7ecbddfSMark Salter if (virt < VMALLOC_START) { 275*d7ecbddfSMark Salter pr_warn("BUG: not creating mapping for %pa at 0x%016lx - outside kernel range\n", 276*d7ecbddfSMark Salter &phys, virt); 277*d7ecbddfSMark Salter return; 278*d7ecbddfSMark Salter } 279*d7ecbddfSMark Salter __create_mapping(pgd_offset_k(virt & PAGE_MASK), phys, virt, size, 0); 280*d7ecbddfSMark Salter } 281*d7ecbddfSMark Salter 282*d7ecbddfSMark Salter void __init create_id_mapping(phys_addr_t addr, phys_addr_t size, int map_io) 283*d7ecbddfSMark Salter { 284*d7ecbddfSMark Salter if ((addr >> PGDIR_SHIFT) >= ARRAY_SIZE(idmap_pg_dir)) { 285*d7ecbddfSMark Salter pr_warn("BUG: not creating id mapping for %pa\n", &addr); 286*d7ecbddfSMark Salter return; 287*d7ecbddfSMark Salter } 288*d7ecbddfSMark Salter __create_mapping(&idmap_pg_dir[pgd_index(addr)], 289*d7ecbddfSMark Salter addr, addr, size, map_io); 290*d7ecbddfSMark Salter } 291*d7ecbddfSMark Salter 292c1cc1552SCatalin Marinas static void __init map_mem(void) 293c1cc1552SCatalin Marinas { 294c1cc1552SCatalin Marinas struct memblock_region *reg; 295e25208f7SCatalin Marinas phys_addr_t limit; 296c1cc1552SCatalin Marinas 297f6bc87c3SSteve Capper /* 298f6bc87c3SSteve Capper * Temporarily limit the memblock range. We need to do this as 299f6bc87c3SSteve Capper * create_mapping requires puds, pmds and ptes to be allocated from 300f6bc87c3SSteve Capper * memory addressable from the initial direct kernel mapping. 301f6bc87c3SSteve Capper * 302f6bc87c3SSteve Capper * The initial direct kernel mapping, located at swapper_pg_dir, 303e25208f7SCatalin Marinas * gives us PGDIR_SIZE memory starting from PHYS_OFFSET (which must be 304e25208f7SCatalin Marinas * aligned to 2MB as per Documentation/arm64/booting.txt). 305f6bc87c3SSteve Capper */ 306e25208f7SCatalin Marinas limit = PHYS_OFFSET + PGDIR_SIZE; 307e25208f7SCatalin Marinas memblock_set_current_limit(limit); 308f6bc87c3SSteve Capper 309c1cc1552SCatalin Marinas /* map all the memory banks */ 310c1cc1552SCatalin Marinas for_each_memblock(memory, reg) { 311c1cc1552SCatalin Marinas phys_addr_t start = reg->base; 312c1cc1552SCatalin Marinas phys_addr_t end = start + reg->size; 313c1cc1552SCatalin Marinas 314c1cc1552SCatalin Marinas if (start >= end) 315c1cc1552SCatalin Marinas break; 316c1cc1552SCatalin Marinas 317e25208f7SCatalin Marinas #ifndef CONFIG_ARM64_64K_PAGES 318e25208f7SCatalin Marinas /* 319e25208f7SCatalin Marinas * For the first memory bank align the start address and 320e25208f7SCatalin Marinas * current memblock limit to prevent create_mapping() from 321e25208f7SCatalin Marinas * allocating pte page tables from unmapped memory. 322e25208f7SCatalin Marinas * When 64K pages are enabled, the pte page table for the 323e25208f7SCatalin Marinas * first PGDIR_SIZE is already present in swapper_pg_dir. 324e25208f7SCatalin Marinas */ 325e25208f7SCatalin Marinas if (start < limit) 326e25208f7SCatalin Marinas start = ALIGN(start, PMD_SIZE); 327e25208f7SCatalin Marinas if (end < limit) { 328e25208f7SCatalin Marinas limit = end & PMD_MASK; 329e25208f7SCatalin Marinas memblock_set_current_limit(limit); 330e25208f7SCatalin Marinas } 331e25208f7SCatalin Marinas #endif 332e25208f7SCatalin Marinas 333c1cc1552SCatalin Marinas create_mapping(start, __phys_to_virt(start), end - start); 334c1cc1552SCatalin Marinas } 335f6bc87c3SSteve Capper 336f6bc87c3SSteve Capper /* Limit no longer required. */ 337f6bc87c3SSteve Capper memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); 338c1cc1552SCatalin Marinas } 339c1cc1552SCatalin Marinas 340c1cc1552SCatalin Marinas /* 341c1cc1552SCatalin Marinas * paging_init() sets up the page tables, initialises the zone memory 342c1cc1552SCatalin Marinas * maps and sets up the zero page. 343c1cc1552SCatalin Marinas */ 344c1cc1552SCatalin Marinas void __init paging_init(void) 345c1cc1552SCatalin Marinas { 346c1cc1552SCatalin Marinas void *zero_page; 347c1cc1552SCatalin Marinas 348c1cc1552SCatalin Marinas map_mem(); 349c1cc1552SCatalin Marinas 350c1cc1552SCatalin Marinas /* 351c1cc1552SCatalin Marinas * Finally flush the caches and tlb to ensure that we're in a 352c1cc1552SCatalin Marinas * consistent state. 353c1cc1552SCatalin Marinas */ 354c1cc1552SCatalin Marinas flush_cache_all(); 355c1cc1552SCatalin Marinas flush_tlb_all(); 356c1cc1552SCatalin Marinas 357c1cc1552SCatalin Marinas /* allocate the zero page. */ 358c1cc1552SCatalin Marinas zero_page = early_alloc(PAGE_SIZE); 359c1cc1552SCatalin Marinas 360c1cc1552SCatalin Marinas bootmem_init(); 361c1cc1552SCatalin Marinas 362c1cc1552SCatalin Marinas empty_zero_page = virt_to_page(zero_page); 363c1cc1552SCatalin Marinas 364c1cc1552SCatalin Marinas /* 365c1cc1552SCatalin Marinas * TTBR0 is only used for the identity mapping at this stage. Make it 366c1cc1552SCatalin Marinas * point to zero page to avoid speculatively fetching new entries. 367c1cc1552SCatalin Marinas */ 368c1cc1552SCatalin Marinas cpu_set_reserved_ttbr0(); 369c1cc1552SCatalin Marinas flush_tlb_all(); 370c1cc1552SCatalin Marinas } 371c1cc1552SCatalin Marinas 372c1cc1552SCatalin Marinas /* 373c1cc1552SCatalin Marinas * Enable the identity mapping to allow the MMU disabling. 374c1cc1552SCatalin Marinas */ 375c1cc1552SCatalin Marinas void setup_mm_for_reboot(void) 376c1cc1552SCatalin Marinas { 377c1cc1552SCatalin Marinas cpu_switch_mm(idmap_pg_dir, &init_mm); 378c1cc1552SCatalin Marinas flush_tlb_all(); 379c1cc1552SCatalin Marinas } 380c1cc1552SCatalin Marinas 381c1cc1552SCatalin Marinas /* 382c1cc1552SCatalin Marinas * Check whether a kernel address is valid (derived from arch/x86/). 383c1cc1552SCatalin Marinas */ 384c1cc1552SCatalin Marinas int kern_addr_valid(unsigned long addr) 385c1cc1552SCatalin Marinas { 386c1cc1552SCatalin Marinas pgd_t *pgd; 387c1cc1552SCatalin Marinas pud_t *pud; 388c1cc1552SCatalin Marinas pmd_t *pmd; 389c1cc1552SCatalin Marinas pte_t *pte; 390c1cc1552SCatalin Marinas 391c1cc1552SCatalin Marinas if ((((long)addr) >> VA_BITS) != -1UL) 392c1cc1552SCatalin Marinas return 0; 393c1cc1552SCatalin Marinas 394c1cc1552SCatalin Marinas pgd = pgd_offset_k(addr); 395c1cc1552SCatalin Marinas if (pgd_none(*pgd)) 396c1cc1552SCatalin Marinas return 0; 397c1cc1552SCatalin Marinas 398c1cc1552SCatalin Marinas pud = pud_offset(pgd, addr); 399c1cc1552SCatalin Marinas if (pud_none(*pud)) 400c1cc1552SCatalin Marinas return 0; 401c1cc1552SCatalin Marinas 402c1cc1552SCatalin Marinas pmd = pmd_offset(pud, addr); 403c1cc1552SCatalin Marinas if (pmd_none(*pmd)) 404c1cc1552SCatalin Marinas return 0; 405c1cc1552SCatalin Marinas 406c1cc1552SCatalin Marinas pte = pte_offset_kernel(pmd, addr); 407c1cc1552SCatalin Marinas if (pte_none(*pte)) 408c1cc1552SCatalin Marinas return 0; 409c1cc1552SCatalin Marinas 410c1cc1552SCatalin Marinas return pfn_valid(pte_pfn(*pte)); 411c1cc1552SCatalin Marinas } 412c1cc1552SCatalin Marinas #ifdef CONFIG_SPARSEMEM_VMEMMAP 413c1cc1552SCatalin Marinas #ifdef CONFIG_ARM64_64K_PAGES 4140aad818bSJohannes Weiner int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node) 415c1cc1552SCatalin Marinas { 4160aad818bSJohannes Weiner return vmemmap_populate_basepages(start, end, node); 417c1cc1552SCatalin Marinas } 418c1cc1552SCatalin Marinas #else /* !CONFIG_ARM64_64K_PAGES */ 4190aad818bSJohannes Weiner int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node) 420c1cc1552SCatalin Marinas { 4210aad818bSJohannes Weiner unsigned long addr = start; 422c1cc1552SCatalin Marinas unsigned long next; 423c1cc1552SCatalin Marinas pgd_t *pgd; 424c1cc1552SCatalin Marinas pud_t *pud; 425c1cc1552SCatalin Marinas pmd_t *pmd; 426c1cc1552SCatalin Marinas 427c1cc1552SCatalin Marinas do { 428c1cc1552SCatalin Marinas next = pmd_addr_end(addr, end); 429c1cc1552SCatalin Marinas 430c1cc1552SCatalin Marinas pgd = vmemmap_pgd_populate(addr, node); 431c1cc1552SCatalin Marinas if (!pgd) 432c1cc1552SCatalin Marinas return -ENOMEM; 433c1cc1552SCatalin Marinas 434c1cc1552SCatalin Marinas pud = vmemmap_pud_populate(pgd, addr, node); 435c1cc1552SCatalin Marinas if (!pud) 436c1cc1552SCatalin Marinas return -ENOMEM; 437c1cc1552SCatalin Marinas 438c1cc1552SCatalin Marinas pmd = pmd_offset(pud, addr); 439c1cc1552SCatalin Marinas if (pmd_none(*pmd)) { 440c1cc1552SCatalin Marinas void *p = NULL; 441c1cc1552SCatalin Marinas 442c1cc1552SCatalin Marinas p = vmemmap_alloc_block_buf(PMD_SIZE, node); 443c1cc1552SCatalin Marinas if (!p) 444c1cc1552SCatalin Marinas return -ENOMEM; 445c1cc1552SCatalin Marinas 446c1cc1552SCatalin Marinas set_pmd(pmd, __pmd(__pa(p) | prot_sect_kernel)); 447c1cc1552SCatalin Marinas } else 448c1cc1552SCatalin Marinas vmemmap_verify((pte_t *)pmd, node, addr, next); 449c1cc1552SCatalin Marinas } while (addr = next, addr != end); 450c1cc1552SCatalin Marinas 451c1cc1552SCatalin Marinas return 0; 452c1cc1552SCatalin Marinas } 453c1cc1552SCatalin Marinas #endif /* CONFIG_ARM64_64K_PAGES */ 4540aad818bSJohannes Weiner void vmemmap_free(unsigned long start, unsigned long end) 4550197518cSTang Chen { 4560197518cSTang Chen } 457c1cc1552SCatalin Marinas #endif /* CONFIG_SPARSEMEM_VMEMMAP */ 458