xref: /openbmc/linux/arch/arm64/mm/mmu.c (revision 206a2a73a62d37c8b8f6ddd3180c202b2e7298ab)
1c1cc1552SCatalin Marinas /*
2c1cc1552SCatalin Marinas  * Based on arch/arm/mm/mmu.c
3c1cc1552SCatalin Marinas  *
4c1cc1552SCatalin Marinas  * Copyright (C) 1995-2005 Russell King
5c1cc1552SCatalin Marinas  * Copyright (C) 2012 ARM Ltd.
6c1cc1552SCatalin Marinas  *
7c1cc1552SCatalin Marinas  * This program is free software; you can redistribute it and/or modify
8c1cc1552SCatalin Marinas  * it under the terms of the GNU General Public License version 2 as
9c1cc1552SCatalin Marinas  * published by the Free Software Foundation.
10c1cc1552SCatalin Marinas  *
11c1cc1552SCatalin Marinas  * This program is distributed in the hope that it will be useful,
12c1cc1552SCatalin Marinas  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13c1cc1552SCatalin Marinas  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14c1cc1552SCatalin Marinas  * GNU General Public License for more details.
15c1cc1552SCatalin Marinas  *
16c1cc1552SCatalin Marinas  * You should have received a copy of the GNU General Public License
17c1cc1552SCatalin Marinas  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
18c1cc1552SCatalin Marinas  */
19c1cc1552SCatalin Marinas 
20c1cc1552SCatalin Marinas #include <linux/export.h>
21c1cc1552SCatalin Marinas #include <linux/kernel.h>
22c1cc1552SCatalin Marinas #include <linux/errno.h>
23c1cc1552SCatalin Marinas #include <linux/init.h>
24c1cc1552SCatalin Marinas #include <linux/mman.h>
25c1cc1552SCatalin Marinas #include <linux/nodemask.h>
26c1cc1552SCatalin Marinas #include <linux/memblock.h>
27c1cc1552SCatalin Marinas #include <linux/fs.h>
282475ff9dSCatalin Marinas #include <linux/io.h>
29c1cc1552SCatalin Marinas 
30c1cc1552SCatalin Marinas #include <asm/cputype.h>
31c1cc1552SCatalin Marinas #include <asm/sections.h>
32c1cc1552SCatalin Marinas #include <asm/setup.h>
33c1cc1552SCatalin Marinas #include <asm/sizes.h>
34c1cc1552SCatalin Marinas #include <asm/tlb.h>
35c1cc1552SCatalin Marinas #include <asm/mmu_context.h>
36c1cc1552SCatalin Marinas 
37c1cc1552SCatalin Marinas #include "mm.h"
38c1cc1552SCatalin Marinas 
39c1cc1552SCatalin Marinas /*
40c1cc1552SCatalin Marinas  * Empty_zero_page is a special page that is used for zero-initialized data
41c1cc1552SCatalin Marinas  * and COW.
42c1cc1552SCatalin Marinas  */
43c1cc1552SCatalin Marinas struct page *empty_zero_page;
44c1cc1552SCatalin Marinas EXPORT_SYMBOL(empty_zero_page);
45c1cc1552SCatalin Marinas 
46c1cc1552SCatalin Marinas struct cachepolicy {
47c1cc1552SCatalin Marinas 	const char	policy[16];
48c1cc1552SCatalin Marinas 	u64		mair;
49c1cc1552SCatalin Marinas 	u64		tcr;
50c1cc1552SCatalin Marinas };
51c1cc1552SCatalin Marinas 
52c1cc1552SCatalin Marinas static struct cachepolicy cache_policies[] __initdata = {
53c1cc1552SCatalin Marinas 	{
54c1cc1552SCatalin Marinas 		.policy		= "uncached",
55c1cc1552SCatalin Marinas 		.mair		= 0x44,			/* inner, outer non-cacheable */
56c1cc1552SCatalin Marinas 		.tcr		= TCR_IRGN_NC | TCR_ORGN_NC,
57c1cc1552SCatalin Marinas 	}, {
58c1cc1552SCatalin Marinas 		.policy		= "writethrough",
59c1cc1552SCatalin Marinas 		.mair		= 0xaa,			/* inner, outer write-through, read-allocate */
60c1cc1552SCatalin Marinas 		.tcr		= TCR_IRGN_WT | TCR_ORGN_WT,
61c1cc1552SCatalin Marinas 	}, {
62c1cc1552SCatalin Marinas 		.policy		= "writeback",
63c1cc1552SCatalin Marinas 		.mair		= 0xee,			/* inner, outer write-back, read-allocate */
64c1cc1552SCatalin Marinas 		.tcr		= TCR_IRGN_WBnWA | TCR_ORGN_WBnWA,
65c1cc1552SCatalin Marinas 	}
66c1cc1552SCatalin Marinas };
67c1cc1552SCatalin Marinas 
68c1cc1552SCatalin Marinas /*
69c1cc1552SCatalin Marinas  * These are useful for identifying cache coherency problems by allowing the
70c1cc1552SCatalin Marinas  * cache or the cache and writebuffer to be turned off. It changes the Normal
71c1cc1552SCatalin Marinas  * memory caching attributes in the MAIR_EL1 register.
72c1cc1552SCatalin Marinas  */
73c1cc1552SCatalin Marinas static int __init early_cachepolicy(char *p)
74c1cc1552SCatalin Marinas {
75c1cc1552SCatalin Marinas 	int i;
76c1cc1552SCatalin Marinas 	u64 tmp;
77c1cc1552SCatalin Marinas 
78c1cc1552SCatalin Marinas 	for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
79c1cc1552SCatalin Marinas 		int len = strlen(cache_policies[i].policy);
80c1cc1552SCatalin Marinas 
81c1cc1552SCatalin Marinas 		if (memcmp(p, cache_policies[i].policy, len) == 0)
82c1cc1552SCatalin Marinas 			break;
83c1cc1552SCatalin Marinas 	}
84c1cc1552SCatalin Marinas 	if (i == ARRAY_SIZE(cache_policies)) {
85c1cc1552SCatalin Marinas 		pr_err("ERROR: unknown or unsupported cache policy: %s\n", p);
86c1cc1552SCatalin Marinas 		return 0;
87c1cc1552SCatalin Marinas 	}
88c1cc1552SCatalin Marinas 
89c1cc1552SCatalin Marinas 	flush_cache_all();
90c1cc1552SCatalin Marinas 
91c1cc1552SCatalin Marinas 	/*
92c1cc1552SCatalin Marinas 	 * Modify MT_NORMAL attributes in MAIR_EL1.
93c1cc1552SCatalin Marinas 	 */
94c1cc1552SCatalin Marinas 	asm volatile(
95c1cc1552SCatalin Marinas 	"	mrs	%0, mair_el1\n"
96c1cc1552SCatalin Marinas 	"	bfi	%0, %1, #%2, #8\n"
97c1cc1552SCatalin Marinas 	"	msr	mair_el1, %0\n"
98c1cc1552SCatalin Marinas 	"	isb\n"
99c1cc1552SCatalin Marinas 	: "=&r" (tmp)
100c1cc1552SCatalin Marinas 	: "r" (cache_policies[i].mair), "i" (MT_NORMAL * 8));
101c1cc1552SCatalin Marinas 
102c1cc1552SCatalin Marinas 	/*
103c1cc1552SCatalin Marinas 	 * Modify TCR PTW cacheability attributes.
104c1cc1552SCatalin Marinas 	 */
105c1cc1552SCatalin Marinas 	asm volatile(
106c1cc1552SCatalin Marinas 	"	mrs	%0, tcr_el1\n"
107c1cc1552SCatalin Marinas 	"	bic	%0, %0, %2\n"
108c1cc1552SCatalin Marinas 	"	orr	%0, %0, %1\n"
109c1cc1552SCatalin Marinas 	"	msr	tcr_el1, %0\n"
110c1cc1552SCatalin Marinas 	"	isb\n"
111c1cc1552SCatalin Marinas 	: "=&r" (tmp)
112c1cc1552SCatalin Marinas 	: "r" (cache_policies[i].tcr), "r" (TCR_IRGN_MASK | TCR_ORGN_MASK));
113c1cc1552SCatalin Marinas 
114c1cc1552SCatalin Marinas 	flush_cache_all();
115c1cc1552SCatalin Marinas 
116c1cc1552SCatalin Marinas 	return 0;
117c1cc1552SCatalin Marinas }
118c1cc1552SCatalin Marinas early_param("cachepolicy", early_cachepolicy);
119c1cc1552SCatalin Marinas 
120c1cc1552SCatalin Marinas pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
121c1cc1552SCatalin Marinas 			      unsigned long size, pgprot_t vma_prot)
122c1cc1552SCatalin Marinas {
123c1cc1552SCatalin Marinas 	if (!pfn_valid(pfn))
124c1cc1552SCatalin Marinas 		return pgprot_noncached(vma_prot);
125c1cc1552SCatalin Marinas 	else if (file->f_flags & O_SYNC)
126c1cc1552SCatalin Marinas 		return pgprot_writecombine(vma_prot);
127c1cc1552SCatalin Marinas 	return vma_prot;
128c1cc1552SCatalin Marinas }
129c1cc1552SCatalin Marinas EXPORT_SYMBOL(phys_mem_access_prot);
130c1cc1552SCatalin Marinas 
131c1cc1552SCatalin Marinas static void __init *early_alloc(unsigned long sz)
132c1cc1552SCatalin Marinas {
133c1cc1552SCatalin Marinas 	void *ptr = __va(memblock_alloc(sz, sz));
134c1cc1552SCatalin Marinas 	memset(ptr, 0, sz);
135c1cc1552SCatalin Marinas 	return ptr;
136c1cc1552SCatalin Marinas }
137c1cc1552SCatalin Marinas 
138c1cc1552SCatalin Marinas static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
139c1cc1552SCatalin Marinas 				  unsigned long end, unsigned long pfn)
140c1cc1552SCatalin Marinas {
141c1cc1552SCatalin Marinas 	pte_t *pte;
142c1cc1552SCatalin Marinas 
143c1cc1552SCatalin Marinas 	if (pmd_none(*pmd)) {
144c1cc1552SCatalin Marinas 		pte = early_alloc(PTRS_PER_PTE * sizeof(pte_t));
145c1cc1552SCatalin Marinas 		__pmd_populate(pmd, __pa(pte), PMD_TYPE_TABLE);
146c1cc1552SCatalin Marinas 	}
147c1cc1552SCatalin Marinas 	BUG_ON(pmd_bad(*pmd));
148c1cc1552SCatalin Marinas 
149c1cc1552SCatalin Marinas 	pte = pte_offset_kernel(pmd, addr);
150c1cc1552SCatalin Marinas 	do {
151c1cc1552SCatalin Marinas 		set_pte(pte, pfn_pte(pfn, PAGE_KERNEL_EXEC));
152c1cc1552SCatalin Marinas 		pfn++;
153c1cc1552SCatalin Marinas 	} while (pte++, addr += PAGE_SIZE, addr != end);
154c1cc1552SCatalin Marinas }
155c1cc1552SCatalin Marinas 
156c1cc1552SCatalin Marinas static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
157c1cc1552SCatalin Marinas 				  unsigned long end, phys_addr_t phys)
158c1cc1552SCatalin Marinas {
159c1cc1552SCatalin Marinas 	pmd_t *pmd;
160c1cc1552SCatalin Marinas 	unsigned long next;
161c1cc1552SCatalin Marinas 
162c1cc1552SCatalin Marinas 	/*
163c1cc1552SCatalin Marinas 	 * Check for initial section mappings in the pgd/pud and remove them.
164c1cc1552SCatalin Marinas 	 */
165c1cc1552SCatalin Marinas 	if (pud_none(*pud) || pud_bad(*pud)) {
166c1cc1552SCatalin Marinas 		pmd = early_alloc(PTRS_PER_PMD * sizeof(pmd_t));
167c1cc1552SCatalin Marinas 		pud_populate(&init_mm, pud, pmd);
168c1cc1552SCatalin Marinas 	}
169c1cc1552SCatalin Marinas 
170c1cc1552SCatalin Marinas 	pmd = pmd_offset(pud, addr);
171c1cc1552SCatalin Marinas 	do {
172c1cc1552SCatalin Marinas 		next = pmd_addr_end(addr, end);
173c1cc1552SCatalin Marinas 		/* try section mapping first */
174a55f9929SCatalin Marinas 		if (((addr | next | phys) & ~SECTION_MASK) == 0) {
175a55f9929SCatalin Marinas 			pmd_t old_pmd =*pmd;
176a501e324SCatalin Marinas 			set_pmd(pmd, __pmd(phys | PROT_SECT_NORMAL_EXEC));
177a55f9929SCatalin Marinas 			/*
178a55f9929SCatalin Marinas 			 * Check for previous table entries created during
179a55f9929SCatalin Marinas 			 * boot (__create_page_tables) and flush them.
180a55f9929SCatalin Marinas 			 */
181a55f9929SCatalin Marinas 			if (!pmd_none(old_pmd))
182a55f9929SCatalin Marinas 				flush_tlb_all();
183a55f9929SCatalin Marinas 		} else {
184c1cc1552SCatalin Marinas 			alloc_init_pte(pmd, addr, next, __phys_to_pfn(phys));
185a55f9929SCatalin Marinas 		}
186c1cc1552SCatalin Marinas 		phys += next - addr;
187c1cc1552SCatalin Marinas 	} while (pmd++, addr = next, addr != end);
188c1cc1552SCatalin Marinas }
189c1cc1552SCatalin Marinas 
190c1cc1552SCatalin Marinas static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
191c1cc1552SCatalin Marinas 				  unsigned long end, unsigned long phys)
192c1cc1552SCatalin Marinas {
193c1cc1552SCatalin Marinas 	pud_t *pud = pud_offset(pgd, addr);
194c1cc1552SCatalin Marinas 	unsigned long next;
195c1cc1552SCatalin Marinas 
196c1cc1552SCatalin Marinas 	do {
197c1cc1552SCatalin Marinas 		next = pud_addr_end(addr, end);
198*206a2a73SSteve Capper 
199*206a2a73SSteve Capper 		/*
200*206a2a73SSteve Capper 		 * For 4K granule only, attempt to put down a 1GB block
201*206a2a73SSteve Capper 		 */
202*206a2a73SSteve Capper 		if ((PAGE_SHIFT == 12) &&
203*206a2a73SSteve Capper 		    ((addr | next | phys) & ~PUD_MASK) == 0) {
204*206a2a73SSteve Capper 			pud_t old_pud = *pud;
205*206a2a73SSteve Capper 			set_pud(pud, __pud(phys | PROT_SECT_NORMAL_EXEC));
206*206a2a73SSteve Capper 
207*206a2a73SSteve Capper 			/*
208*206a2a73SSteve Capper 			 * If we have an old value for a pud, it will
209*206a2a73SSteve Capper 			 * be pointing to a pmd table that we no longer
210*206a2a73SSteve Capper 			 * need (from swapper_pg_dir).
211*206a2a73SSteve Capper 			 *
212*206a2a73SSteve Capper 			 * Look up the old pmd table and free it.
213*206a2a73SSteve Capper 			 */
214*206a2a73SSteve Capper 			if (!pud_none(old_pud)) {
215*206a2a73SSteve Capper 				phys_addr_t table = __pa(pmd_offset(&old_pud, 0));
216*206a2a73SSteve Capper 				memblock_free(table, PAGE_SIZE);
217*206a2a73SSteve Capper 				flush_tlb_all();
218*206a2a73SSteve Capper 			}
219*206a2a73SSteve Capper 		} else {
220c1cc1552SCatalin Marinas 			alloc_init_pmd(pud, addr, next, phys);
221*206a2a73SSteve Capper 		}
222c1cc1552SCatalin Marinas 		phys += next - addr;
223c1cc1552SCatalin Marinas 	} while (pud++, addr = next, addr != end);
224c1cc1552SCatalin Marinas }
225c1cc1552SCatalin Marinas 
226c1cc1552SCatalin Marinas /*
227c1cc1552SCatalin Marinas  * Create the page directory entries and any necessary page tables for the
228c1cc1552SCatalin Marinas  * mapping specified by 'md'.
229c1cc1552SCatalin Marinas  */
230c1cc1552SCatalin Marinas static void __init create_mapping(phys_addr_t phys, unsigned long virt,
231c1cc1552SCatalin Marinas 				  phys_addr_t size)
232c1cc1552SCatalin Marinas {
233c1cc1552SCatalin Marinas 	unsigned long addr, length, end, next;
234c1cc1552SCatalin Marinas 	pgd_t *pgd;
235c1cc1552SCatalin Marinas 
236c1cc1552SCatalin Marinas 	if (virt < VMALLOC_START) {
237c1cc1552SCatalin Marinas 		pr_warning("BUG: not creating mapping for 0x%016llx at 0x%016lx - outside kernel range\n",
238c1cc1552SCatalin Marinas 			   phys, virt);
239c1cc1552SCatalin Marinas 		return;
240c1cc1552SCatalin Marinas 	}
241c1cc1552SCatalin Marinas 
242c1cc1552SCatalin Marinas 	addr = virt & PAGE_MASK;
243c1cc1552SCatalin Marinas 	length = PAGE_ALIGN(size + (virt & ~PAGE_MASK));
244c1cc1552SCatalin Marinas 
245c1cc1552SCatalin Marinas 	pgd = pgd_offset_k(addr);
246c1cc1552SCatalin Marinas 	end = addr + length;
247c1cc1552SCatalin Marinas 	do {
248c1cc1552SCatalin Marinas 		next = pgd_addr_end(addr, end);
249c1cc1552SCatalin Marinas 		alloc_init_pud(pgd, addr, next, phys);
250c1cc1552SCatalin Marinas 		phys += next - addr;
251c1cc1552SCatalin Marinas 	} while (pgd++, addr = next, addr != end);
252c1cc1552SCatalin Marinas }
253c1cc1552SCatalin Marinas 
254c1cc1552SCatalin Marinas static void __init map_mem(void)
255c1cc1552SCatalin Marinas {
256c1cc1552SCatalin Marinas 	struct memblock_region *reg;
257e25208f7SCatalin Marinas 	phys_addr_t limit;
258c1cc1552SCatalin Marinas 
259f6bc87c3SSteve Capper 	/*
260f6bc87c3SSteve Capper 	 * Temporarily limit the memblock range. We need to do this as
261f6bc87c3SSteve Capper 	 * create_mapping requires puds, pmds and ptes to be allocated from
262f6bc87c3SSteve Capper 	 * memory addressable from the initial direct kernel mapping.
263f6bc87c3SSteve Capper 	 *
264f6bc87c3SSteve Capper 	 * The initial direct kernel mapping, located at swapper_pg_dir,
265e25208f7SCatalin Marinas 	 * gives us PGDIR_SIZE memory starting from PHYS_OFFSET (which must be
266e25208f7SCatalin Marinas 	 * aligned to 2MB as per Documentation/arm64/booting.txt).
267f6bc87c3SSteve Capper 	 */
268e25208f7SCatalin Marinas 	limit = PHYS_OFFSET + PGDIR_SIZE;
269e25208f7SCatalin Marinas 	memblock_set_current_limit(limit);
270f6bc87c3SSteve Capper 
271c1cc1552SCatalin Marinas 	/* map all the memory banks */
272c1cc1552SCatalin Marinas 	for_each_memblock(memory, reg) {
273c1cc1552SCatalin Marinas 		phys_addr_t start = reg->base;
274c1cc1552SCatalin Marinas 		phys_addr_t end = start + reg->size;
275c1cc1552SCatalin Marinas 
276c1cc1552SCatalin Marinas 		if (start >= end)
277c1cc1552SCatalin Marinas 			break;
278c1cc1552SCatalin Marinas 
279e25208f7SCatalin Marinas #ifndef CONFIG_ARM64_64K_PAGES
280e25208f7SCatalin Marinas 		/*
281e25208f7SCatalin Marinas 		 * For the first memory bank align the start address and
282e25208f7SCatalin Marinas 		 * current memblock limit to prevent create_mapping() from
283e25208f7SCatalin Marinas 		 * allocating pte page tables from unmapped memory.
284e25208f7SCatalin Marinas 		 * When 64K pages are enabled, the pte page table for the
285e25208f7SCatalin Marinas 		 * first PGDIR_SIZE is already present in swapper_pg_dir.
286e25208f7SCatalin Marinas 		 */
287e25208f7SCatalin Marinas 		if (start < limit)
288e25208f7SCatalin Marinas 			start = ALIGN(start, PMD_SIZE);
289e25208f7SCatalin Marinas 		if (end < limit) {
290e25208f7SCatalin Marinas 			limit = end & PMD_MASK;
291e25208f7SCatalin Marinas 			memblock_set_current_limit(limit);
292e25208f7SCatalin Marinas 		}
293e25208f7SCatalin Marinas #endif
294e25208f7SCatalin Marinas 
295c1cc1552SCatalin Marinas 		create_mapping(start, __phys_to_virt(start), end - start);
296c1cc1552SCatalin Marinas 	}
297f6bc87c3SSteve Capper 
298f6bc87c3SSteve Capper 	/* Limit no longer required. */
299f6bc87c3SSteve Capper 	memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
300c1cc1552SCatalin Marinas }
301c1cc1552SCatalin Marinas 
302c1cc1552SCatalin Marinas /*
303c1cc1552SCatalin Marinas  * paging_init() sets up the page tables, initialises the zone memory
304c1cc1552SCatalin Marinas  * maps and sets up the zero page.
305c1cc1552SCatalin Marinas  */
306c1cc1552SCatalin Marinas void __init paging_init(void)
307c1cc1552SCatalin Marinas {
308c1cc1552SCatalin Marinas 	void *zero_page;
309c1cc1552SCatalin Marinas 
310c1cc1552SCatalin Marinas 	map_mem();
311c1cc1552SCatalin Marinas 
312c1cc1552SCatalin Marinas 	/*
313c1cc1552SCatalin Marinas 	 * Finally flush the caches and tlb to ensure that we're in a
314c1cc1552SCatalin Marinas 	 * consistent state.
315c1cc1552SCatalin Marinas 	 */
316c1cc1552SCatalin Marinas 	flush_cache_all();
317c1cc1552SCatalin Marinas 	flush_tlb_all();
318c1cc1552SCatalin Marinas 
319c1cc1552SCatalin Marinas 	/* allocate the zero page. */
320c1cc1552SCatalin Marinas 	zero_page = early_alloc(PAGE_SIZE);
321c1cc1552SCatalin Marinas 
322c1cc1552SCatalin Marinas 	bootmem_init();
323c1cc1552SCatalin Marinas 
324c1cc1552SCatalin Marinas 	empty_zero_page = virt_to_page(zero_page);
325c1cc1552SCatalin Marinas 
326c1cc1552SCatalin Marinas 	/*
327c1cc1552SCatalin Marinas 	 * TTBR0 is only used for the identity mapping at this stage. Make it
328c1cc1552SCatalin Marinas 	 * point to zero page to avoid speculatively fetching new entries.
329c1cc1552SCatalin Marinas 	 */
330c1cc1552SCatalin Marinas 	cpu_set_reserved_ttbr0();
331c1cc1552SCatalin Marinas 	flush_tlb_all();
332c1cc1552SCatalin Marinas }
333c1cc1552SCatalin Marinas 
334c1cc1552SCatalin Marinas /*
335c1cc1552SCatalin Marinas  * Enable the identity mapping to allow the MMU disabling.
336c1cc1552SCatalin Marinas  */
337c1cc1552SCatalin Marinas void setup_mm_for_reboot(void)
338c1cc1552SCatalin Marinas {
339c1cc1552SCatalin Marinas 	cpu_switch_mm(idmap_pg_dir, &init_mm);
340c1cc1552SCatalin Marinas 	flush_tlb_all();
341c1cc1552SCatalin Marinas }
342c1cc1552SCatalin Marinas 
343c1cc1552SCatalin Marinas /*
344c1cc1552SCatalin Marinas  * Check whether a kernel address is valid (derived from arch/x86/).
345c1cc1552SCatalin Marinas  */
346c1cc1552SCatalin Marinas int kern_addr_valid(unsigned long addr)
347c1cc1552SCatalin Marinas {
348c1cc1552SCatalin Marinas 	pgd_t *pgd;
349c1cc1552SCatalin Marinas 	pud_t *pud;
350c1cc1552SCatalin Marinas 	pmd_t *pmd;
351c1cc1552SCatalin Marinas 	pte_t *pte;
352c1cc1552SCatalin Marinas 
353c1cc1552SCatalin Marinas 	if ((((long)addr) >> VA_BITS) != -1UL)
354c1cc1552SCatalin Marinas 		return 0;
355c1cc1552SCatalin Marinas 
356c1cc1552SCatalin Marinas 	pgd = pgd_offset_k(addr);
357c1cc1552SCatalin Marinas 	if (pgd_none(*pgd))
358c1cc1552SCatalin Marinas 		return 0;
359c1cc1552SCatalin Marinas 
360c1cc1552SCatalin Marinas 	pud = pud_offset(pgd, addr);
361c1cc1552SCatalin Marinas 	if (pud_none(*pud))
362c1cc1552SCatalin Marinas 		return 0;
363c1cc1552SCatalin Marinas 
364*206a2a73SSteve Capper 	if (pud_sect(*pud))
365*206a2a73SSteve Capper 		return pfn_valid(pud_pfn(*pud));
366*206a2a73SSteve Capper 
367c1cc1552SCatalin Marinas 	pmd = pmd_offset(pud, addr);
368c1cc1552SCatalin Marinas 	if (pmd_none(*pmd))
369c1cc1552SCatalin Marinas 		return 0;
370c1cc1552SCatalin Marinas 
371da6e4cb6SDave Anderson 	if (pmd_sect(*pmd))
372da6e4cb6SDave Anderson 		return pfn_valid(pmd_pfn(*pmd));
373da6e4cb6SDave Anderson 
374c1cc1552SCatalin Marinas 	pte = pte_offset_kernel(pmd, addr);
375c1cc1552SCatalin Marinas 	if (pte_none(*pte))
376c1cc1552SCatalin Marinas 		return 0;
377c1cc1552SCatalin Marinas 
378c1cc1552SCatalin Marinas 	return pfn_valid(pte_pfn(*pte));
379c1cc1552SCatalin Marinas }
380c1cc1552SCatalin Marinas #ifdef CONFIG_SPARSEMEM_VMEMMAP
381c1cc1552SCatalin Marinas #ifdef CONFIG_ARM64_64K_PAGES
3820aad818bSJohannes Weiner int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node)
383c1cc1552SCatalin Marinas {
3840aad818bSJohannes Weiner 	return vmemmap_populate_basepages(start, end, node);
385c1cc1552SCatalin Marinas }
386c1cc1552SCatalin Marinas #else	/* !CONFIG_ARM64_64K_PAGES */
3870aad818bSJohannes Weiner int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node)
388c1cc1552SCatalin Marinas {
3890aad818bSJohannes Weiner 	unsigned long addr = start;
390c1cc1552SCatalin Marinas 	unsigned long next;
391c1cc1552SCatalin Marinas 	pgd_t *pgd;
392c1cc1552SCatalin Marinas 	pud_t *pud;
393c1cc1552SCatalin Marinas 	pmd_t *pmd;
394c1cc1552SCatalin Marinas 
395c1cc1552SCatalin Marinas 	do {
396c1cc1552SCatalin Marinas 		next = pmd_addr_end(addr, end);
397c1cc1552SCatalin Marinas 
398c1cc1552SCatalin Marinas 		pgd = vmemmap_pgd_populate(addr, node);
399c1cc1552SCatalin Marinas 		if (!pgd)
400c1cc1552SCatalin Marinas 			return -ENOMEM;
401c1cc1552SCatalin Marinas 
402c1cc1552SCatalin Marinas 		pud = vmemmap_pud_populate(pgd, addr, node);
403c1cc1552SCatalin Marinas 		if (!pud)
404c1cc1552SCatalin Marinas 			return -ENOMEM;
405c1cc1552SCatalin Marinas 
406c1cc1552SCatalin Marinas 		pmd = pmd_offset(pud, addr);
407c1cc1552SCatalin Marinas 		if (pmd_none(*pmd)) {
408c1cc1552SCatalin Marinas 			void *p = NULL;
409c1cc1552SCatalin Marinas 
410c1cc1552SCatalin Marinas 			p = vmemmap_alloc_block_buf(PMD_SIZE, node);
411c1cc1552SCatalin Marinas 			if (!p)
412c1cc1552SCatalin Marinas 				return -ENOMEM;
413c1cc1552SCatalin Marinas 
414a501e324SCatalin Marinas 			set_pmd(pmd, __pmd(__pa(p) | PROT_SECT_NORMAL));
415c1cc1552SCatalin Marinas 		} else
416c1cc1552SCatalin Marinas 			vmemmap_verify((pte_t *)pmd, node, addr, next);
417c1cc1552SCatalin Marinas 	} while (addr = next, addr != end);
418c1cc1552SCatalin Marinas 
419c1cc1552SCatalin Marinas 	return 0;
420c1cc1552SCatalin Marinas }
421c1cc1552SCatalin Marinas #endif	/* CONFIG_ARM64_64K_PAGES */
4220aad818bSJohannes Weiner void vmemmap_free(unsigned long start, unsigned long end)
4230197518cSTang Chen {
4240197518cSTang Chen }
425c1cc1552SCatalin Marinas #endif	/* CONFIG_SPARSEMEM_VMEMMAP */
426