1c1cc1552SCatalin Marinas /* 2c1cc1552SCatalin Marinas * Based on arch/arm/mm/mmu.c 3c1cc1552SCatalin Marinas * 4c1cc1552SCatalin Marinas * Copyright (C) 1995-2005 Russell King 5c1cc1552SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 6c1cc1552SCatalin Marinas * 7c1cc1552SCatalin Marinas * This program is free software; you can redistribute it and/or modify 8c1cc1552SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 9c1cc1552SCatalin Marinas * published by the Free Software Foundation. 10c1cc1552SCatalin Marinas * 11c1cc1552SCatalin Marinas * This program is distributed in the hope that it will be useful, 12c1cc1552SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 13c1cc1552SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14c1cc1552SCatalin Marinas * GNU General Public License for more details. 15c1cc1552SCatalin Marinas * 16c1cc1552SCatalin Marinas * You should have received a copy of the GNU General Public License 17c1cc1552SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 18c1cc1552SCatalin Marinas */ 19c1cc1552SCatalin Marinas 20c1cc1552SCatalin Marinas #include <linux/export.h> 21c1cc1552SCatalin Marinas #include <linux/kernel.h> 22c1cc1552SCatalin Marinas #include <linux/errno.h> 23c1cc1552SCatalin Marinas #include <linux/init.h> 24c1cc1552SCatalin Marinas #include <linux/mman.h> 25c1cc1552SCatalin Marinas #include <linux/nodemask.h> 26c1cc1552SCatalin Marinas #include <linux/memblock.h> 27c1cc1552SCatalin Marinas #include <linux/fs.h> 282475ff9dSCatalin Marinas #include <linux/io.h> 29c1cc1552SCatalin Marinas 30c1cc1552SCatalin Marinas #include <asm/cputype.h> 31c1cc1552SCatalin Marinas #include <asm/sections.h> 32c1cc1552SCatalin Marinas #include <asm/setup.h> 33c1cc1552SCatalin Marinas #include <asm/sizes.h> 34c1cc1552SCatalin Marinas #include <asm/tlb.h> 35c1cc1552SCatalin Marinas #include <asm/mmu_context.h> 36c1cc1552SCatalin Marinas 37c1cc1552SCatalin Marinas #include "mm.h" 38c1cc1552SCatalin Marinas 39c1cc1552SCatalin Marinas /* 40c1cc1552SCatalin Marinas * Empty_zero_page is a special page that is used for zero-initialized data 41c1cc1552SCatalin Marinas * and COW. 42c1cc1552SCatalin Marinas */ 43c1cc1552SCatalin Marinas struct page *empty_zero_page; 44c1cc1552SCatalin Marinas EXPORT_SYMBOL(empty_zero_page); 45c1cc1552SCatalin Marinas 46c1cc1552SCatalin Marinas pgprot_t pgprot_default; 47c1cc1552SCatalin Marinas EXPORT_SYMBOL(pgprot_default); 48c1cc1552SCatalin Marinas 49c1cc1552SCatalin Marinas static pmdval_t prot_sect_kernel; 50c1cc1552SCatalin Marinas 51c1cc1552SCatalin Marinas struct cachepolicy { 52c1cc1552SCatalin Marinas const char policy[16]; 53c1cc1552SCatalin Marinas u64 mair; 54c1cc1552SCatalin Marinas u64 tcr; 55c1cc1552SCatalin Marinas }; 56c1cc1552SCatalin Marinas 57c1cc1552SCatalin Marinas static struct cachepolicy cache_policies[] __initdata = { 58c1cc1552SCatalin Marinas { 59c1cc1552SCatalin Marinas .policy = "uncached", 60c1cc1552SCatalin Marinas .mair = 0x44, /* inner, outer non-cacheable */ 61c1cc1552SCatalin Marinas .tcr = TCR_IRGN_NC | TCR_ORGN_NC, 62c1cc1552SCatalin Marinas }, { 63c1cc1552SCatalin Marinas .policy = "writethrough", 64c1cc1552SCatalin Marinas .mair = 0xaa, /* inner, outer write-through, read-allocate */ 65c1cc1552SCatalin Marinas .tcr = TCR_IRGN_WT | TCR_ORGN_WT, 66c1cc1552SCatalin Marinas }, { 67c1cc1552SCatalin Marinas .policy = "writeback", 68c1cc1552SCatalin Marinas .mair = 0xee, /* inner, outer write-back, read-allocate */ 69c1cc1552SCatalin Marinas .tcr = TCR_IRGN_WBnWA | TCR_ORGN_WBnWA, 70c1cc1552SCatalin Marinas } 71c1cc1552SCatalin Marinas }; 72c1cc1552SCatalin Marinas 73c1cc1552SCatalin Marinas /* 74c1cc1552SCatalin Marinas * These are useful for identifying cache coherency problems by allowing the 75c1cc1552SCatalin Marinas * cache or the cache and writebuffer to be turned off. It changes the Normal 76c1cc1552SCatalin Marinas * memory caching attributes in the MAIR_EL1 register. 77c1cc1552SCatalin Marinas */ 78c1cc1552SCatalin Marinas static int __init early_cachepolicy(char *p) 79c1cc1552SCatalin Marinas { 80c1cc1552SCatalin Marinas int i; 81c1cc1552SCatalin Marinas u64 tmp; 82c1cc1552SCatalin Marinas 83c1cc1552SCatalin Marinas for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { 84c1cc1552SCatalin Marinas int len = strlen(cache_policies[i].policy); 85c1cc1552SCatalin Marinas 86c1cc1552SCatalin Marinas if (memcmp(p, cache_policies[i].policy, len) == 0) 87c1cc1552SCatalin Marinas break; 88c1cc1552SCatalin Marinas } 89c1cc1552SCatalin Marinas if (i == ARRAY_SIZE(cache_policies)) { 90c1cc1552SCatalin Marinas pr_err("ERROR: unknown or unsupported cache policy: %s\n", p); 91c1cc1552SCatalin Marinas return 0; 92c1cc1552SCatalin Marinas } 93c1cc1552SCatalin Marinas 94c1cc1552SCatalin Marinas flush_cache_all(); 95c1cc1552SCatalin Marinas 96c1cc1552SCatalin Marinas /* 97c1cc1552SCatalin Marinas * Modify MT_NORMAL attributes in MAIR_EL1. 98c1cc1552SCatalin Marinas */ 99c1cc1552SCatalin Marinas asm volatile( 100c1cc1552SCatalin Marinas " mrs %0, mair_el1\n" 101c1cc1552SCatalin Marinas " bfi %0, %1, #%2, #8\n" 102c1cc1552SCatalin Marinas " msr mair_el1, %0\n" 103c1cc1552SCatalin Marinas " isb\n" 104c1cc1552SCatalin Marinas : "=&r" (tmp) 105c1cc1552SCatalin Marinas : "r" (cache_policies[i].mair), "i" (MT_NORMAL * 8)); 106c1cc1552SCatalin Marinas 107c1cc1552SCatalin Marinas /* 108c1cc1552SCatalin Marinas * Modify TCR PTW cacheability attributes. 109c1cc1552SCatalin Marinas */ 110c1cc1552SCatalin Marinas asm volatile( 111c1cc1552SCatalin Marinas " mrs %0, tcr_el1\n" 112c1cc1552SCatalin Marinas " bic %0, %0, %2\n" 113c1cc1552SCatalin Marinas " orr %0, %0, %1\n" 114c1cc1552SCatalin Marinas " msr tcr_el1, %0\n" 115c1cc1552SCatalin Marinas " isb\n" 116c1cc1552SCatalin Marinas : "=&r" (tmp) 117c1cc1552SCatalin Marinas : "r" (cache_policies[i].tcr), "r" (TCR_IRGN_MASK | TCR_ORGN_MASK)); 118c1cc1552SCatalin Marinas 119c1cc1552SCatalin Marinas flush_cache_all(); 120c1cc1552SCatalin Marinas 121c1cc1552SCatalin Marinas return 0; 122c1cc1552SCatalin Marinas } 123c1cc1552SCatalin Marinas early_param("cachepolicy", early_cachepolicy); 124c1cc1552SCatalin Marinas 125c1cc1552SCatalin Marinas /* 126c1cc1552SCatalin Marinas * Adjust the PMD section entries according to the CPU in use. 127c1cc1552SCatalin Marinas */ 128c1cc1552SCatalin Marinas static void __init init_mem_pgprot(void) 129c1cc1552SCatalin Marinas { 130c1cc1552SCatalin Marinas pteval_t default_pgprot; 131c1cc1552SCatalin Marinas int i; 132c1cc1552SCatalin Marinas 133c1cc1552SCatalin Marinas default_pgprot = PTE_ATTRINDX(MT_NORMAL); 134c1cc1552SCatalin Marinas prot_sect_kernel = PMD_TYPE_SECT | PMD_SECT_AF | PMD_ATTRINDX(MT_NORMAL); 135c1cc1552SCatalin Marinas 136c1cc1552SCatalin Marinas #ifdef CONFIG_SMP 137c1cc1552SCatalin Marinas /* 138c1cc1552SCatalin Marinas * Mark memory with the "shared" attribute for SMP systems 139c1cc1552SCatalin Marinas */ 140c1cc1552SCatalin Marinas default_pgprot |= PTE_SHARED; 141c1cc1552SCatalin Marinas prot_sect_kernel |= PMD_SECT_S; 142c1cc1552SCatalin Marinas #endif 143c1cc1552SCatalin Marinas 144c1cc1552SCatalin Marinas for (i = 0; i < 16; i++) { 145c1cc1552SCatalin Marinas unsigned long v = pgprot_val(protection_map[i]); 146c1cc1552SCatalin Marinas protection_map[i] = __pgprot(v | default_pgprot); 147c1cc1552SCatalin Marinas } 148c1cc1552SCatalin Marinas 149c1cc1552SCatalin Marinas pgprot_default = __pgprot(PTE_TYPE_PAGE | PTE_AF | default_pgprot); 150c1cc1552SCatalin Marinas } 151c1cc1552SCatalin Marinas 152c1cc1552SCatalin Marinas pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 153c1cc1552SCatalin Marinas unsigned long size, pgprot_t vma_prot) 154c1cc1552SCatalin Marinas { 155c1cc1552SCatalin Marinas if (!pfn_valid(pfn)) 156c1cc1552SCatalin Marinas return pgprot_noncached(vma_prot); 157c1cc1552SCatalin Marinas else if (file->f_flags & O_SYNC) 158c1cc1552SCatalin Marinas return pgprot_writecombine(vma_prot); 159c1cc1552SCatalin Marinas return vma_prot; 160c1cc1552SCatalin Marinas } 161c1cc1552SCatalin Marinas EXPORT_SYMBOL(phys_mem_access_prot); 162c1cc1552SCatalin Marinas 163c1cc1552SCatalin Marinas static void __init *early_alloc(unsigned long sz) 164c1cc1552SCatalin Marinas { 165c1cc1552SCatalin Marinas void *ptr = __va(memblock_alloc(sz, sz)); 166c1cc1552SCatalin Marinas memset(ptr, 0, sz); 167c1cc1552SCatalin Marinas return ptr; 168c1cc1552SCatalin Marinas } 169c1cc1552SCatalin Marinas 170c1cc1552SCatalin Marinas static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, 171c1cc1552SCatalin Marinas unsigned long end, unsigned long pfn) 172c1cc1552SCatalin Marinas { 173c1cc1552SCatalin Marinas pte_t *pte; 174c1cc1552SCatalin Marinas 175c1cc1552SCatalin Marinas if (pmd_none(*pmd)) { 176c1cc1552SCatalin Marinas pte = early_alloc(PTRS_PER_PTE * sizeof(pte_t)); 177c1cc1552SCatalin Marinas __pmd_populate(pmd, __pa(pte), PMD_TYPE_TABLE); 178c1cc1552SCatalin Marinas } 179c1cc1552SCatalin Marinas BUG_ON(pmd_bad(*pmd)); 180c1cc1552SCatalin Marinas 181c1cc1552SCatalin Marinas pte = pte_offset_kernel(pmd, addr); 182c1cc1552SCatalin Marinas do { 183c1cc1552SCatalin Marinas set_pte(pte, pfn_pte(pfn, PAGE_KERNEL_EXEC)); 184c1cc1552SCatalin Marinas pfn++; 185c1cc1552SCatalin Marinas } while (pte++, addr += PAGE_SIZE, addr != end); 186c1cc1552SCatalin Marinas } 187c1cc1552SCatalin Marinas 188c1cc1552SCatalin Marinas static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, 189c1cc1552SCatalin Marinas unsigned long end, phys_addr_t phys) 190c1cc1552SCatalin Marinas { 191c1cc1552SCatalin Marinas pmd_t *pmd; 192c1cc1552SCatalin Marinas unsigned long next; 193c1cc1552SCatalin Marinas 194c1cc1552SCatalin Marinas /* 195c1cc1552SCatalin Marinas * Check for initial section mappings in the pgd/pud and remove them. 196c1cc1552SCatalin Marinas */ 197c1cc1552SCatalin Marinas if (pud_none(*pud) || pud_bad(*pud)) { 198c1cc1552SCatalin Marinas pmd = early_alloc(PTRS_PER_PMD * sizeof(pmd_t)); 199c1cc1552SCatalin Marinas pud_populate(&init_mm, pud, pmd); 200c1cc1552SCatalin Marinas } 201c1cc1552SCatalin Marinas 202c1cc1552SCatalin Marinas pmd = pmd_offset(pud, addr); 203c1cc1552SCatalin Marinas do { 204c1cc1552SCatalin Marinas next = pmd_addr_end(addr, end); 205c1cc1552SCatalin Marinas /* try section mapping first */ 206c1cc1552SCatalin Marinas if (((addr | next | phys) & ~SECTION_MASK) == 0) 207c1cc1552SCatalin Marinas set_pmd(pmd, __pmd(phys | prot_sect_kernel)); 208c1cc1552SCatalin Marinas else 209c1cc1552SCatalin Marinas alloc_init_pte(pmd, addr, next, __phys_to_pfn(phys)); 210c1cc1552SCatalin Marinas phys += next - addr; 211c1cc1552SCatalin Marinas } while (pmd++, addr = next, addr != end); 212c1cc1552SCatalin Marinas } 213c1cc1552SCatalin Marinas 214c1cc1552SCatalin Marinas static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, 215c1cc1552SCatalin Marinas unsigned long end, unsigned long phys) 216c1cc1552SCatalin Marinas { 217c1cc1552SCatalin Marinas pud_t *pud = pud_offset(pgd, addr); 218c1cc1552SCatalin Marinas unsigned long next; 219c1cc1552SCatalin Marinas 220c1cc1552SCatalin Marinas do { 221c1cc1552SCatalin Marinas next = pud_addr_end(addr, end); 222c1cc1552SCatalin Marinas alloc_init_pmd(pud, addr, next, phys); 223c1cc1552SCatalin Marinas phys += next - addr; 224c1cc1552SCatalin Marinas } while (pud++, addr = next, addr != end); 225c1cc1552SCatalin Marinas } 226c1cc1552SCatalin Marinas 227c1cc1552SCatalin Marinas /* 228c1cc1552SCatalin Marinas * Create the page directory entries and any necessary page tables for the 229c1cc1552SCatalin Marinas * mapping specified by 'md'. 230c1cc1552SCatalin Marinas */ 231c1cc1552SCatalin Marinas static void __init create_mapping(phys_addr_t phys, unsigned long virt, 232c1cc1552SCatalin Marinas phys_addr_t size) 233c1cc1552SCatalin Marinas { 234c1cc1552SCatalin Marinas unsigned long addr, length, end, next; 235c1cc1552SCatalin Marinas pgd_t *pgd; 236c1cc1552SCatalin Marinas 237c1cc1552SCatalin Marinas if (virt < VMALLOC_START) { 238c1cc1552SCatalin Marinas pr_warning("BUG: not creating mapping for 0x%016llx at 0x%016lx - outside kernel range\n", 239c1cc1552SCatalin Marinas phys, virt); 240c1cc1552SCatalin Marinas return; 241c1cc1552SCatalin Marinas } 242c1cc1552SCatalin Marinas 243c1cc1552SCatalin Marinas addr = virt & PAGE_MASK; 244c1cc1552SCatalin Marinas length = PAGE_ALIGN(size + (virt & ~PAGE_MASK)); 245c1cc1552SCatalin Marinas 246c1cc1552SCatalin Marinas pgd = pgd_offset_k(addr); 247c1cc1552SCatalin Marinas end = addr + length; 248c1cc1552SCatalin Marinas do { 249c1cc1552SCatalin Marinas next = pgd_addr_end(addr, end); 250c1cc1552SCatalin Marinas alloc_init_pud(pgd, addr, next, phys); 251c1cc1552SCatalin Marinas phys += next - addr; 252c1cc1552SCatalin Marinas } while (pgd++, addr = next, addr != end); 253c1cc1552SCatalin Marinas } 254c1cc1552SCatalin Marinas 2552475ff9dSCatalin Marinas #ifdef CONFIG_EARLY_PRINTK 2562475ff9dSCatalin Marinas /* 2572475ff9dSCatalin Marinas * Create an early I/O mapping using the pgd/pmd entries already populated 2582475ff9dSCatalin Marinas * in head.S as this function is called too early to allocated any memory. The 2592475ff9dSCatalin Marinas * mapping size is 2MB with 4KB pages or 64KB or 64KB pages. 2602475ff9dSCatalin Marinas */ 2612475ff9dSCatalin Marinas void __iomem * __init early_io_map(phys_addr_t phys, unsigned long virt) 2622475ff9dSCatalin Marinas { 2632475ff9dSCatalin Marinas unsigned long size, mask; 2642475ff9dSCatalin Marinas bool page64k = IS_ENABLED(ARM64_64K_PAGES); 2652475ff9dSCatalin Marinas pgd_t *pgd; 2662475ff9dSCatalin Marinas pud_t *pud; 2672475ff9dSCatalin Marinas pmd_t *pmd; 2682475ff9dSCatalin Marinas pte_t *pte; 2692475ff9dSCatalin Marinas 2702475ff9dSCatalin Marinas /* 2712475ff9dSCatalin Marinas * No early pte entries with !ARM64_64K_PAGES configuration, so using 2722475ff9dSCatalin Marinas * sections (pmd). 2732475ff9dSCatalin Marinas */ 2742475ff9dSCatalin Marinas size = page64k ? PAGE_SIZE : SECTION_SIZE; 2752475ff9dSCatalin Marinas mask = ~(size - 1); 2762475ff9dSCatalin Marinas 2772475ff9dSCatalin Marinas pgd = pgd_offset_k(virt); 2782475ff9dSCatalin Marinas pud = pud_offset(pgd, virt); 2792475ff9dSCatalin Marinas if (pud_none(*pud)) 2802475ff9dSCatalin Marinas return NULL; 2812475ff9dSCatalin Marinas pmd = pmd_offset(pud, virt); 2822475ff9dSCatalin Marinas 2832475ff9dSCatalin Marinas if (page64k) { 2842475ff9dSCatalin Marinas if (pmd_none(*pmd)) 2852475ff9dSCatalin Marinas return NULL; 2862475ff9dSCatalin Marinas pte = pte_offset_kernel(pmd, virt); 2872475ff9dSCatalin Marinas set_pte(pte, __pte((phys & mask) | PROT_DEVICE_nGnRE)); 2882475ff9dSCatalin Marinas } else { 2892475ff9dSCatalin Marinas set_pmd(pmd, __pmd((phys & mask) | PROT_SECT_DEVICE_nGnRE)); 2902475ff9dSCatalin Marinas } 2912475ff9dSCatalin Marinas 2922475ff9dSCatalin Marinas return (void __iomem *)((virt & mask) + (phys & ~mask)); 2932475ff9dSCatalin Marinas } 2942475ff9dSCatalin Marinas #endif 2952475ff9dSCatalin Marinas 296c1cc1552SCatalin Marinas static void __init map_mem(void) 297c1cc1552SCatalin Marinas { 298c1cc1552SCatalin Marinas struct memblock_region *reg; 299c1cc1552SCatalin Marinas 300c1cc1552SCatalin Marinas /* map all the memory banks */ 301c1cc1552SCatalin Marinas for_each_memblock(memory, reg) { 302c1cc1552SCatalin Marinas phys_addr_t start = reg->base; 303c1cc1552SCatalin Marinas phys_addr_t end = start + reg->size; 304c1cc1552SCatalin Marinas 305c1cc1552SCatalin Marinas if (start >= end) 306c1cc1552SCatalin Marinas break; 307c1cc1552SCatalin Marinas 308c1cc1552SCatalin Marinas create_mapping(start, __phys_to_virt(start), end - start); 309c1cc1552SCatalin Marinas } 310c1cc1552SCatalin Marinas } 311c1cc1552SCatalin Marinas 312c1cc1552SCatalin Marinas /* 313c1cc1552SCatalin Marinas * paging_init() sets up the page tables, initialises the zone memory 314c1cc1552SCatalin Marinas * maps and sets up the zero page. 315c1cc1552SCatalin Marinas */ 316c1cc1552SCatalin Marinas void __init paging_init(void) 317c1cc1552SCatalin Marinas { 318c1cc1552SCatalin Marinas void *zero_page; 319c1cc1552SCatalin Marinas 320c1cc1552SCatalin Marinas /* 321c1cc1552SCatalin Marinas * Maximum PGDIR_SIZE addressable via the initial direct kernel 322c1cc1552SCatalin Marinas * mapping in swapper_pg_dir. 323c1cc1552SCatalin Marinas */ 324c1cc1552SCatalin Marinas memblock_set_current_limit((PHYS_OFFSET & PGDIR_MASK) + PGDIR_SIZE); 325c1cc1552SCatalin Marinas 326c1cc1552SCatalin Marinas init_mem_pgprot(); 327c1cc1552SCatalin Marinas map_mem(); 328c1cc1552SCatalin Marinas 329c1cc1552SCatalin Marinas /* 330c1cc1552SCatalin Marinas * Finally flush the caches and tlb to ensure that we're in a 331c1cc1552SCatalin Marinas * consistent state. 332c1cc1552SCatalin Marinas */ 333c1cc1552SCatalin Marinas flush_cache_all(); 334c1cc1552SCatalin Marinas flush_tlb_all(); 335c1cc1552SCatalin Marinas 336c1cc1552SCatalin Marinas /* allocate the zero page. */ 337c1cc1552SCatalin Marinas zero_page = early_alloc(PAGE_SIZE); 338c1cc1552SCatalin Marinas 339c1cc1552SCatalin Marinas bootmem_init(); 340c1cc1552SCatalin Marinas 341c1cc1552SCatalin Marinas empty_zero_page = virt_to_page(zero_page); 342c1cc1552SCatalin Marinas __flush_dcache_page(empty_zero_page); 343c1cc1552SCatalin Marinas 344c1cc1552SCatalin Marinas /* 345c1cc1552SCatalin Marinas * TTBR0 is only used for the identity mapping at this stage. Make it 346c1cc1552SCatalin Marinas * point to zero page to avoid speculatively fetching new entries. 347c1cc1552SCatalin Marinas */ 348c1cc1552SCatalin Marinas cpu_set_reserved_ttbr0(); 349c1cc1552SCatalin Marinas flush_tlb_all(); 350c1cc1552SCatalin Marinas } 351c1cc1552SCatalin Marinas 352c1cc1552SCatalin Marinas /* 353c1cc1552SCatalin Marinas * Enable the identity mapping to allow the MMU disabling. 354c1cc1552SCatalin Marinas */ 355c1cc1552SCatalin Marinas void setup_mm_for_reboot(void) 356c1cc1552SCatalin Marinas { 357c1cc1552SCatalin Marinas cpu_switch_mm(idmap_pg_dir, &init_mm); 358c1cc1552SCatalin Marinas flush_tlb_all(); 359c1cc1552SCatalin Marinas } 360c1cc1552SCatalin Marinas 361c1cc1552SCatalin Marinas /* 362c1cc1552SCatalin Marinas * Check whether a kernel address is valid (derived from arch/x86/). 363c1cc1552SCatalin Marinas */ 364c1cc1552SCatalin Marinas int kern_addr_valid(unsigned long addr) 365c1cc1552SCatalin Marinas { 366c1cc1552SCatalin Marinas pgd_t *pgd; 367c1cc1552SCatalin Marinas pud_t *pud; 368c1cc1552SCatalin Marinas pmd_t *pmd; 369c1cc1552SCatalin Marinas pte_t *pte; 370c1cc1552SCatalin Marinas 371c1cc1552SCatalin Marinas if ((((long)addr) >> VA_BITS) != -1UL) 372c1cc1552SCatalin Marinas return 0; 373c1cc1552SCatalin Marinas 374c1cc1552SCatalin Marinas pgd = pgd_offset_k(addr); 375c1cc1552SCatalin Marinas if (pgd_none(*pgd)) 376c1cc1552SCatalin Marinas return 0; 377c1cc1552SCatalin Marinas 378c1cc1552SCatalin Marinas pud = pud_offset(pgd, addr); 379c1cc1552SCatalin Marinas if (pud_none(*pud)) 380c1cc1552SCatalin Marinas return 0; 381c1cc1552SCatalin Marinas 382c1cc1552SCatalin Marinas pmd = pmd_offset(pud, addr); 383c1cc1552SCatalin Marinas if (pmd_none(*pmd)) 384c1cc1552SCatalin Marinas return 0; 385c1cc1552SCatalin Marinas 386c1cc1552SCatalin Marinas pte = pte_offset_kernel(pmd, addr); 387c1cc1552SCatalin Marinas if (pte_none(*pte)) 388c1cc1552SCatalin Marinas return 0; 389c1cc1552SCatalin Marinas 390c1cc1552SCatalin Marinas return pfn_valid(pte_pfn(*pte)); 391c1cc1552SCatalin Marinas } 392c1cc1552SCatalin Marinas #ifdef CONFIG_SPARSEMEM_VMEMMAP 393c1cc1552SCatalin Marinas #ifdef CONFIG_ARM64_64K_PAGES 394c1cc1552SCatalin Marinas int __meminit vmemmap_populate(struct page *start_page, 395c1cc1552SCatalin Marinas unsigned long size, int node) 396c1cc1552SCatalin Marinas { 397c1cc1552SCatalin Marinas return vmemmap_populate_basepages(start_page, size, node); 398c1cc1552SCatalin Marinas } 399c1cc1552SCatalin Marinas #else /* !CONFIG_ARM64_64K_PAGES */ 400c1cc1552SCatalin Marinas int __meminit vmemmap_populate(struct page *start_page, 401c1cc1552SCatalin Marinas unsigned long size, int node) 402c1cc1552SCatalin Marinas { 403c1cc1552SCatalin Marinas unsigned long addr = (unsigned long)start_page; 404c1cc1552SCatalin Marinas unsigned long end = (unsigned long)(start_page + size); 405c1cc1552SCatalin Marinas unsigned long next; 406c1cc1552SCatalin Marinas pgd_t *pgd; 407c1cc1552SCatalin Marinas pud_t *pud; 408c1cc1552SCatalin Marinas pmd_t *pmd; 409c1cc1552SCatalin Marinas 410c1cc1552SCatalin Marinas do { 411c1cc1552SCatalin Marinas next = pmd_addr_end(addr, end); 412c1cc1552SCatalin Marinas 413c1cc1552SCatalin Marinas pgd = vmemmap_pgd_populate(addr, node); 414c1cc1552SCatalin Marinas if (!pgd) 415c1cc1552SCatalin Marinas return -ENOMEM; 416c1cc1552SCatalin Marinas 417c1cc1552SCatalin Marinas pud = vmemmap_pud_populate(pgd, addr, node); 418c1cc1552SCatalin Marinas if (!pud) 419c1cc1552SCatalin Marinas return -ENOMEM; 420c1cc1552SCatalin Marinas 421c1cc1552SCatalin Marinas pmd = pmd_offset(pud, addr); 422c1cc1552SCatalin Marinas if (pmd_none(*pmd)) { 423c1cc1552SCatalin Marinas void *p = NULL; 424c1cc1552SCatalin Marinas 425c1cc1552SCatalin Marinas p = vmemmap_alloc_block_buf(PMD_SIZE, node); 426c1cc1552SCatalin Marinas if (!p) 427c1cc1552SCatalin Marinas return -ENOMEM; 428c1cc1552SCatalin Marinas 429c1cc1552SCatalin Marinas set_pmd(pmd, __pmd(__pa(p) | prot_sect_kernel)); 430c1cc1552SCatalin Marinas } else 431c1cc1552SCatalin Marinas vmemmap_verify((pte_t *)pmd, node, addr, next); 432c1cc1552SCatalin Marinas } while (addr = next, addr != end); 433c1cc1552SCatalin Marinas 434c1cc1552SCatalin Marinas return 0; 435c1cc1552SCatalin Marinas } 436c1cc1552SCatalin Marinas #endif /* CONFIG_ARM64_64K_PAGES */ 437*0197518cSTang Chen void vmemmap_free(struct page *memmap, unsigned long nr_pages) 438*0197518cSTang Chen { 439*0197518cSTang Chen } 440c1cc1552SCatalin Marinas #endif /* CONFIG_SPARSEMEM_VMEMMAP */ 441