1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bsearch.h> 13 #include <linux/kvm_host.h> 14 #include <linux/mm.h> 15 #include <linux/printk.h> 16 #include <linux/uaccess.h> 17 18 #include <asm/cacheflush.h> 19 #include <asm/cputype.h> 20 #include <asm/debug-monitors.h> 21 #include <asm/esr.h> 22 #include <asm/kvm_arm.h> 23 #include <asm/kvm_emulate.h> 24 #include <asm/kvm_hyp.h> 25 #include <asm/kvm_mmu.h> 26 #include <asm/perf_event.h> 27 #include <asm/sysreg.h> 28 29 #include <trace/events/kvm.h> 30 31 #include "sys_regs.h" 32 33 #include "trace.h" 34 35 /* 36 * All of this file is extremely similar to the ARM coproc.c, but the 37 * types are different. My gut feeling is that it should be pretty 38 * easy to merge, but that would be an ABI breakage -- again. VFP 39 * would also need to be abstracted. 40 * 41 * For AArch32, we only take care of what is being trapped. Anything 42 * that has to do with init and userspace access has to go via the 43 * 64bit interface. 44 */ 45 46 static bool read_from_write_only(struct kvm_vcpu *vcpu, 47 struct sys_reg_params *params, 48 const struct sys_reg_desc *r) 49 { 50 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n"); 51 print_sys_reg_instr(params); 52 kvm_inject_undefined(vcpu); 53 return false; 54 } 55 56 static bool write_to_read_only(struct kvm_vcpu *vcpu, 57 struct sys_reg_params *params, 58 const struct sys_reg_desc *r) 59 { 60 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n"); 61 print_sys_reg_instr(params); 62 kvm_inject_undefined(vcpu); 63 return false; 64 } 65 66 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 67 { 68 u64 val = 0x8badf00d8badf00d; 69 70 if (vcpu->arch.sysregs_loaded_on_cpu && 71 __vcpu_read_sys_reg_from_cpu(reg, &val)) 72 return val; 73 74 return __vcpu_sys_reg(vcpu, reg); 75 } 76 77 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 78 { 79 if (vcpu->arch.sysregs_loaded_on_cpu && 80 __vcpu_write_sys_reg_to_cpu(val, reg)) 81 return; 82 83 __vcpu_sys_reg(vcpu, reg) = val; 84 } 85 86 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ 87 static u32 cache_levels; 88 89 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 90 #define CSSELR_MAX 14 91 92 /* Which cache CCSIDR represents depends on CSSELR value. */ 93 static u32 get_ccsidr(u32 csselr) 94 { 95 u32 ccsidr; 96 97 /* Make sure noone else changes CSSELR during this! */ 98 local_irq_disable(); 99 write_sysreg(csselr, csselr_el1); 100 isb(); 101 ccsidr = read_sysreg(ccsidr_el1); 102 local_irq_enable(); 103 104 return ccsidr; 105 } 106 107 /* 108 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 109 */ 110 static bool access_dcsw(struct kvm_vcpu *vcpu, 111 struct sys_reg_params *p, 112 const struct sys_reg_desc *r) 113 { 114 if (!p->is_write) 115 return read_from_write_only(vcpu, p, r); 116 117 /* 118 * Only track S/W ops if we don't have FWB. It still indicates 119 * that the guest is a bit broken (S/W operations should only 120 * be done by firmware, knowing that there is only a single 121 * CPU left in the system, and certainly not from non-secure 122 * software). 123 */ 124 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) 125 kvm_set_way_flush(vcpu); 126 127 return true; 128 } 129 130 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift) 131 { 132 switch (r->aarch32_map) { 133 case AA32_LO: 134 *mask = GENMASK_ULL(31, 0); 135 *shift = 0; 136 break; 137 case AA32_HI: 138 *mask = GENMASK_ULL(63, 32); 139 *shift = 32; 140 break; 141 default: 142 *mask = GENMASK_ULL(63, 0); 143 *shift = 0; 144 break; 145 } 146 } 147 148 /* 149 * Generic accessor for VM registers. Only called as long as HCR_TVM 150 * is set. If the guest enables the MMU, we stop trapping the VM 151 * sys_regs and leave it in complete control of the caches. 152 */ 153 static bool access_vm_reg(struct kvm_vcpu *vcpu, 154 struct sys_reg_params *p, 155 const struct sys_reg_desc *r) 156 { 157 bool was_enabled = vcpu_has_cache_enabled(vcpu); 158 u64 val, mask, shift; 159 160 BUG_ON(!p->is_write); 161 162 get_access_mask(r, &mask, &shift); 163 164 if (~mask) { 165 val = vcpu_read_sys_reg(vcpu, r->reg); 166 val &= ~mask; 167 } else { 168 val = 0; 169 } 170 171 val |= (p->regval & (mask >> shift)) << shift; 172 vcpu_write_sys_reg(vcpu, val, r->reg); 173 174 kvm_toggle_cache(vcpu, was_enabled); 175 return true; 176 } 177 178 static bool access_actlr(struct kvm_vcpu *vcpu, 179 struct sys_reg_params *p, 180 const struct sys_reg_desc *r) 181 { 182 u64 mask, shift; 183 184 if (p->is_write) 185 return ignore_write(vcpu, p); 186 187 get_access_mask(r, &mask, &shift); 188 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; 189 190 return true; 191 } 192 193 /* 194 * Trap handler for the GICv3 SGI generation system register. 195 * Forward the request to the VGIC emulation. 196 * The cp15_64 code makes sure this automatically works 197 * for both AArch64 and AArch32 accesses. 198 */ 199 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 200 struct sys_reg_params *p, 201 const struct sys_reg_desc *r) 202 { 203 bool g1; 204 205 if (!p->is_write) 206 return read_from_write_only(vcpu, p, r); 207 208 /* 209 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 210 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 211 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 212 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 213 * group. 214 */ 215 if (p->Op0 == 0) { /* AArch32 */ 216 switch (p->Op1) { 217 default: /* Keep GCC quiet */ 218 case 0: /* ICC_SGI1R */ 219 g1 = true; 220 break; 221 case 1: /* ICC_ASGI1R */ 222 case 2: /* ICC_SGI0R */ 223 g1 = false; 224 break; 225 } 226 } else { /* AArch64 */ 227 switch (p->Op2) { 228 default: /* Keep GCC quiet */ 229 case 5: /* ICC_SGI1R_EL1 */ 230 g1 = true; 231 break; 232 case 6: /* ICC_ASGI1R_EL1 */ 233 case 7: /* ICC_SGI0R_EL1 */ 234 g1 = false; 235 break; 236 } 237 } 238 239 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 240 241 return true; 242 } 243 244 static bool access_gic_sre(struct kvm_vcpu *vcpu, 245 struct sys_reg_params *p, 246 const struct sys_reg_desc *r) 247 { 248 if (p->is_write) 249 return ignore_write(vcpu, p); 250 251 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 252 return true; 253 } 254 255 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 256 struct sys_reg_params *p, 257 const struct sys_reg_desc *r) 258 { 259 if (p->is_write) 260 return ignore_write(vcpu, p); 261 else 262 return read_zero(vcpu, p); 263 } 264 265 /* 266 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 267 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 268 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 269 * treat it separately. 270 */ 271 static bool trap_loregion(struct kvm_vcpu *vcpu, 272 struct sys_reg_params *p, 273 const struct sys_reg_desc *r) 274 { 275 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 276 u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1, 277 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); 278 279 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) { 280 kvm_inject_undefined(vcpu); 281 return false; 282 } 283 284 if (p->is_write && sr == SYS_LORID_EL1) 285 return write_to_read_only(vcpu, p, r); 286 287 return trap_raz_wi(vcpu, p, r); 288 } 289 290 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 291 struct sys_reg_params *p, 292 const struct sys_reg_desc *r) 293 { 294 if (p->is_write) { 295 return ignore_write(vcpu, p); 296 } else { 297 p->regval = (1 << 3); 298 return true; 299 } 300 } 301 302 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 303 struct sys_reg_params *p, 304 const struct sys_reg_desc *r) 305 { 306 if (p->is_write) { 307 return ignore_write(vcpu, p); 308 } else { 309 p->regval = read_sysreg(dbgauthstatus_el1); 310 return true; 311 } 312 } 313 314 /* 315 * We want to avoid world-switching all the DBG registers all the 316 * time: 317 * 318 * - If we've touched any debug register, it is likely that we're 319 * going to touch more of them. It then makes sense to disable the 320 * traps and start doing the save/restore dance 321 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 322 * then mandatory to save/restore the registers, as the guest 323 * depends on them. 324 * 325 * For this, we use a DIRTY bit, indicating the guest has modified the 326 * debug registers, used as follow: 327 * 328 * On guest entry: 329 * - If the dirty bit is set (because we're coming back from trapping), 330 * disable the traps, save host registers, restore guest registers. 331 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 332 * set the dirty bit, disable the traps, save host registers, 333 * restore guest registers. 334 * - Otherwise, enable the traps 335 * 336 * On guest exit: 337 * - If the dirty bit is set, save guest registers, restore host 338 * registers and clear the dirty bit. This ensure that the host can 339 * now use the debug registers. 340 */ 341 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 342 struct sys_reg_params *p, 343 const struct sys_reg_desc *r) 344 { 345 if (p->is_write) { 346 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 347 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 348 } else { 349 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 350 } 351 352 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 353 354 return true; 355 } 356 357 /* 358 * reg_to_dbg/dbg_to_reg 359 * 360 * A 32 bit write to a debug register leave top bits alone 361 * A 32 bit read from a debug register only returns the bottom bits 362 * 363 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the 364 * hyp.S code switches between host and guest values in future. 365 */ 366 static void reg_to_dbg(struct kvm_vcpu *vcpu, 367 struct sys_reg_params *p, 368 const struct sys_reg_desc *rd, 369 u64 *dbg_reg) 370 { 371 u64 mask, shift, val; 372 373 get_access_mask(rd, &mask, &shift); 374 375 val = *dbg_reg; 376 val &= ~mask; 377 val |= (p->regval & (mask >> shift)) << shift; 378 *dbg_reg = val; 379 380 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 381 } 382 383 static void dbg_to_reg(struct kvm_vcpu *vcpu, 384 struct sys_reg_params *p, 385 const struct sys_reg_desc *rd, 386 u64 *dbg_reg) 387 { 388 u64 mask, shift; 389 390 get_access_mask(rd, &mask, &shift); 391 p->regval = (*dbg_reg & mask) >> shift; 392 } 393 394 static bool trap_bvr(struct kvm_vcpu *vcpu, 395 struct sys_reg_params *p, 396 const struct sys_reg_desc *rd) 397 { 398 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 399 400 if (p->is_write) 401 reg_to_dbg(vcpu, p, rd, dbg_reg); 402 else 403 dbg_to_reg(vcpu, p, rd, dbg_reg); 404 405 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 406 407 return true; 408 } 409 410 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 411 const struct kvm_one_reg *reg, void __user *uaddr) 412 { 413 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 414 415 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 416 return -EFAULT; 417 return 0; 418 } 419 420 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 421 const struct kvm_one_reg *reg, void __user *uaddr) 422 { 423 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 424 425 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 426 return -EFAULT; 427 return 0; 428 } 429 430 static void reset_bvr(struct kvm_vcpu *vcpu, 431 const struct sys_reg_desc *rd) 432 { 433 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val; 434 } 435 436 static bool trap_bcr(struct kvm_vcpu *vcpu, 437 struct sys_reg_params *p, 438 const struct sys_reg_desc *rd) 439 { 440 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 441 442 if (p->is_write) 443 reg_to_dbg(vcpu, p, rd, dbg_reg); 444 else 445 dbg_to_reg(vcpu, p, rd, dbg_reg); 446 447 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 448 449 return true; 450 } 451 452 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 453 const struct kvm_one_reg *reg, void __user *uaddr) 454 { 455 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 456 457 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 458 return -EFAULT; 459 460 return 0; 461 } 462 463 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 464 const struct kvm_one_reg *reg, void __user *uaddr) 465 { 466 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 467 468 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 469 return -EFAULT; 470 return 0; 471 } 472 473 static void reset_bcr(struct kvm_vcpu *vcpu, 474 const struct sys_reg_desc *rd) 475 { 476 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val; 477 } 478 479 static bool trap_wvr(struct kvm_vcpu *vcpu, 480 struct sys_reg_params *p, 481 const struct sys_reg_desc *rd) 482 { 483 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 484 485 if (p->is_write) 486 reg_to_dbg(vcpu, p, rd, dbg_reg); 487 else 488 dbg_to_reg(vcpu, p, rd, dbg_reg); 489 490 trace_trap_reg(__func__, rd->reg, p->is_write, 491 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]); 492 493 return true; 494 } 495 496 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 497 const struct kvm_one_reg *reg, void __user *uaddr) 498 { 499 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 500 501 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 502 return -EFAULT; 503 return 0; 504 } 505 506 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 507 const struct kvm_one_reg *reg, void __user *uaddr) 508 { 509 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 510 511 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 512 return -EFAULT; 513 return 0; 514 } 515 516 static void reset_wvr(struct kvm_vcpu *vcpu, 517 const struct sys_reg_desc *rd) 518 { 519 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val; 520 } 521 522 static bool trap_wcr(struct kvm_vcpu *vcpu, 523 struct sys_reg_params *p, 524 const struct sys_reg_desc *rd) 525 { 526 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 527 528 if (p->is_write) 529 reg_to_dbg(vcpu, p, rd, dbg_reg); 530 else 531 dbg_to_reg(vcpu, p, rd, dbg_reg); 532 533 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 534 535 return true; 536 } 537 538 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 539 const struct kvm_one_reg *reg, void __user *uaddr) 540 { 541 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 542 543 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 544 return -EFAULT; 545 return 0; 546 } 547 548 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 549 const struct kvm_one_reg *reg, void __user *uaddr) 550 { 551 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 552 553 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 554 return -EFAULT; 555 return 0; 556 } 557 558 static void reset_wcr(struct kvm_vcpu *vcpu, 559 const struct sys_reg_desc *rd) 560 { 561 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val; 562 } 563 564 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 565 { 566 u64 amair = read_sysreg(amair_el1); 567 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 568 } 569 570 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 571 { 572 u64 actlr = read_sysreg(actlr_el1); 573 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 574 } 575 576 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 577 { 578 u64 mpidr; 579 580 /* 581 * Map the vcpu_id into the first three affinity level fields of 582 * the MPIDR. We limit the number of VCPUs in level 0 due to a 583 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 584 * of the GICv3 to be able to address each CPU directly when 585 * sending IPIs. 586 */ 587 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 588 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 589 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 590 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1); 591 } 592 593 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 594 { 595 u64 pmcr, val; 596 597 pmcr = read_sysreg(pmcr_el0); 598 /* 599 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN 600 * except PMCR.E resetting to zero. 601 */ 602 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK) 603 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E); 604 if (!system_supports_32bit_el0()) 605 val |= ARMV8_PMU_PMCR_LC; 606 __vcpu_sys_reg(vcpu, r->reg) = val; 607 } 608 609 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 610 { 611 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 612 bool enabled = kvm_vcpu_has_pmu(vcpu); 613 614 enabled &= (reg & flags) || vcpu_mode_priv(vcpu); 615 if (!enabled) 616 kvm_inject_undefined(vcpu); 617 618 return !enabled; 619 } 620 621 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 622 { 623 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 624 } 625 626 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 627 { 628 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 629 } 630 631 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 632 { 633 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 634 } 635 636 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 637 { 638 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 639 } 640 641 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 642 const struct sys_reg_desc *r) 643 { 644 u64 val; 645 646 if (pmu_access_el0_disabled(vcpu)) 647 return false; 648 649 if (p->is_write) { 650 /* Only update writeable bits of PMCR */ 651 val = __vcpu_sys_reg(vcpu, PMCR_EL0); 652 val &= ~ARMV8_PMU_PMCR_MASK; 653 val |= p->regval & ARMV8_PMU_PMCR_MASK; 654 if (!system_supports_32bit_el0()) 655 val |= ARMV8_PMU_PMCR_LC; 656 __vcpu_sys_reg(vcpu, PMCR_EL0) = val; 657 kvm_pmu_handle_pmcr(vcpu, val); 658 kvm_vcpu_pmu_restore_guest(vcpu); 659 } else { 660 /* PMCR.P & PMCR.C are RAZ */ 661 val = __vcpu_sys_reg(vcpu, PMCR_EL0) 662 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 663 p->regval = val; 664 } 665 666 return true; 667 } 668 669 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 670 const struct sys_reg_desc *r) 671 { 672 if (pmu_access_event_counter_el0_disabled(vcpu)) 673 return false; 674 675 if (p->is_write) 676 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 677 else 678 /* return PMSELR.SEL field */ 679 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 680 & ARMV8_PMU_COUNTER_MASK; 681 682 return true; 683 } 684 685 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 686 const struct sys_reg_desc *r) 687 { 688 u64 pmceid; 689 690 BUG_ON(p->is_write); 691 692 if (pmu_access_el0_disabled(vcpu)) 693 return false; 694 695 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1)); 696 697 p->regval = pmceid; 698 699 return true; 700 } 701 702 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 703 { 704 u64 pmcr, val; 705 706 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0); 707 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; 708 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 709 kvm_inject_undefined(vcpu); 710 return false; 711 } 712 713 return true; 714 } 715 716 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 717 struct sys_reg_params *p, 718 const struct sys_reg_desc *r) 719 { 720 u64 idx = ~0UL; 721 722 if (r->CRn == 9 && r->CRm == 13) { 723 if (r->Op2 == 2) { 724 /* PMXEVCNTR_EL0 */ 725 if (pmu_access_event_counter_el0_disabled(vcpu)) 726 return false; 727 728 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) 729 & ARMV8_PMU_COUNTER_MASK; 730 } else if (r->Op2 == 0) { 731 /* PMCCNTR_EL0 */ 732 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 733 return false; 734 735 idx = ARMV8_PMU_CYCLE_IDX; 736 } 737 } else if (r->CRn == 0 && r->CRm == 9) { 738 /* PMCCNTR */ 739 if (pmu_access_event_counter_el0_disabled(vcpu)) 740 return false; 741 742 idx = ARMV8_PMU_CYCLE_IDX; 743 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 744 /* PMEVCNTRn_EL0 */ 745 if (pmu_access_event_counter_el0_disabled(vcpu)) 746 return false; 747 748 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 749 } 750 751 /* Catch any decoding mistake */ 752 WARN_ON(idx == ~0UL); 753 754 if (!pmu_counter_idx_valid(vcpu, idx)) 755 return false; 756 757 if (p->is_write) { 758 if (pmu_access_el0_disabled(vcpu)) 759 return false; 760 761 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 762 } else { 763 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 764 } 765 766 return true; 767 } 768 769 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 770 const struct sys_reg_desc *r) 771 { 772 u64 idx, reg; 773 774 if (pmu_access_el0_disabled(vcpu)) 775 return false; 776 777 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 778 /* PMXEVTYPER_EL0 */ 779 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; 780 reg = PMEVTYPER0_EL0 + idx; 781 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 782 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 783 if (idx == ARMV8_PMU_CYCLE_IDX) 784 reg = PMCCFILTR_EL0; 785 else 786 /* PMEVTYPERn_EL0 */ 787 reg = PMEVTYPER0_EL0 + idx; 788 } else { 789 BUG(); 790 } 791 792 if (!pmu_counter_idx_valid(vcpu, idx)) 793 return false; 794 795 if (p->is_write) { 796 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 797 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; 798 kvm_vcpu_pmu_restore_guest(vcpu); 799 } else { 800 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; 801 } 802 803 return true; 804 } 805 806 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 807 const struct sys_reg_desc *r) 808 { 809 u64 val, mask; 810 811 if (pmu_access_el0_disabled(vcpu)) 812 return false; 813 814 mask = kvm_pmu_valid_counter_mask(vcpu); 815 if (p->is_write) { 816 val = p->regval & mask; 817 if (r->Op2 & 0x1) { 818 /* accessing PMCNTENSET_EL0 */ 819 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 820 kvm_pmu_enable_counter_mask(vcpu, val); 821 kvm_vcpu_pmu_restore_guest(vcpu); 822 } else { 823 /* accessing PMCNTENCLR_EL0 */ 824 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 825 kvm_pmu_disable_counter_mask(vcpu, val); 826 } 827 } else { 828 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask; 829 } 830 831 return true; 832 } 833 834 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 835 const struct sys_reg_desc *r) 836 { 837 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 838 839 if (check_pmu_access_disabled(vcpu, 0)) 840 return false; 841 842 if (p->is_write) { 843 u64 val = p->regval & mask; 844 845 if (r->Op2 & 0x1) 846 /* accessing PMINTENSET_EL1 */ 847 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 848 else 849 /* accessing PMINTENCLR_EL1 */ 850 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 851 } else { 852 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask; 853 } 854 855 return true; 856 } 857 858 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 859 const struct sys_reg_desc *r) 860 { 861 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 862 863 if (pmu_access_el0_disabled(vcpu)) 864 return false; 865 866 if (p->is_write) { 867 if (r->CRm & 0x2) 868 /* accessing PMOVSSET_EL0 */ 869 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 870 else 871 /* accessing PMOVSCLR_EL0 */ 872 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 873 } else { 874 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask; 875 } 876 877 return true; 878 } 879 880 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 881 const struct sys_reg_desc *r) 882 { 883 u64 mask; 884 885 if (!p->is_write) 886 return read_from_write_only(vcpu, p, r); 887 888 if (pmu_write_swinc_el0_disabled(vcpu)) 889 return false; 890 891 mask = kvm_pmu_valid_counter_mask(vcpu); 892 kvm_pmu_software_increment(vcpu, p->regval & mask); 893 return true; 894 } 895 896 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 897 const struct sys_reg_desc *r) 898 { 899 if (!kvm_vcpu_has_pmu(vcpu)) { 900 kvm_inject_undefined(vcpu); 901 return false; 902 } 903 904 if (p->is_write) { 905 if (!vcpu_mode_priv(vcpu)) { 906 kvm_inject_undefined(vcpu); 907 return false; 908 } 909 910 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 911 p->regval & ARMV8_PMU_USERENR_MASK; 912 } else { 913 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 914 & ARMV8_PMU_USERENR_MASK; 915 } 916 917 return true; 918 } 919 920 #define reg_to_encoding(x) \ 921 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \ 922 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2); 923 924 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 925 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 926 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 927 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 928 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 929 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 930 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 931 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 932 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 933 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 934 935 /* Macro to expand the PMEVCNTRn_EL0 register */ 936 #define PMU_PMEVCNTR_EL0(n) \ 937 { SYS_DESC(SYS_PMEVCNTRn_EL0(n)), \ 938 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), } 939 940 /* Macro to expand the PMEVTYPERn_EL0 register */ 941 #define PMU_PMEVTYPER_EL0(n) \ 942 { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \ 943 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), } 944 945 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 946 const struct sys_reg_desc *r) 947 { 948 kvm_inject_undefined(vcpu); 949 950 return false; 951 } 952 953 /* Macro to expand the AMU counter and type registers*/ 954 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access } 955 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access } 956 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access } 957 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access } 958 959 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 960 const struct sys_reg_desc *rd) 961 { 962 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN; 963 } 964 965 /* 966 * If we land here on a PtrAuth access, that is because we didn't 967 * fixup the access on exit by allowing the PtrAuth sysregs. The only 968 * way this happens is when the guest does not have PtrAuth support 969 * enabled. 970 */ 971 #define __PTRAUTH_KEY(k) \ 972 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \ 973 .visibility = ptrauth_visibility} 974 975 #define PTRAUTH_KEY(k) \ 976 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 977 __PTRAUTH_KEY(k ## KEYHI_EL1) 978 979 static bool access_arch_timer(struct kvm_vcpu *vcpu, 980 struct sys_reg_params *p, 981 const struct sys_reg_desc *r) 982 { 983 enum kvm_arch_timers tmr; 984 enum kvm_arch_timer_regs treg; 985 u64 reg = reg_to_encoding(r); 986 987 switch (reg) { 988 case SYS_CNTP_TVAL_EL0: 989 case SYS_AARCH32_CNTP_TVAL: 990 tmr = TIMER_PTIMER; 991 treg = TIMER_REG_TVAL; 992 break; 993 case SYS_CNTP_CTL_EL0: 994 case SYS_AARCH32_CNTP_CTL: 995 tmr = TIMER_PTIMER; 996 treg = TIMER_REG_CTL; 997 break; 998 case SYS_CNTP_CVAL_EL0: 999 case SYS_AARCH32_CNTP_CVAL: 1000 tmr = TIMER_PTIMER; 1001 treg = TIMER_REG_CVAL; 1002 break; 1003 default: 1004 BUG(); 1005 } 1006 1007 if (p->is_write) 1008 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1009 else 1010 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1011 1012 return true; 1013 } 1014 1015 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1016 static u64 read_id_reg(const struct kvm_vcpu *vcpu, 1017 struct sys_reg_desc const *r, bool raz) 1018 { 1019 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1, 1020 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); 1021 u64 val = raz ? 0 : read_sanitised_ftr_reg(id); 1022 1023 if (id == SYS_ID_AA64PFR0_EL1) { 1024 if (!vcpu_has_sve(vcpu)) 1025 val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT); 1026 val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT); 1027 val &= ~(0xfUL << ID_AA64PFR0_CSV2_SHIFT); 1028 val |= ((u64)vcpu->kvm->arch.pfr0_csv2 << ID_AA64PFR0_CSV2_SHIFT); 1029 val &= ~(0xfUL << ID_AA64PFR0_CSV3_SHIFT); 1030 val |= ((u64)vcpu->kvm->arch.pfr0_csv3 << ID_AA64PFR0_CSV3_SHIFT); 1031 } else if (id == SYS_ID_AA64PFR1_EL1) { 1032 val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT); 1033 } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) { 1034 val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) | 1035 (0xfUL << ID_AA64ISAR1_API_SHIFT) | 1036 (0xfUL << ID_AA64ISAR1_GPA_SHIFT) | 1037 (0xfUL << ID_AA64ISAR1_GPI_SHIFT)); 1038 } else if (id == SYS_ID_AA64DFR0_EL1) { 1039 u64 cap = 0; 1040 1041 /* Limit guests to PMUv3 for ARMv8.1 */ 1042 if (kvm_vcpu_has_pmu(vcpu)) 1043 cap = ID_AA64DFR0_PMUVER_8_1; 1044 1045 val = cpuid_feature_cap_perfmon_field(val, 1046 ID_AA64DFR0_PMUVER_SHIFT, 1047 cap); 1048 } else if (id == SYS_ID_DFR0_EL1) { 1049 /* Limit guests to PMUv3 for ARMv8.1 */ 1050 val = cpuid_feature_cap_perfmon_field(val, 1051 ID_DFR0_PERFMON_SHIFT, 1052 ID_DFR0_PERFMON_8_1); 1053 } 1054 1055 return val; 1056 } 1057 1058 static unsigned int id_visibility(const struct kvm_vcpu *vcpu, 1059 const struct sys_reg_desc *r) 1060 { 1061 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1, 1062 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); 1063 1064 switch (id) { 1065 case SYS_ID_AA64ZFR0_EL1: 1066 if (!vcpu_has_sve(vcpu)) 1067 return REG_RAZ; 1068 break; 1069 } 1070 1071 return 0; 1072 } 1073 1074 /* cpufeature ID register access trap handlers */ 1075 1076 static bool __access_id_reg(struct kvm_vcpu *vcpu, 1077 struct sys_reg_params *p, 1078 const struct sys_reg_desc *r, 1079 bool raz) 1080 { 1081 if (p->is_write) 1082 return write_to_read_only(vcpu, p, r); 1083 1084 p->regval = read_id_reg(vcpu, r, raz); 1085 return true; 1086 } 1087 1088 static bool access_id_reg(struct kvm_vcpu *vcpu, 1089 struct sys_reg_params *p, 1090 const struct sys_reg_desc *r) 1091 { 1092 bool raz = sysreg_visible_as_raz(vcpu, r); 1093 1094 return __access_id_reg(vcpu, p, r, raz); 1095 } 1096 1097 static bool access_raz_id_reg(struct kvm_vcpu *vcpu, 1098 struct sys_reg_params *p, 1099 const struct sys_reg_desc *r) 1100 { 1101 return __access_id_reg(vcpu, p, r, true); 1102 } 1103 1104 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); 1105 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); 1106 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 1107 1108 /* Visibility overrides for SVE-specific control registers */ 1109 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1110 const struct sys_reg_desc *rd) 1111 { 1112 if (vcpu_has_sve(vcpu)) 1113 return 0; 1114 1115 return REG_HIDDEN; 1116 } 1117 1118 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, 1119 const struct sys_reg_desc *rd, 1120 const struct kvm_one_reg *reg, void __user *uaddr) 1121 { 1122 const u64 id = sys_reg_to_index(rd); 1123 u8 csv2, csv3; 1124 int err; 1125 u64 val; 1126 1127 err = reg_from_user(&val, uaddr, id); 1128 if (err) 1129 return err; 1130 1131 /* 1132 * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as 1133 * it doesn't promise more than what is actually provided (the 1134 * guest could otherwise be covered in ectoplasmic residue). 1135 */ 1136 csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV2_SHIFT); 1137 if (csv2 > 1 || 1138 (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED)) 1139 return -EINVAL; 1140 1141 /* Same thing for CSV3 */ 1142 csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV3_SHIFT); 1143 if (csv3 > 1 || 1144 (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED)) 1145 return -EINVAL; 1146 1147 /* We can only differ with CSV[23], and anything else is an error */ 1148 val ^= read_id_reg(vcpu, rd, false); 1149 val &= ~((0xFUL << ID_AA64PFR0_CSV2_SHIFT) | 1150 (0xFUL << ID_AA64PFR0_CSV3_SHIFT)); 1151 if (val) 1152 return -EINVAL; 1153 1154 vcpu->kvm->arch.pfr0_csv2 = csv2; 1155 vcpu->kvm->arch.pfr0_csv3 = csv3 ; 1156 1157 return 0; 1158 } 1159 1160 /* 1161 * cpufeature ID register user accessors 1162 * 1163 * For now, these registers are immutable for userspace, so no values 1164 * are stored, and for set_id_reg() we don't allow the effective value 1165 * to be changed. 1166 */ 1167 static int __get_id_reg(const struct kvm_vcpu *vcpu, 1168 const struct sys_reg_desc *rd, void __user *uaddr, 1169 bool raz) 1170 { 1171 const u64 id = sys_reg_to_index(rd); 1172 const u64 val = read_id_reg(vcpu, rd, raz); 1173 1174 return reg_to_user(uaddr, &val, id); 1175 } 1176 1177 static int __set_id_reg(const struct kvm_vcpu *vcpu, 1178 const struct sys_reg_desc *rd, void __user *uaddr, 1179 bool raz) 1180 { 1181 const u64 id = sys_reg_to_index(rd); 1182 int err; 1183 u64 val; 1184 1185 err = reg_from_user(&val, uaddr, id); 1186 if (err) 1187 return err; 1188 1189 /* This is what we mean by invariant: you can't change it. */ 1190 if (val != read_id_reg(vcpu, rd, raz)) 1191 return -EINVAL; 1192 1193 return 0; 1194 } 1195 1196 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1197 const struct kvm_one_reg *reg, void __user *uaddr) 1198 { 1199 bool raz = sysreg_visible_as_raz(vcpu, rd); 1200 1201 return __get_id_reg(vcpu, rd, uaddr, raz); 1202 } 1203 1204 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1205 const struct kvm_one_reg *reg, void __user *uaddr) 1206 { 1207 bool raz = sysreg_visible_as_raz(vcpu, rd); 1208 1209 return __set_id_reg(vcpu, rd, uaddr, raz); 1210 } 1211 1212 static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1213 const struct kvm_one_reg *reg, void __user *uaddr) 1214 { 1215 return __get_id_reg(vcpu, rd, uaddr, true); 1216 } 1217 1218 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1219 const struct kvm_one_reg *reg, void __user *uaddr) 1220 { 1221 return __set_id_reg(vcpu, rd, uaddr, true); 1222 } 1223 1224 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1225 const struct sys_reg_desc *r) 1226 { 1227 if (p->is_write) 1228 return write_to_read_only(vcpu, p, r); 1229 1230 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); 1231 return true; 1232 } 1233 1234 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1235 const struct sys_reg_desc *r) 1236 { 1237 if (p->is_write) 1238 return write_to_read_only(vcpu, p, r); 1239 1240 p->regval = read_sysreg(clidr_el1); 1241 return true; 1242 } 1243 1244 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1245 const struct sys_reg_desc *r) 1246 { 1247 int reg = r->reg; 1248 1249 if (p->is_write) 1250 vcpu_write_sys_reg(vcpu, p->regval, reg); 1251 else 1252 p->regval = vcpu_read_sys_reg(vcpu, reg); 1253 return true; 1254 } 1255 1256 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1257 const struct sys_reg_desc *r) 1258 { 1259 u32 csselr; 1260 1261 if (p->is_write) 1262 return write_to_read_only(vcpu, p, r); 1263 1264 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 1265 p->regval = get_ccsidr(csselr); 1266 1267 /* 1268 * Guests should not be doing cache operations by set/way at all, and 1269 * for this reason, we trap them and attempt to infer the intent, so 1270 * that we can flush the entire guest's address space at the appropriate 1271 * time. 1272 * To prevent this trapping from causing performance problems, let's 1273 * expose the geometry of all data and unified caches (which are 1274 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way. 1275 * [If guests should attempt to infer aliasing properties from the 1276 * geometry (which is not permitted by the architecture), they would 1277 * only do so for virtually indexed caches.] 1278 */ 1279 if (!(csselr & 1)) // data or unified cache 1280 p->regval &= ~GENMASK(27, 3); 1281 return true; 1282 } 1283 1284 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1285 #define ID_SANITISED(name) { \ 1286 SYS_DESC(SYS_##name), \ 1287 .access = access_id_reg, \ 1288 .get_user = get_id_reg, \ 1289 .set_user = set_id_reg, \ 1290 .visibility = id_visibility, \ 1291 } 1292 1293 /* 1294 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 1295 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 1296 * (1 <= crm < 8, 0 <= Op2 < 8). 1297 */ 1298 #define ID_UNALLOCATED(crm, op2) { \ 1299 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 1300 .access = access_raz_id_reg, \ 1301 .get_user = get_raz_id_reg, \ 1302 .set_user = set_raz_id_reg, \ 1303 } 1304 1305 /* 1306 * sys_reg_desc initialiser for known ID registers that we hide from guests. 1307 * For now, these are exposed just like unallocated ID regs: they appear 1308 * RAZ for the guest. 1309 */ 1310 #define ID_HIDDEN(name) { \ 1311 SYS_DESC(SYS_##name), \ 1312 .access = access_raz_id_reg, \ 1313 .get_user = get_raz_id_reg, \ 1314 .set_user = set_raz_id_reg, \ 1315 } 1316 1317 /* 1318 * Architected system registers. 1319 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 1320 * 1321 * Debug handling: We do trap most, if not all debug related system 1322 * registers. The implementation is good enough to ensure that a guest 1323 * can use these with minimal performance degradation. The drawback is 1324 * that we don't implement any of the external debug, none of the 1325 * OSlock protocol. This should be revisited if we ever encounter a 1326 * more demanding guest... 1327 */ 1328 static const struct sys_reg_desc sys_reg_descs[] = { 1329 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 1330 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 1331 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 1332 1333 DBG_BCR_BVR_WCR_WVR_EL1(0), 1334 DBG_BCR_BVR_WCR_WVR_EL1(1), 1335 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 1336 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 1337 DBG_BCR_BVR_WCR_WVR_EL1(2), 1338 DBG_BCR_BVR_WCR_WVR_EL1(3), 1339 DBG_BCR_BVR_WCR_WVR_EL1(4), 1340 DBG_BCR_BVR_WCR_WVR_EL1(5), 1341 DBG_BCR_BVR_WCR_WVR_EL1(6), 1342 DBG_BCR_BVR_WCR_WVR_EL1(7), 1343 DBG_BCR_BVR_WCR_WVR_EL1(8), 1344 DBG_BCR_BVR_WCR_WVR_EL1(9), 1345 DBG_BCR_BVR_WCR_WVR_EL1(10), 1346 DBG_BCR_BVR_WCR_WVR_EL1(11), 1347 DBG_BCR_BVR_WCR_WVR_EL1(12), 1348 DBG_BCR_BVR_WCR_WVR_EL1(13), 1349 DBG_BCR_BVR_WCR_WVR_EL1(14), 1350 DBG_BCR_BVR_WCR_WVR_EL1(15), 1351 1352 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 1353 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi }, 1354 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 }, 1355 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 1356 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 1357 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 1358 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 1359 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 1360 1361 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 1362 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 1363 // DBGDTR[TR]X_EL0 share the same encoding 1364 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 1365 1366 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 }, 1367 1368 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 1369 1370 /* 1371 * ID regs: all ID_SANITISED() entries here must have corresponding 1372 * entries in arm64_ftr_regs[]. 1373 */ 1374 1375 /* AArch64 mappings of the AArch32 ID registers */ 1376 /* CRm=1 */ 1377 ID_SANITISED(ID_PFR0_EL1), 1378 ID_SANITISED(ID_PFR1_EL1), 1379 ID_SANITISED(ID_DFR0_EL1), 1380 ID_HIDDEN(ID_AFR0_EL1), 1381 ID_SANITISED(ID_MMFR0_EL1), 1382 ID_SANITISED(ID_MMFR1_EL1), 1383 ID_SANITISED(ID_MMFR2_EL1), 1384 ID_SANITISED(ID_MMFR3_EL1), 1385 1386 /* CRm=2 */ 1387 ID_SANITISED(ID_ISAR0_EL1), 1388 ID_SANITISED(ID_ISAR1_EL1), 1389 ID_SANITISED(ID_ISAR2_EL1), 1390 ID_SANITISED(ID_ISAR3_EL1), 1391 ID_SANITISED(ID_ISAR4_EL1), 1392 ID_SANITISED(ID_ISAR5_EL1), 1393 ID_SANITISED(ID_MMFR4_EL1), 1394 ID_SANITISED(ID_ISAR6_EL1), 1395 1396 /* CRm=3 */ 1397 ID_SANITISED(MVFR0_EL1), 1398 ID_SANITISED(MVFR1_EL1), 1399 ID_SANITISED(MVFR2_EL1), 1400 ID_UNALLOCATED(3,3), 1401 ID_SANITISED(ID_PFR2_EL1), 1402 ID_HIDDEN(ID_DFR1_EL1), 1403 ID_SANITISED(ID_MMFR5_EL1), 1404 ID_UNALLOCATED(3,7), 1405 1406 /* AArch64 ID registers */ 1407 /* CRm=4 */ 1408 { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg, 1409 .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, }, 1410 ID_SANITISED(ID_AA64PFR1_EL1), 1411 ID_UNALLOCATED(4,2), 1412 ID_UNALLOCATED(4,3), 1413 ID_SANITISED(ID_AA64ZFR0_EL1), 1414 ID_UNALLOCATED(4,5), 1415 ID_UNALLOCATED(4,6), 1416 ID_UNALLOCATED(4,7), 1417 1418 /* CRm=5 */ 1419 ID_SANITISED(ID_AA64DFR0_EL1), 1420 ID_SANITISED(ID_AA64DFR1_EL1), 1421 ID_UNALLOCATED(5,2), 1422 ID_UNALLOCATED(5,3), 1423 ID_HIDDEN(ID_AA64AFR0_EL1), 1424 ID_HIDDEN(ID_AA64AFR1_EL1), 1425 ID_UNALLOCATED(5,6), 1426 ID_UNALLOCATED(5,7), 1427 1428 /* CRm=6 */ 1429 ID_SANITISED(ID_AA64ISAR0_EL1), 1430 ID_SANITISED(ID_AA64ISAR1_EL1), 1431 ID_UNALLOCATED(6,2), 1432 ID_UNALLOCATED(6,3), 1433 ID_UNALLOCATED(6,4), 1434 ID_UNALLOCATED(6,5), 1435 ID_UNALLOCATED(6,6), 1436 ID_UNALLOCATED(6,7), 1437 1438 /* CRm=7 */ 1439 ID_SANITISED(ID_AA64MMFR0_EL1), 1440 ID_SANITISED(ID_AA64MMFR1_EL1), 1441 ID_SANITISED(ID_AA64MMFR2_EL1), 1442 ID_UNALLOCATED(7,3), 1443 ID_UNALLOCATED(7,4), 1444 ID_UNALLOCATED(7,5), 1445 ID_UNALLOCATED(7,6), 1446 ID_UNALLOCATED(7,7), 1447 1448 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 1449 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 1450 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 1451 1452 { SYS_DESC(SYS_RGSR_EL1), undef_access }, 1453 { SYS_DESC(SYS_GCR_EL1), undef_access }, 1454 1455 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 1456 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 1457 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 1458 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 1459 1460 PTRAUTH_KEY(APIA), 1461 PTRAUTH_KEY(APIB), 1462 PTRAUTH_KEY(APDA), 1463 PTRAUTH_KEY(APDB), 1464 PTRAUTH_KEY(APGA), 1465 1466 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 1467 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 1468 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 1469 1470 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 1471 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 1472 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 1473 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 1474 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 1475 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 1476 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 1477 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 1478 1479 { SYS_DESC(SYS_TFSR_EL1), undef_access }, 1480 { SYS_DESC(SYS_TFSRE0_EL1), undef_access }, 1481 1482 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 1483 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 1484 1485 { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, 1486 { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, 1487 1488 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 1489 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 1490 1491 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 1492 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 1493 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 1494 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 1495 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 1496 1497 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 }, 1498 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 1499 1500 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, 1501 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, 1502 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, 1503 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, 1504 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, 1505 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 1506 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 1507 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 1508 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, 1509 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, 1510 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, 1511 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 1512 1513 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 1514 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 1515 1516 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access }, 1517 1518 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 1519 1520 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 1521 { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, 1522 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 1523 { SYS_DESC(SYS_CTR_EL0), access_ctr }, 1524 1525 { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 }, 1526 { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 }, 1527 { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 }, 1528 { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 }, 1529 { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 }, 1530 { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 }, 1531 { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid }, 1532 { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid }, 1533 { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 }, 1534 { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper }, 1535 { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr }, 1536 /* 1537 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 1538 * in 32bit mode. Here we choose to reset it as zero for consistency. 1539 */ 1540 { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 }, 1541 { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 }, 1542 1543 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 1544 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 1545 1546 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, 1547 1548 { SYS_DESC(SYS_AMCR_EL0), undef_access }, 1549 { SYS_DESC(SYS_AMCFGR_EL0), undef_access }, 1550 { SYS_DESC(SYS_AMCGCR_EL0), undef_access }, 1551 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access }, 1552 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access }, 1553 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access }, 1554 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access }, 1555 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access }, 1556 AMU_AMEVCNTR0_EL0(0), 1557 AMU_AMEVCNTR0_EL0(1), 1558 AMU_AMEVCNTR0_EL0(2), 1559 AMU_AMEVCNTR0_EL0(3), 1560 AMU_AMEVCNTR0_EL0(4), 1561 AMU_AMEVCNTR0_EL0(5), 1562 AMU_AMEVCNTR0_EL0(6), 1563 AMU_AMEVCNTR0_EL0(7), 1564 AMU_AMEVCNTR0_EL0(8), 1565 AMU_AMEVCNTR0_EL0(9), 1566 AMU_AMEVCNTR0_EL0(10), 1567 AMU_AMEVCNTR0_EL0(11), 1568 AMU_AMEVCNTR0_EL0(12), 1569 AMU_AMEVCNTR0_EL0(13), 1570 AMU_AMEVCNTR0_EL0(14), 1571 AMU_AMEVCNTR0_EL0(15), 1572 AMU_AMEVTYPER0_EL0(0), 1573 AMU_AMEVTYPER0_EL0(1), 1574 AMU_AMEVTYPER0_EL0(2), 1575 AMU_AMEVTYPER0_EL0(3), 1576 AMU_AMEVTYPER0_EL0(4), 1577 AMU_AMEVTYPER0_EL0(5), 1578 AMU_AMEVTYPER0_EL0(6), 1579 AMU_AMEVTYPER0_EL0(7), 1580 AMU_AMEVTYPER0_EL0(8), 1581 AMU_AMEVTYPER0_EL0(9), 1582 AMU_AMEVTYPER0_EL0(10), 1583 AMU_AMEVTYPER0_EL0(11), 1584 AMU_AMEVTYPER0_EL0(12), 1585 AMU_AMEVTYPER0_EL0(13), 1586 AMU_AMEVTYPER0_EL0(14), 1587 AMU_AMEVTYPER0_EL0(15), 1588 AMU_AMEVCNTR1_EL0(0), 1589 AMU_AMEVCNTR1_EL0(1), 1590 AMU_AMEVCNTR1_EL0(2), 1591 AMU_AMEVCNTR1_EL0(3), 1592 AMU_AMEVCNTR1_EL0(4), 1593 AMU_AMEVCNTR1_EL0(5), 1594 AMU_AMEVCNTR1_EL0(6), 1595 AMU_AMEVCNTR1_EL0(7), 1596 AMU_AMEVCNTR1_EL0(8), 1597 AMU_AMEVCNTR1_EL0(9), 1598 AMU_AMEVCNTR1_EL0(10), 1599 AMU_AMEVCNTR1_EL0(11), 1600 AMU_AMEVCNTR1_EL0(12), 1601 AMU_AMEVCNTR1_EL0(13), 1602 AMU_AMEVCNTR1_EL0(14), 1603 AMU_AMEVCNTR1_EL0(15), 1604 AMU_AMEVTYPER1_EL0(0), 1605 AMU_AMEVTYPER1_EL0(1), 1606 AMU_AMEVTYPER1_EL0(2), 1607 AMU_AMEVTYPER1_EL0(3), 1608 AMU_AMEVTYPER1_EL0(4), 1609 AMU_AMEVTYPER1_EL0(5), 1610 AMU_AMEVTYPER1_EL0(6), 1611 AMU_AMEVTYPER1_EL0(7), 1612 AMU_AMEVTYPER1_EL0(8), 1613 AMU_AMEVTYPER1_EL0(9), 1614 AMU_AMEVTYPER1_EL0(10), 1615 AMU_AMEVTYPER1_EL0(11), 1616 AMU_AMEVTYPER1_EL0(12), 1617 AMU_AMEVTYPER1_EL0(13), 1618 AMU_AMEVTYPER1_EL0(14), 1619 AMU_AMEVTYPER1_EL0(15), 1620 1621 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 1622 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 1623 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 1624 1625 /* PMEVCNTRn_EL0 */ 1626 PMU_PMEVCNTR_EL0(0), 1627 PMU_PMEVCNTR_EL0(1), 1628 PMU_PMEVCNTR_EL0(2), 1629 PMU_PMEVCNTR_EL0(3), 1630 PMU_PMEVCNTR_EL0(4), 1631 PMU_PMEVCNTR_EL0(5), 1632 PMU_PMEVCNTR_EL0(6), 1633 PMU_PMEVCNTR_EL0(7), 1634 PMU_PMEVCNTR_EL0(8), 1635 PMU_PMEVCNTR_EL0(9), 1636 PMU_PMEVCNTR_EL0(10), 1637 PMU_PMEVCNTR_EL0(11), 1638 PMU_PMEVCNTR_EL0(12), 1639 PMU_PMEVCNTR_EL0(13), 1640 PMU_PMEVCNTR_EL0(14), 1641 PMU_PMEVCNTR_EL0(15), 1642 PMU_PMEVCNTR_EL0(16), 1643 PMU_PMEVCNTR_EL0(17), 1644 PMU_PMEVCNTR_EL0(18), 1645 PMU_PMEVCNTR_EL0(19), 1646 PMU_PMEVCNTR_EL0(20), 1647 PMU_PMEVCNTR_EL0(21), 1648 PMU_PMEVCNTR_EL0(22), 1649 PMU_PMEVCNTR_EL0(23), 1650 PMU_PMEVCNTR_EL0(24), 1651 PMU_PMEVCNTR_EL0(25), 1652 PMU_PMEVCNTR_EL0(26), 1653 PMU_PMEVCNTR_EL0(27), 1654 PMU_PMEVCNTR_EL0(28), 1655 PMU_PMEVCNTR_EL0(29), 1656 PMU_PMEVCNTR_EL0(30), 1657 /* PMEVTYPERn_EL0 */ 1658 PMU_PMEVTYPER_EL0(0), 1659 PMU_PMEVTYPER_EL0(1), 1660 PMU_PMEVTYPER_EL0(2), 1661 PMU_PMEVTYPER_EL0(3), 1662 PMU_PMEVTYPER_EL0(4), 1663 PMU_PMEVTYPER_EL0(5), 1664 PMU_PMEVTYPER_EL0(6), 1665 PMU_PMEVTYPER_EL0(7), 1666 PMU_PMEVTYPER_EL0(8), 1667 PMU_PMEVTYPER_EL0(9), 1668 PMU_PMEVTYPER_EL0(10), 1669 PMU_PMEVTYPER_EL0(11), 1670 PMU_PMEVTYPER_EL0(12), 1671 PMU_PMEVTYPER_EL0(13), 1672 PMU_PMEVTYPER_EL0(14), 1673 PMU_PMEVTYPER_EL0(15), 1674 PMU_PMEVTYPER_EL0(16), 1675 PMU_PMEVTYPER_EL0(17), 1676 PMU_PMEVTYPER_EL0(18), 1677 PMU_PMEVTYPER_EL0(19), 1678 PMU_PMEVTYPER_EL0(20), 1679 PMU_PMEVTYPER_EL0(21), 1680 PMU_PMEVTYPER_EL0(22), 1681 PMU_PMEVTYPER_EL0(23), 1682 PMU_PMEVTYPER_EL0(24), 1683 PMU_PMEVTYPER_EL0(25), 1684 PMU_PMEVTYPER_EL0(26), 1685 PMU_PMEVTYPER_EL0(27), 1686 PMU_PMEVTYPER_EL0(28), 1687 PMU_PMEVTYPER_EL0(29), 1688 PMU_PMEVTYPER_EL0(30), 1689 /* 1690 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 1691 * in 32bit mode. Here we choose to reset it as zero for consistency. 1692 */ 1693 { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 }, 1694 1695 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, 1696 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, 1697 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 }, 1698 }; 1699 1700 static bool trap_dbgidr(struct kvm_vcpu *vcpu, 1701 struct sys_reg_params *p, 1702 const struct sys_reg_desc *r) 1703 { 1704 if (p->is_write) { 1705 return ignore_write(vcpu, p); 1706 } else { 1707 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1708 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1709 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT); 1710 1711 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | 1712 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | 1713 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) 1714 | (6 << 16) | (el3 << 14) | (el3 << 12)); 1715 return true; 1716 } 1717 } 1718 1719 /* 1720 * AArch32 debug register mappings 1721 * 1722 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 1723 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 1724 * 1725 * None of the other registers share their location, so treat them as 1726 * if they were 64bit. 1727 */ 1728 #define DBG_BCR_BVR_WCR_WVR(n) \ 1729 /* DBGBVRn */ \ 1730 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 1731 /* DBGBCRn */ \ 1732 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 1733 /* DBGWVRn */ \ 1734 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 1735 /* DBGWCRn */ \ 1736 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 1737 1738 #define DBGBXVR(n) \ 1739 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n } 1740 1741 /* 1742 * Trapped cp14 registers. We generally ignore most of the external 1743 * debug, on the principle that they don't really make sense to a 1744 * guest. Revisit this one day, would this principle change. 1745 */ 1746 static const struct sys_reg_desc cp14_regs[] = { 1747 /* DBGIDR */ 1748 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr }, 1749 /* DBGDTRRXext */ 1750 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 1751 1752 DBG_BCR_BVR_WCR_WVR(0), 1753 /* DBGDSCRint */ 1754 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 1755 DBG_BCR_BVR_WCR_WVR(1), 1756 /* DBGDCCINT */ 1757 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 }, 1758 /* DBGDSCRext */ 1759 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 }, 1760 DBG_BCR_BVR_WCR_WVR(2), 1761 /* DBGDTR[RT]Xint */ 1762 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 1763 /* DBGDTR[RT]Xext */ 1764 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 1765 DBG_BCR_BVR_WCR_WVR(3), 1766 DBG_BCR_BVR_WCR_WVR(4), 1767 DBG_BCR_BVR_WCR_WVR(5), 1768 /* DBGWFAR */ 1769 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 1770 /* DBGOSECCR */ 1771 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 1772 DBG_BCR_BVR_WCR_WVR(6), 1773 /* DBGVCR */ 1774 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 }, 1775 DBG_BCR_BVR_WCR_WVR(7), 1776 DBG_BCR_BVR_WCR_WVR(8), 1777 DBG_BCR_BVR_WCR_WVR(9), 1778 DBG_BCR_BVR_WCR_WVR(10), 1779 DBG_BCR_BVR_WCR_WVR(11), 1780 DBG_BCR_BVR_WCR_WVR(12), 1781 DBG_BCR_BVR_WCR_WVR(13), 1782 DBG_BCR_BVR_WCR_WVR(14), 1783 DBG_BCR_BVR_WCR_WVR(15), 1784 1785 /* DBGDRAR (32bit) */ 1786 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 1787 1788 DBGBXVR(0), 1789 /* DBGOSLAR */ 1790 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, 1791 DBGBXVR(1), 1792 /* DBGOSLSR */ 1793 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 }, 1794 DBGBXVR(2), 1795 DBGBXVR(3), 1796 /* DBGOSDLR */ 1797 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 1798 DBGBXVR(4), 1799 /* DBGPRCR */ 1800 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 1801 DBGBXVR(5), 1802 DBGBXVR(6), 1803 DBGBXVR(7), 1804 DBGBXVR(8), 1805 DBGBXVR(9), 1806 DBGBXVR(10), 1807 DBGBXVR(11), 1808 DBGBXVR(12), 1809 DBGBXVR(13), 1810 DBGBXVR(14), 1811 DBGBXVR(15), 1812 1813 /* DBGDSAR (32bit) */ 1814 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 1815 1816 /* DBGDEVID2 */ 1817 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 1818 /* DBGDEVID1 */ 1819 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 1820 /* DBGDEVID */ 1821 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 1822 /* DBGCLAIMSET */ 1823 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 1824 /* DBGCLAIMCLR */ 1825 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 1826 /* DBGAUTHSTATUS */ 1827 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 1828 }; 1829 1830 /* Trapped cp14 64bit registers */ 1831 static const struct sys_reg_desc cp14_64_regs[] = { 1832 /* DBGDRAR (64bit) */ 1833 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 1834 1835 /* DBGDSAR (64bit) */ 1836 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 1837 }; 1838 1839 /* Macro to expand the PMEVCNTRn register */ 1840 #define PMU_PMEVCNTR(n) \ 1841 /* PMEVCNTRn */ \ 1842 { Op1(0), CRn(0b1110), \ 1843 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 1844 access_pmu_evcntr } 1845 1846 /* Macro to expand the PMEVTYPERn register */ 1847 #define PMU_PMEVTYPER(n) \ 1848 /* PMEVTYPERn */ \ 1849 { Op1(0), CRn(0b1110), \ 1850 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 1851 access_pmu_evtyper } 1852 1853 /* 1854 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 1855 * depending on the way they are accessed (as a 32bit or a 64bit 1856 * register). 1857 */ 1858 static const struct sys_reg_desc cp15_regs[] = { 1859 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 1860 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 }, 1861 /* ACTLR */ 1862 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 }, 1863 /* ACTLR2 */ 1864 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 }, 1865 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 1866 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 }, 1867 /* TTBCR */ 1868 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 }, 1869 /* TTBCR2 */ 1870 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 }, 1871 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 }, 1872 /* DFSR */ 1873 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 }, 1874 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 }, 1875 /* ADFSR */ 1876 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 }, 1877 /* AIFSR */ 1878 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 }, 1879 /* DFAR */ 1880 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 }, 1881 /* IFAR */ 1882 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 }, 1883 1884 /* 1885 * DC{C,I,CI}SW operations: 1886 */ 1887 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 1888 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 1889 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 1890 1891 /* PMU */ 1892 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr }, 1893 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten }, 1894 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten }, 1895 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, 1896 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, 1897 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, 1898 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, 1899 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, 1900 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr }, 1901 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper }, 1902 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr }, 1903 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr }, 1904 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten }, 1905 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten }, 1906 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs }, 1907 1908 /* PRRR/MAIR0 */ 1909 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 }, 1910 /* NMRR/MAIR1 */ 1911 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 }, 1912 /* AMAIR0 */ 1913 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 }, 1914 /* AMAIR1 */ 1915 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 }, 1916 1917 /* ICC_SRE */ 1918 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, 1919 1920 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 }, 1921 1922 /* Arch Tmers */ 1923 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 1924 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 1925 1926 /* PMEVCNTRn */ 1927 PMU_PMEVCNTR(0), 1928 PMU_PMEVCNTR(1), 1929 PMU_PMEVCNTR(2), 1930 PMU_PMEVCNTR(3), 1931 PMU_PMEVCNTR(4), 1932 PMU_PMEVCNTR(5), 1933 PMU_PMEVCNTR(6), 1934 PMU_PMEVCNTR(7), 1935 PMU_PMEVCNTR(8), 1936 PMU_PMEVCNTR(9), 1937 PMU_PMEVCNTR(10), 1938 PMU_PMEVCNTR(11), 1939 PMU_PMEVCNTR(12), 1940 PMU_PMEVCNTR(13), 1941 PMU_PMEVCNTR(14), 1942 PMU_PMEVCNTR(15), 1943 PMU_PMEVCNTR(16), 1944 PMU_PMEVCNTR(17), 1945 PMU_PMEVCNTR(18), 1946 PMU_PMEVCNTR(19), 1947 PMU_PMEVCNTR(20), 1948 PMU_PMEVCNTR(21), 1949 PMU_PMEVCNTR(22), 1950 PMU_PMEVCNTR(23), 1951 PMU_PMEVCNTR(24), 1952 PMU_PMEVCNTR(25), 1953 PMU_PMEVCNTR(26), 1954 PMU_PMEVCNTR(27), 1955 PMU_PMEVCNTR(28), 1956 PMU_PMEVCNTR(29), 1957 PMU_PMEVCNTR(30), 1958 /* PMEVTYPERn */ 1959 PMU_PMEVTYPER(0), 1960 PMU_PMEVTYPER(1), 1961 PMU_PMEVTYPER(2), 1962 PMU_PMEVTYPER(3), 1963 PMU_PMEVTYPER(4), 1964 PMU_PMEVTYPER(5), 1965 PMU_PMEVTYPER(6), 1966 PMU_PMEVTYPER(7), 1967 PMU_PMEVTYPER(8), 1968 PMU_PMEVTYPER(9), 1969 PMU_PMEVTYPER(10), 1970 PMU_PMEVTYPER(11), 1971 PMU_PMEVTYPER(12), 1972 PMU_PMEVTYPER(13), 1973 PMU_PMEVTYPER(14), 1974 PMU_PMEVTYPER(15), 1975 PMU_PMEVTYPER(16), 1976 PMU_PMEVTYPER(17), 1977 PMU_PMEVTYPER(18), 1978 PMU_PMEVTYPER(19), 1979 PMU_PMEVTYPER(20), 1980 PMU_PMEVTYPER(21), 1981 PMU_PMEVTYPER(22), 1982 PMU_PMEVTYPER(23), 1983 PMU_PMEVTYPER(24), 1984 PMU_PMEVTYPER(25), 1985 PMU_PMEVTYPER(26), 1986 PMU_PMEVTYPER(27), 1987 PMU_PMEVTYPER(28), 1988 PMU_PMEVTYPER(29), 1989 PMU_PMEVTYPER(30), 1990 /* PMCCFILTR */ 1991 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper }, 1992 1993 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 1994 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 1995 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, 1996 }; 1997 1998 static const struct sys_reg_desc cp15_64_regs[] = { 1999 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 }, 2000 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr }, 2001 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 2002 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 }, 2003 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 2004 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 2005 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 2006 }; 2007 2008 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 2009 bool is_32) 2010 { 2011 unsigned int i; 2012 2013 for (i = 0; i < n; i++) { 2014 if (!is_32 && table[i].reg && !table[i].reset) { 2015 kvm_err("sys_reg table %p entry %d has lacks reset\n", 2016 table, i); 2017 return 1; 2018 } 2019 2020 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 2021 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1); 2022 return 1; 2023 } 2024 } 2025 2026 return 0; 2027 } 2028 2029 static int match_sys_reg(const void *key, const void *elt) 2030 { 2031 const unsigned long pval = (unsigned long)key; 2032 const struct sys_reg_desc *r = elt; 2033 2034 return pval - reg_to_encoding(r); 2035 } 2036 2037 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params, 2038 const struct sys_reg_desc table[], 2039 unsigned int num) 2040 { 2041 unsigned long pval = reg_to_encoding(params); 2042 2043 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg); 2044 } 2045 2046 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 2047 { 2048 kvm_inject_undefined(vcpu); 2049 return 1; 2050 } 2051 2052 static void perform_access(struct kvm_vcpu *vcpu, 2053 struct sys_reg_params *params, 2054 const struct sys_reg_desc *r) 2055 { 2056 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 2057 2058 /* Check for regs disabled by runtime config */ 2059 if (sysreg_hidden(vcpu, r)) { 2060 kvm_inject_undefined(vcpu); 2061 return; 2062 } 2063 2064 /* 2065 * Not having an accessor means that we have configured a trap 2066 * that we don't know how to handle. This certainly qualifies 2067 * as a gross bug that should be fixed right away. 2068 */ 2069 BUG_ON(!r->access); 2070 2071 /* Skip instruction if instructed so */ 2072 if (likely(r->access(vcpu, params, r))) 2073 kvm_incr_pc(vcpu); 2074 } 2075 2076 /* 2077 * emulate_cp -- tries to match a sys_reg access in a handling table, and 2078 * call the corresponding trap handler. 2079 * 2080 * @params: pointer to the descriptor of the access 2081 * @table: array of trap descriptors 2082 * @num: size of the trap descriptor array 2083 * 2084 * Return 0 if the access has been handled, and -1 if not. 2085 */ 2086 static int emulate_cp(struct kvm_vcpu *vcpu, 2087 struct sys_reg_params *params, 2088 const struct sys_reg_desc *table, 2089 size_t num) 2090 { 2091 const struct sys_reg_desc *r; 2092 2093 if (!table) 2094 return -1; /* Not handled */ 2095 2096 r = find_reg(params, table, num); 2097 2098 if (r) { 2099 perform_access(vcpu, params, r); 2100 return 0; 2101 } 2102 2103 /* Not handled */ 2104 return -1; 2105 } 2106 2107 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 2108 struct sys_reg_params *params) 2109 { 2110 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 2111 int cp = -1; 2112 2113 switch (esr_ec) { 2114 case ESR_ELx_EC_CP15_32: 2115 case ESR_ELx_EC_CP15_64: 2116 cp = 15; 2117 break; 2118 case ESR_ELx_EC_CP14_MR: 2119 case ESR_ELx_EC_CP14_64: 2120 cp = 14; 2121 break; 2122 default: 2123 WARN_ON(1); 2124 } 2125 2126 print_sys_reg_msg(params, 2127 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 2128 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2129 kvm_inject_undefined(vcpu); 2130 } 2131 2132 /** 2133 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 2134 * @vcpu: The VCPU pointer 2135 * @run: The kvm_run struct 2136 */ 2137 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 2138 const struct sys_reg_desc *global, 2139 size_t nr_global) 2140 { 2141 struct sys_reg_params params; 2142 u32 esr = kvm_vcpu_get_esr(vcpu); 2143 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2144 int Rt2 = (esr >> 10) & 0x1f; 2145 2146 params.CRm = (esr >> 1) & 0xf; 2147 params.is_write = ((esr & 1) == 0); 2148 2149 params.Op0 = 0; 2150 params.Op1 = (esr >> 16) & 0xf; 2151 params.Op2 = 0; 2152 params.CRn = 0; 2153 2154 /* 2155 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 2156 * backends between AArch32 and AArch64, we get away with it. 2157 */ 2158 if (params.is_write) { 2159 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 2160 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 2161 } 2162 2163 /* 2164 * If the table contains a handler, handle the 2165 * potential register operation in the case of a read and return 2166 * with success. 2167 */ 2168 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { 2169 /* Split up the value between registers for the read side */ 2170 if (!params.is_write) { 2171 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 2172 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 2173 } 2174 2175 return 1; 2176 } 2177 2178 unhandled_cp_access(vcpu, ¶ms); 2179 return 1; 2180 } 2181 2182 /** 2183 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 2184 * @vcpu: The VCPU pointer 2185 * @run: The kvm_run struct 2186 */ 2187 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 2188 const struct sys_reg_desc *global, 2189 size_t nr_global) 2190 { 2191 struct sys_reg_params params; 2192 u32 esr = kvm_vcpu_get_esr(vcpu); 2193 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2194 2195 params.CRm = (esr >> 1) & 0xf; 2196 params.regval = vcpu_get_reg(vcpu, Rt); 2197 params.is_write = ((esr & 1) == 0); 2198 params.CRn = (esr >> 10) & 0xf; 2199 params.Op0 = 0; 2200 params.Op1 = (esr >> 14) & 0x7; 2201 params.Op2 = (esr >> 17) & 0x7; 2202 2203 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { 2204 if (!params.is_write) 2205 vcpu_set_reg(vcpu, Rt, params.regval); 2206 return 1; 2207 } 2208 2209 unhandled_cp_access(vcpu, ¶ms); 2210 return 1; 2211 } 2212 2213 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 2214 { 2215 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 2216 } 2217 2218 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 2219 { 2220 return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs)); 2221 } 2222 2223 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 2224 { 2225 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 2226 } 2227 2228 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 2229 { 2230 return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs)); 2231 } 2232 2233 static bool is_imp_def_sys_reg(struct sys_reg_params *params) 2234 { 2235 // See ARM DDI 0487E.a, section D12.3.2 2236 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011; 2237 } 2238 2239 static int emulate_sys_reg(struct kvm_vcpu *vcpu, 2240 struct sys_reg_params *params) 2241 { 2242 const struct sys_reg_desc *r; 2243 2244 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2245 2246 if (likely(r)) { 2247 perform_access(vcpu, params, r); 2248 } else if (is_imp_def_sys_reg(params)) { 2249 kvm_inject_undefined(vcpu); 2250 } else { 2251 print_sys_reg_msg(params, 2252 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 2253 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2254 kvm_inject_undefined(vcpu); 2255 } 2256 return 1; 2257 } 2258 2259 /** 2260 * kvm_reset_sys_regs - sets system registers to reset value 2261 * @vcpu: The VCPU pointer 2262 * 2263 * This function finds the right table above and sets the registers on the 2264 * virtual CPU struct to their architecturally defined reset values. 2265 */ 2266 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 2267 { 2268 unsigned long i; 2269 2270 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) 2271 if (sys_reg_descs[i].reset) 2272 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]); 2273 } 2274 2275 /** 2276 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access 2277 * @vcpu: The VCPU pointer 2278 */ 2279 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 2280 { 2281 struct sys_reg_params params; 2282 unsigned long esr = kvm_vcpu_get_esr(vcpu); 2283 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2284 int ret; 2285 2286 trace_kvm_handle_sys_reg(esr); 2287 2288 params.Op0 = (esr >> 20) & 3; 2289 params.Op1 = (esr >> 14) & 0x7; 2290 params.CRn = (esr >> 10) & 0xf; 2291 params.CRm = (esr >> 1) & 0xf; 2292 params.Op2 = (esr >> 17) & 0x7; 2293 params.regval = vcpu_get_reg(vcpu, Rt); 2294 params.is_write = !(esr & 1); 2295 2296 ret = emulate_sys_reg(vcpu, ¶ms); 2297 2298 if (!params.is_write) 2299 vcpu_set_reg(vcpu, Rt, params.regval); 2300 return ret; 2301 } 2302 2303 /****************************************************************************** 2304 * Userspace API 2305 *****************************************************************************/ 2306 2307 static bool index_to_params(u64 id, struct sys_reg_params *params) 2308 { 2309 switch (id & KVM_REG_SIZE_MASK) { 2310 case KVM_REG_SIZE_U64: 2311 /* Any unused index bits means it's not valid. */ 2312 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 2313 | KVM_REG_ARM_COPROC_MASK 2314 | KVM_REG_ARM64_SYSREG_OP0_MASK 2315 | KVM_REG_ARM64_SYSREG_OP1_MASK 2316 | KVM_REG_ARM64_SYSREG_CRN_MASK 2317 | KVM_REG_ARM64_SYSREG_CRM_MASK 2318 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 2319 return false; 2320 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 2321 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 2322 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 2323 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 2324 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 2325 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 2326 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 2327 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 2328 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 2329 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 2330 return true; 2331 default: 2332 return false; 2333 } 2334 } 2335 2336 const struct sys_reg_desc *find_reg_by_id(u64 id, 2337 struct sys_reg_params *params, 2338 const struct sys_reg_desc table[], 2339 unsigned int num) 2340 { 2341 if (!index_to_params(id, params)) 2342 return NULL; 2343 2344 return find_reg(params, table, num); 2345 } 2346 2347 /* Decode an index value, and find the sys_reg_desc entry. */ 2348 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu, 2349 u64 id) 2350 { 2351 const struct sys_reg_desc *r; 2352 struct sys_reg_params params; 2353 2354 /* We only do sys_reg for now. */ 2355 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 2356 return NULL; 2357 2358 if (!index_to_params(id, ¶ms)) 2359 return NULL; 2360 2361 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2362 2363 /* Not saved in the sys_reg array and not otherwise accessible? */ 2364 if (r && !(r->reg || r->get_user)) 2365 r = NULL; 2366 2367 return r; 2368 } 2369 2370 /* 2371 * These are the invariant sys_reg registers: we let the guest see the 2372 * host versions of these, so they're part of the guest state. 2373 * 2374 * A future CPU may provide a mechanism to present different values to 2375 * the guest, or a future kvm may trap them. 2376 */ 2377 2378 #define FUNCTION_INVARIANT(reg) \ 2379 static void get_##reg(struct kvm_vcpu *v, \ 2380 const struct sys_reg_desc *r) \ 2381 { \ 2382 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 2383 } 2384 2385 FUNCTION_INVARIANT(midr_el1) 2386 FUNCTION_INVARIANT(revidr_el1) 2387 FUNCTION_INVARIANT(clidr_el1) 2388 FUNCTION_INVARIANT(aidr_el1) 2389 2390 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) 2391 { 2392 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); 2393 } 2394 2395 /* ->val is filled in by kvm_sys_reg_table_init() */ 2396 static struct sys_reg_desc invariant_sys_regs[] = { 2397 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, 2398 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, 2399 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 }, 2400 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, 2401 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, 2402 }; 2403 2404 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id) 2405 { 2406 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0) 2407 return -EFAULT; 2408 return 0; 2409 } 2410 2411 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id) 2412 { 2413 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0) 2414 return -EFAULT; 2415 return 0; 2416 } 2417 2418 static int get_invariant_sys_reg(u64 id, void __user *uaddr) 2419 { 2420 struct sys_reg_params params; 2421 const struct sys_reg_desc *r; 2422 2423 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2424 ARRAY_SIZE(invariant_sys_regs)); 2425 if (!r) 2426 return -ENOENT; 2427 2428 return reg_to_user(uaddr, &r->val, id); 2429 } 2430 2431 static int set_invariant_sys_reg(u64 id, void __user *uaddr) 2432 { 2433 struct sys_reg_params params; 2434 const struct sys_reg_desc *r; 2435 int err; 2436 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */ 2437 2438 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2439 ARRAY_SIZE(invariant_sys_regs)); 2440 if (!r) 2441 return -ENOENT; 2442 2443 err = reg_from_user(&val, uaddr, id); 2444 if (err) 2445 return err; 2446 2447 /* This is what we mean by invariant: you can't change it. */ 2448 if (r->val != val) 2449 return -EINVAL; 2450 2451 return 0; 2452 } 2453 2454 static bool is_valid_cache(u32 val) 2455 { 2456 u32 level, ctype; 2457 2458 if (val >= CSSELR_MAX) 2459 return false; 2460 2461 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ 2462 level = (val >> 1); 2463 ctype = (cache_levels >> (level * 3)) & 7; 2464 2465 switch (ctype) { 2466 case 0: /* No cache */ 2467 return false; 2468 case 1: /* Instruction cache only */ 2469 return (val & 1); 2470 case 2: /* Data cache only */ 2471 case 4: /* Unified cache */ 2472 return !(val & 1); 2473 case 3: /* Separate instruction and data caches */ 2474 return true; 2475 default: /* Reserved: we can't know instruction or data. */ 2476 return false; 2477 } 2478 } 2479 2480 static int demux_c15_get(u64 id, void __user *uaddr) 2481 { 2482 u32 val; 2483 u32 __user *uval = uaddr; 2484 2485 /* Fail if we have unknown bits set. */ 2486 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2487 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2488 return -ENOENT; 2489 2490 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2491 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2492 if (KVM_REG_SIZE(id) != 4) 2493 return -ENOENT; 2494 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2495 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2496 if (!is_valid_cache(val)) 2497 return -ENOENT; 2498 2499 return put_user(get_ccsidr(val), uval); 2500 default: 2501 return -ENOENT; 2502 } 2503 } 2504 2505 static int demux_c15_set(u64 id, void __user *uaddr) 2506 { 2507 u32 val, newval; 2508 u32 __user *uval = uaddr; 2509 2510 /* Fail if we have unknown bits set. */ 2511 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2512 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2513 return -ENOENT; 2514 2515 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2516 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2517 if (KVM_REG_SIZE(id) != 4) 2518 return -ENOENT; 2519 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2520 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2521 if (!is_valid_cache(val)) 2522 return -ENOENT; 2523 2524 if (get_user(newval, uval)) 2525 return -EFAULT; 2526 2527 /* This is also invariant: you can't change it. */ 2528 if (newval != get_ccsidr(val)) 2529 return -EINVAL; 2530 return 0; 2531 default: 2532 return -ENOENT; 2533 } 2534 } 2535 2536 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2537 { 2538 const struct sys_reg_desc *r; 2539 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2540 2541 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2542 return demux_c15_get(reg->id, uaddr); 2543 2544 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2545 return -ENOENT; 2546 2547 r = index_to_sys_reg_desc(vcpu, reg->id); 2548 if (!r) 2549 return get_invariant_sys_reg(reg->id, uaddr); 2550 2551 /* Check for regs disabled by runtime config */ 2552 if (sysreg_hidden(vcpu, r)) 2553 return -ENOENT; 2554 2555 if (r->get_user) 2556 return (r->get_user)(vcpu, r, reg, uaddr); 2557 2558 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id); 2559 } 2560 2561 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2562 { 2563 const struct sys_reg_desc *r; 2564 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2565 2566 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2567 return demux_c15_set(reg->id, uaddr); 2568 2569 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2570 return -ENOENT; 2571 2572 r = index_to_sys_reg_desc(vcpu, reg->id); 2573 if (!r) 2574 return set_invariant_sys_reg(reg->id, uaddr); 2575 2576 /* Check for regs disabled by runtime config */ 2577 if (sysreg_hidden(vcpu, r)) 2578 return -ENOENT; 2579 2580 if (r->set_user) 2581 return (r->set_user)(vcpu, r, reg, uaddr); 2582 2583 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id); 2584 } 2585 2586 static unsigned int num_demux_regs(void) 2587 { 2588 unsigned int i, count = 0; 2589 2590 for (i = 0; i < CSSELR_MAX; i++) 2591 if (is_valid_cache(i)) 2592 count++; 2593 2594 return count; 2595 } 2596 2597 static int write_demux_regids(u64 __user *uindices) 2598 { 2599 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 2600 unsigned int i; 2601 2602 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 2603 for (i = 0; i < CSSELR_MAX; i++) { 2604 if (!is_valid_cache(i)) 2605 continue; 2606 if (put_user(val | i, uindices)) 2607 return -EFAULT; 2608 uindices++; 2609 } 2610 return 0; 2611 } 2612 2613 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 2614 { 2615 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 2616 KVM_REG_ARM64_SYSREG | 2617 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 2618 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 2619 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 2620 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 2621 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 2622 } 2623 2624 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 2625 { 2626 if (!*uind) 2627 return true; 2628 2629 if (put_user(sys_reg_to_index(reg), *uind)) 2630 return false; 2631 2632 (*uind)++; 2633 return true; 2634 } 2635 2636 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 2637 const struct sys_reg_desc *rd, 2638 u64 __user **uind, 2639 unsigned int *total) 2640 { 2641 /* 2642 * Ignore registers we trap but don't save, 2643 * and for which no custom user accessor is provided. 2644 */ 2645 if (!(rd->reg || rd->get_user)) 2646 return 0; 2647 2648 if (sysreg_hidden(vcpu, rd)) 2649 return 0; 2650 2651 if (!copy_reg_to_user(rd, uind)) 2652 return -EFAULT; 2653 2654 (*total)++; 2655 return 0; 2656 } 2657 2658 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 2659 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 2660 { 2661 const struct sys_reg_desc *i2, *end2; 2662 unsigned int total = 0; 2663 int err; 2664 2665 i2 = sys_reg_descs; 2666 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 2667 2668 while (i2 != end2) { 2669 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 2670 if (err) 2671 return err; 2672 } 2673 return total; 2674 } 2675 2676 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 2677 { 2678 return ARRAY_SIZE(invariant_sys_regs) 2679 + num_demux_regs() 2680 + walk_sys_regs(vcpu, (u64 __user *)NULL); 2681 } 2682 2683 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 2684 { 2685 unsigned int i; 2686 int err; 2687 2688 /* Then give them all the invariant registers' indices. */ 2689 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 2690 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 2691 return -EFAULT; 2692 uindices++; 2693 } 2694 2695 err = walk_sys_regs(vcpu, uindices); 2696 if (err < 0) 2697 return err; 2698 uindices += err; 2699 2700 return write_demux_regids(uindices); 2701 } 2702 2703 void kvm_sys_reg_table_init(void) 2704 { 2705 unsigned int i; 2706 struct sys_reg_desc clidr; 2707 2708 /* Make sure tables are unique and in order. */ 2709 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false)); 2710 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true)); 2711 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true)); 2712 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true)); 2713 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true)); 2714 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false)); 2715 2716 /* We abuse the reset function to overwrite the table itself. */ 2717 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 2718 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 2719 2720 /* 2721 * CLIDR format is awkward, so clean it up. See ARM B4.1.20: 2722 * 2723 * If software reads the Cache Type fields from Ctype1 2724 * upwards, once it has seen a value of 0b000, no caches 2725 * exist at further-out levels of the hierarchy. So, for 2726 * example, if Ctype3 is the first Cache Type field with a 2727 * value of 0b000, the values of Ctype4 to Ctype7 must be 2728 * ignored. 2729 */ 2730 get_clidr_el1(NULL, &clidr); /* Ugly... */ 2731 cache_levels = clidr.val; 2732 for (i = 0; i < 7; i++) 2733 if (((cache_levels >> (i*3)) & 7) == 0) 2734 break; 2735 /* Clear all higher bits. */ 2736 cache_levels &= (1 << (i*3))-1; 2737 } 2738