1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level CPU initialisation 4 * Based on arch/arm/kernel/head.S 5 * 6 * Copyright (C) 1994-2002 Russell King 7 * Copyright (C) 2003-2012 ARM Ltd. 8 * Authors: Catalin Marinas <catalin.marinas@arm.com> 9 * Will Deacon <will.deacon@arm.com> 10 */ 11 12#include <linux/linkage.h> 13#include <linux/init.h> 14#include <linux/pgtable.h> 15 16#include <asm/asm_pointer_auth.h> 17#include <asm/assembler.h> 18#include <asm/boot.h> 19#include <asm/bug.h> 20#include <asm/ptrace.h> 21#include <asm/asm-offsets.h> 22#include <asm/cache.h> 23#include <asm/cputype.h> 24#include <asm/el2_setup.h> 25#include <asm/elf.h> 26#include <asm/image.h> 27#include <asm/kernel-pgtable.h> 28#include <asm/kvm_arm.h> 29#include <asm/memory.h> 30#include <asm/pgtable-hwdef.h> 31#include <asm/page.h> 32#include <asm/scs.h> 33#include <asm/smp.h> 34#include <asm/sysreg.h> 35#include <asm/thread_info.h> 36#include <asm/virt.h> 37 38#include "efi-header.S" 39 40#define __PHYS_OFFSET KERNEL_START 41 42#if (PAGE_OFFSET & 0x1fffff) != 0 43#error PAGE_OFFSET must be at least 2MB aligned 44#endif 45 46/* 47 * Kernel startup entry point. 48 * --------------------------- 49 * 50 * The requirements are: 51 * MMU = off, D-cache = off, I-cache = on or off, 52 * x0 = physical address to the FDT blob. 53 * 54 * This code is mostly position independent so you call this at 55 * __pa(PAGE_OFFSET). 56 * 57 * Note that the callee-saved registers are used for storing variables 58 * that are useful before the MMU is enabled. The allocations are described 59 * in the entry routines. 60 */ 61 __HEAD 62 /* 63 * DO NOT MODIFY. Image header expected by Linux boot-loaders. 64 */ 65 efi_signature_nop // special NOP to identity as PE/COFF executable 66 b primary_entry // branch to kernel start, magic 67 .quad 0 // Image load offset from start of RAM, little-endian 68 le64sym _kernel_size_le // Effective size of kernel image, little-endian 69 le64sym _kernel_flags_le // Informative flags, little-endian 70 .quad 0 // reserved 71 .quad 0 // reserved 72 .quad 0 // reserved 73 .ascii ARM64_IMAGE_MAGIC // Magic number 74 .long .Lpe_header_offset // Offset to the PE header. 75 76 __EFI_PE_HEADER 77 78 __INIT 79 80 /* 81 * The following callee saved general purpose registers are used on the 82 * primary lowlevel boot path: 83 * 84 * Register Scope Purpose 85 * x21 primary_entry() .. start_kernel() FDT pointer passed at boot in x0 86 * x23 primary_entry() .. start_kernel() physical misalignment/KASLR offset 87 * x28 clear_page_tables() callee preserved temp register 88 * x19/x20 __primary_switch() callee preserved temp registers 89 * x24 __primary_switch() .. relocate_kernel() current RELR displacement 90 * x28 create_idmap() callee preserved temp register 91 */ 92SYM_CODE_START(primary_entry) 93 bl preserve_boot_args 94 bl init_kernel_el // w0=cpu_boot_mode 95 adrp x23, __PHYS_OFFSET 96 and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 97 bl set_cpu_boot_mode_flag 98 bl clear_page_tables 99 bl create_idmap 100 bl create_kernel_mapping 101 102 /* 103 * The following calls CPU setup code, see arch/arm64/mm/proc.S for 104 * details. 105 * On return, the CPU will be ready for the MMU to be turned on and 106 * the TCR will have been set. 107 */ 108 bl __cpu_setup // initialise processor 109 b __primary_switch 110SYM_CODE_END(primary_entry) 111 112/* 113 * Preserve the arguments passed by the bootloader in x0 .. x3 114 */ 115SYM_CODE_START_LOCAL(preserve_boot_args) 116 mov x21, x0 // x21=FDT 117 118 adr_l x0, boot_args // record the contents of 119 stp x21, x1, [x0] // x0 .. x3 at kernel entry 120 stp x2, x3, [x0, #16] 121 122 dmb sy // needed before dc ivac with 123 // MMU off 124 125 add x1, x0, #0x20 // 4 x 8 bytes 126 b dcache_inval_poc // tail call 127SYM_CODE_END(preserve_boot_args) 128 129SYM_FUNC_START_LOCAL(clear_page_tables) 130 mov x28, lr 131 132 /* 133 * Invalidate the init page tables to avoid potential dirty cache lines 134 * being evicted. Other page tables are allocated in rodata as part of 135 * the kernel image, and thus are clean to the PoC per the boot 136 * protocol. 137 */ 138 adrp x0, init_pg_dir 139 adrp x1, init_pg_end 140 bl dcache_inval_poc 141 142 /* 143 * Clear the init page tables. 144 */ 145 adrp x0, init_pg_dir 146 adrp x1, init_pg_end 147 sub x1, x1, x0 1481: stp xzr, xzr, [x0], #16 149 stp xzr, xzr, [x0], #16 150 stp xzr, xzr, [x0], #16 151 stp xzr, xzr, [x0], #16 152 subs x1, x1, #64 153 b.ne 1b 154 155 ret x28 156SYM_FUNC_END(clear_page_tables) 157 158/* 159 * Macro to populate page table entries, these entries can be pointers to the next level 160 * or last level entries pointing to physical memory. 161 * 162 * tbl: page table address 163 * rtbl: pointer to page table or physical memory 164 * index: start index to write 165 * eindex: end index to write - [index, eindex] written to 166 * flags: flags for pagetable entry to or in 167 * inc: increment to rtbl between each entry 168 * tmp1: temporary variable 169 * 170 * Preserves: tbl, eindex, flags, inc 171 * Corrupts: index, tmp1 172 * Returns: rtbl 173 */ 174 .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1 175.Lpe\@: phys_to_pte \tmp1, \rtbl 176 orr \tmp1, \tmp1, \flags // tmp1 = table entry 177 str \tmp1, [\tbl, \index, lsl #3] 178 add \rtbl, \rtbl, \inc // rtbl = pa next level 179 add \index, \index, #1 180 cmp \index, \eindex 181 b.ls .Lpe\@ 182 .endm 183 184/* 185 * Compute indices of table entries from virtual address range. If multiple entries 186 * were needed in the previous page table level then the next page table level is assumed 187 * to be composed of multiple pages. (This effectively scales the end index). 188 * 189 * vstart: virtual address of start of range 190 * vend: virtual address of end of range - we map [vstart, vend] 191 * shift: shift used to transform virtual address into index 192 * order: #imm 2log(number of entries in page table) 193 * istart: index in table corresponding to vstart 194 * iend: index in table corresponding to vend 195 * count: On entry: how many extra entries were required in previous level, scales 196 * our end index. 197 * On exit: returns how many extra entries required for next page table level 198 * 199 * Preserves: vstart, vend 200 * Returns: istart, iend, count 201 */ 202 .macro compute_indices, vstart, vend, shift, order, istart, iend, count 203 ubfx \istart, \vstart, \shift, \order 204 ubfx \iend, \vend, \shift, \order 205 add \iend, \iend, \count, lsl \order 206 sub \count, \iend, \istart 207 .endm 208 209/* 210 * Map memory for specified virtual address range. Each level of page table needed supports 211 * multiple entries. If a level requires n entries the next page table level is assumed to be 212 * formed from n pages. 213 * 214 * tbl: location of page table 215 * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE) 216 * vstart: virtual address of start of range 217 * vend: virtual address of end of range - we map [vstart, vend - 1] 218 * flags: flags to use to map last level entries 219 * phys: physical address corresponding to vstart - physical memory is contiguous 220 * order: #imm 2log(number of entries in PGD table) 221 * 222 * If extra_shift is set, an extra level will be populated if the end address does 223 * not fit in 'extra_shift' bits. This assumes vend is in the TTBR0 range. 224 * 225 * Temporaries: istart, iend, tmp, count, sv - these need to be different registers 226 * Preserves: vstart, flags 227 * Corrupts: tbl, rtbl, vend, istart, iend, tmp, count, sv 228 */ 229 .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, order, istart, iend, tmp, count, sv, extra_shift 230 sub \vend, \vend, #1 231 add \rtbl, \tbl, #PAGE_SIZE 232 mov \count, #0 233 234 .ifnb \extra_shift 235 tst \vend, #~((1 << (\extra_shift)) - 1) 236 b.eq .L_\@ 237 compute_indices \vstart, \vend, #\extra_shift, #(PAGE_SHIFT - 3), \istart, \iend, \count 238 mov \sv, \rtbl 239 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 240 mov \tbl, \sv 241 .endif 242.L_\@: 243 compute_indices \vstart, \vend, #PGDIR_SHIFT, #\order, \istart, \iend, \count 244 mov \sv, \rtbl 245 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 246 mov \tbl, \sv 247 248#if SWAPPER_PGTABLE_LEVELS > 3 249 compute_indices \vstart, \vend, #PUD_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count 250 mov \sv, \rtbl 251 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 252 mov \tbl, \sv 253#endif 254 255#if SWAPPER_PGTABLE_LEVELS > 2 256 compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count 257 mov \sv, \rtbl 258 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 259 mov \tbl, \sv 260#endif 261 262 compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count 263 bic \rtbl, \phys, #SWAPPER_BLOCK_SIZE - 1 264 populate_entries \tbl, \rtbl, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp 265 .endm 266 267/* 268 * Remap a subregion created with the map_memory macro with modified attributes 269 * or output address. The entire remapped region must have been covered in the 270 * invocation of map_memory. 271 * 272 * x0: last level table address (returned in first argument to map_memory) 273 * x1: start VA of the existing mapping 274 * x2: start VA of the region to update 275 * x3: end VA of the region to update (exclusive) 276 * x4: start PA associated with the region to update 277 * x5: attributes to set on the updated region 278 * x6: order of the last level mappings 279 */ 280SYM_FUNC_START_LOCAL(remap_region) 281 sub x3, x3, #1 // make end inclusive 282 283 // Get the index offset for the start of the last level table 284 lsr x1, x1, x6 285 bfi x1, xzr, #0, #PAGE_SHIFT - 3 286 287 // Derive the start and end indexes into the last level table 288 // associated with the provided region 289 lsr x2, x2, x6 290 lsr x3, x3, x6 291 sub x2, x2, x1 292 sub x3, x3, x1 293 294 mov x1, #1 295 lsl x6, x1, x6 // block size at this level 296 297 populate_entries x0, x4, x2, x3, x5, x6, x7 298 ret 299SYM_FUNC_END(remap_region) 300 301SYM_FUNC_START_LOCAL(create_idmap) 302 mov x28, lr 303 /* 304 * The ID map carries a 1:1 mapping of the physical address range 305 * covered by the loaded image, which could be anywhere in DRAM. This 306 * means that the required size of the VA (== PA) space is decided at 307 * boot time, and could be more than the configured size of the VA 308 * space for ordinary kernel and user space mappings. 309 * 310 * There are three cases to consider here: 311 * - 39 <= VA_BITS < 48, and the ID map needs up to 48 VA bits to cover 312 * the placement of the image. In this case, we configure one extra 313 * level of translation on the fly for the ID map only. (This case 314 * also covers 42-bit VA/52-bit PA on 64k pages). 315 * 316 * - VA_BITS == 48, and the ID map needs more than 48 VA bits. This can 317 * only happen when using 64k pages, in which case we need to extend 318 * the root level table rather than add a level. Note that we can 319 * treat this case as 'always extended' as long as we take care not 320 * to program an unsupported T0SZ value into the TCR register. 321 * 322 * - Combinations that would require two additional levels of 323 * translation are not supported, e.g., VA_BITS==36 on 16k pages, or 324 * VA_BITS==39/4k pages with 5-level paging, where the input address 325 * requires more than 47 or 48 bits, respectively. 326 */ 327#if (VA_BITS < 48) 328#define IDMAP_PGD_ORDER (VA_BITS - PGDIR_SHIFT) 329#define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) 330 331 /* 332 * If VA_BITS < 48, we have to configure an additional table level. 333 * First, we have to verify our assumption that the current value of 334 * VA_BITS was chosen such that all translation levels are fully 335 * utilised, and that lowering T0SZ will always result in an additional 336 * translation level to be configured. 337 */ 338#if VA_BITS != EXTRA_SHIFT 339#error "Mismatch between VA_BITS and page size/number of translation levels" 340#endif 341#else 342#define IDMAP_PGD_ORDER (PHYS_MASK_SHIFT - PGDIR_SHIFT) 343#define EXTRA_SHIFT 344 /* 345 * If VA_BITS == 48, we don't have to configure an additional 346 * translation level, but the top-level table has more entries. 347 */ 348#endif 349 adrp x0, init_idmap_pg_dir 350 adrp x3, _text 351 adrp x6, _end 352 mov x7, SWAPPER_RX_MMUFLAGS 353 354 map_memory x0, x1, x3, x6, x7, x3, IDMAP_PGD_ORDER, x10, x11, x12, x13, x14, EXTRA_SHIFT 355 356 /* Remap the kernel page tables r/w in the ID map */ 357 adrp x1, _text 358 adrp x2, init_pg_dir 359 adrp x3, init_pg_end 360 bic x4, x2, #SWAPPER_BLOCK_SIZE - 1 361 mov x5, SWAPPER_RW_MMUFLAGS 362 mov x6, #SWAPPER_BLOCK_SHIFT 363 bl remap_region 364 365 /* 366 * Since the page tables have been populated with non-cacheable 367 * accesses (MMU disabled), invalidate those tables again to 368 * remove any speculatively loaded cache lines. 369 */ 370 dmb sy 371 372 adrp x0, init_idmap_pg_dir 373 adrp x1, init_idmap_pg_end 374 bl dcache_inval_poc 375 ret x28 376SYM_FUNC_END(create_idmap) 377 378SYM_FUNC_START_LOCAL(create_kernel_mapping) 379 adrp x0, init_pg_dir 380 mov_q x5, KIMAGE_VADDR // compile time __va(_text) 381 add x5, x5, x23 // add KASLR displacement 382 adrp x6, _end // runtime __pa(_end) 383 adrp x3, _text // runtime __pa(_text) 384 sub x6, x6, x3 // _end - _text 385 add x6, x6, x5 // runtime __va(_end) 386 mov x7, SWAPPER_RW_MMUFLAGS 387 388 map_memory x0, x1, x5, x6, x7, x3, (VA_BITS - PGDIR_SHIFT), x10, x11, x12, x13, x14 389 390 /* 391 * Since the page tables have been populated with non-cacheable 392 * accesses (MMU disabled), invalidate those tables again to 393 * remove any speculatively loaded cache lines. 394 */ 395 dmb sy 396 397 adrp x0, init_pg_dir 398 adrp x1, init_pg_end 399 b dcache_inval_poc // tail call 400SYM_FUNC_END(create_kernel_mapping) 401 402 /* 403 * Initialize CPU registers with task-specific and cpu-specific context. 404 * 405 * Create a final frame record at task_pt_regs(current)->stackframe, so 406 * that the unwinder can identify the final frame record of any task by 407 * its location in the task stack. We reserve the entire pt_regs space 408 * for consistency with user tasks and kthreads. 409 */ 410 .macro init_cpu_task tsk, tmp1, tmp2 411 msr sp_el0, \tsk 412 413 ldr \tmp1, [\tsk, #TSK_STACK] 414 add sp, \tmp1, #THREAD_SIZE 415 sub sp, sp, #PT_REGS_SIZE 416 417 stp xzr, xzr, [sp, #S_STACKFRAME] 418 add x29, sp, #S_STACKFRAME 419 420 scs_load \tsk 421 422 adr_l \tmp1, __per_cpu_offset 423 ldr w\tmp2, [\tsk, #TSK_TI_CPU] 424 ldr \tmp1, [\tmp1, \tmp2, lsl #3] 425 set_this_cpu_offset \tmp1 426 .endm 427 428/* 429 * The following fragment of code is executed with the MMU enabled. 430 * 431 * x0 = __PHYS_OFFSET 432 */ 433SYM_FUNC_START_LOCAL(__primary_switched) 434 adr_l x4, init_task 435 init_cpu_task x4, x5, x6 436 437 adr_l x8, vectors // load VBAR_EL1 with virtual 438 msr vbar_el1, x8 // vector table address 439 isb 440 441 stp x29, x30, [sp, #-16]! 442 mov x29, sp 443 444 str_l x21, __fdt_pointer, x5 // Save FDT pointer 445 446 ldr_l x4, kimage_vaddr // Save the offset between 447 sub x4, x4, x0 // the kernel virtual and 448 str_l x4, kimage_voffset, x5 // physical mappings 449 450 // Clear BSS 451 adr_l x0, __bss_start 452 mov x1, xzr 453 adr_l x2, __bss_stop 454 sub x2, x2, x0 455 bl __pi_memset 456 dsb ishst // Make zero page visible to PTW 457 458#if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS) 459 bl kasan_early_init 460#endif 461 mov x0, x21 // pass FDT address in x0 462 bl early_fdt_map // Try mapping the FDT early 463 bl init_feature_override // Parse cpu feature overrides 464#ifdef CONFIG_RANDOMIZE_BASE 465 tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized? 466 b.ne 0f 467 bl kaslr_early_init // parse FDT for KASLR options 468 cbz x0, 0f // KASLR disabled? just proceed 469 orr x23, x23, x0 // record KASLR offset 470 ldp x29, x30, [sp], #16 // we must enable KASLR, return 471 ret // to __primary_switch() 4720: 473#endif 474 bl switch_to_vhe // Prefer VHE if possible 475 ldp x29, x30, [sp], #16 476 bl start_kernel 477 ASM_BUG() 478SYM_FUNC_END(__primary_switched) 479 480/* 481 * end early head section, begin head code that is also used for 482 * hotplug and needs to have the same protections as the text region 483 */ 484 .section ".idmap.text","awx" 485 486/* 487 * Starting from EL2 or EL1, configure the CPU to execute at the highest 488 * reachable EL supported by the kernel in a chosen default state. If dropping 489 * from EL2 to EL1, configure EL2 before configuring EL1. 490 * 491 * Since we cannot always rely on ERET synchronizing writes to sysregs (e.g. if 492 * SCTLR_ELx.EOS is clear), we place an ISB prior to ERET. 493 * 494 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if 495 * booted in EL1 or EL2 respectively. 496 */ 497SYM_FUNC_START(init_kernel_el) 498 mrs x0, CurrentEL 499 cmp x0, #CurrentEL_EL2 500 b.eq init_el2 501 502SYM_INNER_LABEL(init_el1, SYM_L_LOCAL) 503 mov_q x0, INIT_SCTLR_EL1_MMU_OFF 504 msr sctlr_el1, x0 505 isb 506 mov_q x0, INIT_PSTATE_EL1 507 msr spsr_el1, x0 508 msr elr_el1, lr 509 mov w0, #BOOT_CPU_MODE_EL1 510 eret 511 512SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) 513 mov_q x0, HCR_HOST_NVHE_FLAGS 514 msr hcr_el2, x0 515 isb 516 517 init_el2_state 518 519 /* Hypervisor stub */ 520 adr_l x0, __hyp_stub_vectors 521 msr vbar_el2, x0 522 isb 523 524 /* 525 * Fruity CPUs seem to have HCR_EL2.E2H set to RES1, 526 * making it impossible to start in nVHE mode. Is that 527 * compliant with the architecture? Absolutely not! 528 */ 529 mrs x0, hcr_el2 530 and x0, x0, #HCR_E2H 531 cbz x0, 1f 532 533 /* Switching to VHE requires a sane SCTLR_EL1 as a start */ 534 mov_q x0, INIT_SCTLR_EL1_MMU_OFF 535 msr_s SYS_SCTLR_EL12, x0 536 537 /* 538 * Force an eret into a helper "function", and let it return 539 * to our original caller... This makes sure that we have 540 * initialised the basic PSTATE state. 541 */ 542 mov x0, #INIT_PSTATE_EL2 543 msr spsr_el1, x0 544 adr x0, __cpu_stick_to_vhe 545 msr elr_el1, x0 546 eret 547 5481: 549 mov_q x0, INIT_SCTLR_EL1_MMU_OFF 550 msr sctlr_el1, x0 551 552 msr elr_el2, lr 553 mov w0, #BOOT_CPU_MODE_EL2 554 eret 555 556__cpu_stick_to_vhe: 557 mov x0, #HVC_VHE_RESTART 558 hvc #0 559 mov x0, #BOOT_CPU_MODE_EL2 560 ret 561SYM_FUNC_END(init_kernel_el) 562 563/* 564 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed 565 * in w0. See arch/arm64/include/asm/virt.h for more info. 566 */ 567SYM_FUNC_START_LOCAL(set_cpu_boot_mode_flag) 568 adr_l x1, __boot_cpu_mode 569 cmp w0, #BOOT_CPU_MODE_EL2 570 b.ne 1f 571 add x1, x1, #4 5721: str w0, [x1] // Save CPU boot mode 573 dmb sy 574 dc ivac, x1 // Invalidate potentially stale cache line 575 ret 576SYM_FUNC_END(set_cpu_boot_mode_flag) 577 578/* 579 * These values are written with the MMU off, but read with the MMU on. 580 * Writers will invalidate the corresponding address, discarding up to a 581 * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures 582 * sufficient alignment that the CWG doesn't overlap another section. 583 */ 584 .pushsection ".mmuoff.data.write", "aw" 585/* 586 * We need to find out the CPU boot mode long after boot, so we need to 587 * store it in a writable variable. 588 * 589 * This is not in .bss, because we set it sufficiently early that the boot-time 590 * zeroing of .bss would clobber it. 591 */ 592SYM_DATA_START(__boot_cpu_mode) 593 .long BOOT_CPU_MODE_EL2 594 .long BOOT_CPU_MODE_EL1 595SYM_DATA_END(__boot_cpu_mode) 596/* 597 * The booting CPU updates the failed status @__early_cpu_boot_status, 598 * with MMU turned off. 599 */ 600SYM_DATA_START(__early_cpu_boot_status) 601 .quad 0 602SYM_DATA_END(__early_cpu_boot_status) 603 604 .popsection 605 606 /* 607 * This provides a "holding pen" for platforms to hold all secondary 608 * cores are held until we're ready for them to initialise. 609 */ 610SYM_FUNC_START(secondary_holding_pen) 611 bl init_kernel_el // w0=cpu_boot_mode 612 bl set_cpu_boot_mode_flag 613 mrs x0, mpidr_el1 614 mov_q x1, MPIDR_HWID_BITMASK 615 and x0, x0, x1 616 adr_l x3, secondary_holding_pen_release 617pen: ldr x4, [x3] 618 cmp x4, x0 619 b.eq secondary_startup 620 wfe 621 b pen 622SYM_FUNC_END(secondary_holding_pen) 623 624 /* 625 * Secondary entry point that jumps straight into the kernel. Only to 626 * be used where CPUs are brought online dynamically by the kernel. 627 */ 628SYM_FUNC_START(secondary_entry) 629 bl init_kernel_el // w0=cpu_boot_mode 630 bl set_cpu_boot_mode_flag 631 b secondary_startup 632SYM_FUNC_END(secondary_entry) 633 634SYM_FUNC_START_LOCAL(secondary_startup) 635 /* 636 * Common entry point for secondary CPUs. 637 */ 638 bl switch_to_vhe 639 bl __cpu_secondary_check52bitva 640 bl __cpu_setup // initialise processor 641 adrp x1, swapper_pg_dir 642 adrp x2, idmap_pg_dir 643 bl __enable_mmu 644 ldr x8, =__secondary_switched 645 br x8 646SYM_FUNC_END(secondary_startup) 647 648SYM_FUNC_START_LOCAL(__secondary_switched) 649 adr_l x5, vectors 650 msr vbar_el1, x5 651 isb 652 653 adr_l x0, secondary_data 654 ldr x2, [x0, #CPU_BOOT_TASK] 655 cbz x2, __secondary_too_slow 656 657 init_cpu_task x2, x1, x3 658 659#ifdef CONFIG_ARM64_PTR_AUTH 660 ptrauth_keys_init_cpu x2, x3, x4, x5 661#endif 662 663 bl secondary_start_kernel 664 ASM_BUG() 665SYM_FUNC_END(__secondary_switched) 666 667SYM_FUNC_START_LOCAL(__secondary_too_slow) 668 wfe 669 wfi 670 b __secondary_too_slow 671SYM_FUNC_END(__secondary_too_slow) 672 673/* 674 * The booting CPU updates the failed status @__early_cpu_boot_status, 675 * with MMU turned off. 676 * 677 * update_early_cpu_boot_status tmp, status 678 * - Corrupts tmp1, tmp2 679 * - Writes 'status' to __early_cpu_boot_status and makes sure 680 * it is committed to memory. 681 */ 682 683 .macro update_early_cpu_boot_status status, tmp1, tmp2 684 mov \tmp2, #\status 685 adr_l \tmp1, __early_cpu_boot_status 686 str \tmp2, [\tmp1] 687 dmb sy 688 dc ivac, \tmp1 // Invalidate potentially stale cache line 689 .endm 690 691/* 692 * Enable the MMU. 693 * 694 * x0 = SCTLR_EL1 value for turning on the MMU. 695 * x1 = TTBR1_EL1 value 696 * x2 = ID map root table address 697 * 698 * Returns to the caller via x30/lr. This requires the caller to be covered 699 * by the .idmap.text section. 700 * 701 * Checks if the selected granule size is supported by the CPU. 702 * If it isn't, park the CPU 703 */ 704SYM_FUNC_START(__enable_mmu) 705 mrs x3, ID_AA64MMFR0_EL1 706 ubfx x3, x3, #ID_AA64MMFR0_TGRAN_SHIFT, 4 707 cmp x3, #ID_AA64MMFR0_TGRAN_SUPPORTED_MIN 708 b.lt __no_granule_support 709 cmp x3, #ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 710 b.gt __no_granule_support 711 update_early_cpu_boot_status 0, x3, x4 712 phys_to_ttbr x1, x1 713 phys_to_ttbr x2, x2 714 msr ttbr0_el1, x2 // load TTBR0 715 offset_ttbr1 x1, x3 716 msr ttbr1_el1, x1 // load TTBR1 717 isb 718 719 set_sctlr_el1 x0 720 721 ret 722SYM_FUNC_END(__enable_mmu) 723 724SYM_FUNC_START(__cpu_secondary_check52bitva) 725#if VA_BITS > 48 726 ldr_l x0, vabits_actual 727 cmp x0, #52 728 b.ne 2f 729 730 mrs_s x0, SYS_ID_AA64MMFR2_EL1 731 and x0, x0, #(0xf << ID_AA64MMFR2_LVA_SHIFT) 732 cbnz x0, 2f 733 734 update_early_cpu_boot_status \ 735 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_52_BIT_VA, x0, x1 7361: wfe 737 wfi 738 b 1b 739 740#endif 7412: ret 742SYM_FUNC_END(__cpu_secondary_check52bitva) 743 744SYM_FUNC_START_LOCAL(__no_granule_support) 745 /* Indicate that this CPU can't boot and is stuck in the kernel */ 746 update_early_cpu_boot_status \ 747 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_NO_GRAN, x1, x2 7481: 749 wfe 750 wfi 751 b 1b 752SYM_FUNC_END(__no_granule_support) 753 754#ifdef CONFIG_RELOCATABLE 755SYM_FUNC_START_LOCAL(__relocate_kernel) 756 /* 757 * Iterate over each entry in the relocation table, and apply the 758 * relocations in place. 759 */ 760 ldr w9, =__rela_offset // offset to reloc table 761 ldr w10, =__rela_size // size of reloc table 762 763 mov_q x11, KIMAGE_VADDR // default virtual offset 764 add x11, x11, x23 // actual virtual offset 765 add x9, x9, x11 // __va(.rela) 766 add x10, x9, x10 // __va(.rela) + sizeof(.rela) 767 7680: cmp x9, x10 769 b.hs 1f 770 ldp x12, x13, [x9], #24 771 ldr x14, [x9, #-8] 772 cmp w13, #R_AARCH64_RELATIVE 773 b.ne 0b 774 add x14, x14, x23 // relocate 775 str x14, [x12, x23] 776 b 0b 777 7781: 779#ifdef CONFIG_RELR 780 /* 781 * Apply RELR relocations. 782 * 783 * RELR is a compressed format for storing relative relocations. The 784 * encoded sequence of entries looks like: 785 * [ AAAAAAAA BBBBBBB1 BBBBBBB1 ... AAAAAAAA BBBBBB1 ... ] 786 * 787 * i.e. start with an address, followed by any number of bitmaps. The 788 * address entry encodes 1 relocation. The subsequent bitmap entries 789 * encode up to 63 relocations each, at subsequent offsets following 790 * the last address entry. 791 * 792 * The bitmap entries must have 1 in the least significant bit. The 793 * assumption here is that an address cannot have 1 in lsb. Odd 794 * addresses are not supported. Any odd addresses are stored in the RELA 795 * section, which is handled above. 796 * 797 * Excluding the least significant bit in the bitmap, each non-zero 798 * bit in the bitmap represents a relocation to be applied to 799 * a corresponding machine word that follows the base address 800 * word. The second least significant bit represents the machine 801 * word immediately following the initial address, and each bit 802 * that follows represents the next word, in linear order. As such, 803 * a single bitmap can encode up to 63 relocations in a 64-bit object. 804 * 805 * In this implementation we store the address of the next RELR table 806 * entry in x9, the address being relocated by the current address or 807 * bitmap entry in x13 and the address being relocated by the current 808 * bit in x14. 809 * 810 * Because addends are stored in place in the binary, RELR relocations 811 * cannot be applied idempotently. We use x24 to keep track of the 812 * currently applied displacement so that we can correctly relocate if 813 * __relocate_kernel is called twice with non-zero displacements (i.e. 814 * if there is both a physical misalignment and a KASLR displacement). 815 */ 816 ldr w9, =__relr_offset // offset to reloc table 817 ldr w10, =__relr_size // size of reloc table 818 add x9, x9, x11 // __va(.relr) 819 add x10, x9, x10 // __va(.relr) + sizeof(.relr) 820 821 sub x15, x23, x24 // delta from previous offset 822 cbz x15, 7f // nothing to do if unchanged 823 mov x24, x23 // save new offset 824 8252: cmp x9, x10 826 b.hs 7f 827 ldr x11, [x9], #8 828 tbnz x11, #0, 3f // branch to handle bitmaps 829 add x13, x11, x23 830 ldr x12, [x13] // relocate address entry 831 add x12, x12, x15 832 str x12, [x13], #8 // adjust to start of bitmap 833 b 2b 834 8353: mov x14, x13 8364: lsr x11, x11, #1 837 cbz x11, 6f 838 tbz x11, #0, 5f // skip bit if not set 839 ldr x12, [x14] // relocate bit 840 add x12, x12, x15 841 str x12, [x14] 842 8435: add x14, x14, #8 // move to next bit's address 844 b 4b 845 8466: /* 847 * Move to the next bitmap's address. 8 is the word size, and 63 is the 848 * number of significant bits in a bitmap entry. 849 */ 850 add x13, x13, #(8 * 63) 851 b 2b 852 8537: 854#endif 855 ret 856 857SYM_FUNC_END(__relocate_kernel) 858#endif 859 860SYM_FUNC_START_LOCAL(__primary_switch) 861#ifdef CONFIG_RANDOMIZE_BASE 862 mov x19, x0 // preserve new SCTLR_EL1 value 863 mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value 864#endif 865 866 adrp x1, init_pg_dir 867 adrp x2, init_idmap_pg_dir 868 bl __enable_mmu 869#ifdef CONFIG_RELOCATABLE 870#ifdef CONFIG_RELR 871 mov x24, #0 // no RELR displacement yet 872#endif 873 bl __relocate_kernel 874#ifdef CONFIG_RANDOMIZE_BASE 875 ldr x8, =__primary_switched 876 adrp x0, __PHYS_OFFSET 877 blr x8 878 879 /* 880 * If we return here, we have a KASLR displacement in x23 which we need 881 * to take into account by discarding the current kernel mapping and 882 * creating a new one. 883 */ 884 pre_disable_mmu_workaround 885 msr sctlr_el1, x20 // disable the MMU 886 isb 887 bl clear_page_tables 888 bl create_kernel_mapping // Recreate kernel mapping 889 890 tlbi vmalle1 // Remove any stale TLB entries 891 dsb nsh 892 isb 893 894 set_sctlr_el1 x19 // re-enable the MMU 895 896 bl __relocate_kernel 897#endif 898#endif 899 ldr x8, =__primary_switched 900 adrp x0, __PHYS_OFFSET 901 br x8 902SYM_FUNC_END(__primary_switch) 903