1*c9af7f31SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 25d425c18SSudeep Holla /* 35d425c18SSudeep Holla * ARM64 cacheinfo support 45d425c18SSudeep Holla * 55d425c18SSudeep Holla * Copyright (C) 2015 ARM Ltd. 65d425c18SSudeep Holla * All Rights Reserved 75d425c18SSudeep Holla */ 85d425c18SSudeep Holla 98571890eSJeremy Linton #include <linux/acpi.h> 105d425c18SSudeep Holla #include <linux/cacheinfo.h> 115d425c18SSudeep Holla #include <linux/of.h> 125d425c18SSudeep Holla 135d425c18SSudeep Holla #define MAX_CACHE_LEVEL 7 /* Max 7 level supported */ 145d425c18SSudeep Holla /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */ 155d425c18SSudeep Holla #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) 165d425c18SSudeep Holla #define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) 175d425c18SSudeep Holla #define CLIDR_CTYPE(clidr, level) \ 185d425c18SSudeep Holla (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) 195d425c18SSudeep Holla 205d425c18SSudeep Holla static inline enum cache_type get_cache_type(int level) 215d425c18SSudeep Holla { 225d425c18SSudeep Holla u64 clidr; 235d425c18SSudeep Holla 245d425c18SSudeep Holla if (level > MAX_CACHE_LEVEL) 255d425c18SSudeep Holla return CACHE_TYPE_NOCACHE; 26adf75899SMark Rutland clidr = read_sysreg(clidr_el1); 275d425c18SSudeep Holla return CLIDR_CTYPE(clidr, level); 285d425c18SSudeep Holla } 295d425c18SSudeep Holla 305d425c18SSudeep Holla static void ci_leaf_init(struct cacheinfo *this_leaf, 315d425c18SSudeep Holla enum cache_type type, unsigned int level) 325d425c18SSudeep Holla { 335d425c18SSudeep Holla this_leaf->level = level; 345d425c18SSudeep Holla this_leaf->type = type; 355d425c18SSudeep Holla } 365d425c18SSudeep Holla 375d425c18SSudeep Holla static int __init_cache_level(unsigned int cpu) 385d425c18SSudeep Holla { 398571890eSJeremy Linton unsigned int ctype, level, leaves, fw_level; 405d425c18SSudeep Holla struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); 415d425c18SSudeep Holla 425d425c18SSudeep Holla for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { 435d425c18SSudeep Holla ctype = get_cache_type(level); 445d425c18SSudeep Holla if (ctype == CACHE_TYPE_NOCACHE) { 455d425c18SSudeep Holla level--; 465d425c18SSudeep Holla break; 475d425c18SSudeep Holla } 485d425c18SSudeep Holla /* Separate instruction and data caches */ 495d425c18SSudeep Holla leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1; 505d425c18SSudeep Holla } 515d425c18SSudeep Holla 528571890eSJeremy Linton if (acpi_disabled) 538571890eSJeremy Linton fw_level = of_find_last_cache_level(cpu); 548571890eSJeremy Linton else 558571890eSJeremy Linton fw_level = acpi_find_last_cache_level(cpu); 568571890eSJeremy Linton 578571890eSJeremy Linton if (level < fw_level) { 589a802431SSudeep Holla /* 599a802431SSudeep Holla * some external caches not specified in CLIDR_EL1 609a802431SSudeep Holla * the information may be available in the device tree 619a802431SSudeep Holla * only unified external caches are considered here 629a802431SSudeep Holla */ 638571890eSJeremy Linton leaves += (fw_level - level); 648571890eSJeremy Linton level = fw_level; 659a802431SSudeep Holla } 669a802431SSudeep Holla 675d425c18SSudeep Holla this_cpu_ci->num_levels = level; 685d425c18SSudeep Holla this_cpu_ci->num_leaves = leaves; 695d425c18SSudeep Holla return 0; 705d425c18SSudeep Holla } 715d425c18SSudeep Holla 725d425c18SSudeep Holla static int __populate_cache_leaves(unsigned int cpu) 735d425c18SSudeep Holla { 745d425c18SSudeep Holla unsigned int level, idx; 755d425c18SSudeep Holla enum cache_type type; 765d425c18SSudeep Holla struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); 775d425c18SSudeep Holla struct cacheinfo *this_leaf = this_cpu_ci->info_list; 785d425c18SSudeep Holla 795d425c18SSudeep Holla for (idx = 0, level = 1; level <= this_cpu_ci->num_levels && 805d425c18SSudeep Holla idx < this_cpu_ci->num_leaves; idx++, level++) { 815d425c18SSudeep Holla type = get_cache_type(level); 825d425c18SSudeep Holla if (type == CACHE_TYPE_SEPARATE) { 835d425c18SSudeep Holla ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); 845d425c18SSudeep Holla ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); 855d425c18SSudeep Holla } else { 865d425c18SSudeep Holla ci_leaf_init(this_leaf++, type, level); 875d425c18SSudeep Holla } 885d425c18SSudeep Holla } 895d425c18SSudeep Holla return 0; 905d425c18SSudeep Holla } 915d425c18SSudeep Holla 925d425c18SSudeep Holla DEFINE_SMP_CALL_CACHE_FUNCTION(init_cache_level) 935d425c18SSudeep Holla DEFINE_SMP_CALL_CACHE_FUNCTION(populate_cache_leaves) 94