15d425c18SSudeep Holla /* 25d425c18SSudeep Holla * ARM64 cacheinfo support 35d425c18SSudeep Holla * 45d425c18SSudeep Holla * Copyright (C) 2015 ARM Ltd. 55d425c18SSudeep Holla * All Rights Reserved 65d425c18SSudeep Holla * 75d425c18SSudeep Holla * This program is free software; you can redistribute it and/or modify 85d425c18SSudeep Holla * it under the terms of the GNU General Public License version 2 as 95d425c18SSudeep Holla * published by the Free Software Foundation. 105d425c18SSudeep Holla * 115d425c18SSudeep Holla * This program is distributed "as is" WITHOUT ANY WARRANTY of any 125d425c18SSudeep Holla * kind, whether express or implied; without even the implied warranty 135d425c18SSudeep Holla * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 145d425c18SSudeep Holla * GNU General Public License for more details. 155d425c18SSudeep Holla * 165d425c18SSudeep Holla * You should have received a copy of the GNU General Public License 175d425c18SSudeep Holla * along with this program. If not, see <http://www.gnu.org/licenses/>. 185d425c18SSudeep Holla */ 195d425c18SSudeep Holla 20*8571890eSJeremy Linton #include <linux/acpi.h> 215d425c18SSudeep Holla #include <linux/cacheinfo.h> 225d425c18SSudeep Holla #include <linux/of.h> 235d425c18SSudeep Holla 245d425c18SSudeep Holla #define MAX_CACHE_LEVEL 7 /* Max 7 level supported */ 255d425c18SSudeep Holla /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */ 265d425c18SSudeep Holla #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) 275d425c18SSudeep Holla #define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) 285d425c18SSudeep Holla #define CLIDR_CTYPE(clidr, level) \ 295d425c18SSudeep Holla (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) 305d425c18SSudeep Holla 315d425c18SSudeep Holla static inline enum cache_type get_cache_type(int level) 325d425c18SSudeep Holla { 335d425c18SSudeep Holla u64 clidr; 345d425c18SSudeep Holla 355d425c18SSudeep Holla if (level > MAX_CACHE_LEVEL) 365d425c18SSudeep Holla return CACHE_TYPE_NOCACHE; 37adf75899SMark Rutland clidr = read_sysreg(clidr_el1); 385d425c18SSudeep Holla return CLIDR_CTYPE(clidr, level); 395d425c18SSudeep Holla } 405d425c18SSudeep Holla 415d425c18SSudeep Holla static void ci_leaf_init(struct cacheinfo *this_leaf, 425d425c18SSudeep Holla enum cache_type type, unsigned int level) 435d425c18SSudeep Holla { 445d425c18SSudeep Holla this_leaf->level = level; 455d425c18SSudeep Holla this_leaf->type = type; 465d425c18SSudeep Holla } 475d425c18SSudeep Holla 485d425c18SSudeep Holla static int __init_cache_level(unsigned int cpu) 495d425c18SSudeep Holla { 50*8571890eSJeremy Linton unsigned int ctype, level, leaves, fw_level; 515d425c18SSudeep Holla struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); 525d425c18SSudeep Holla 535d425c18SSudeep Holla for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { 545d425c18SSudeep Holla ctype = get_cache_type(level); 555d425c18SSudeep Holla if (ctype == CACHE_TYPE_NOCACHE) { 565d425c18SSudeep Holla level--; 575d425c18SSudeep Holla break; 585d425c18SSudeep Holla } 595d425c18SSudeep Holla /* Separate instruction and data caches */ 605d425c18SSudeep Holla leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1; 615d425c18SSudeep Holla } 625d425c18SSudeep Holla 63*8571890eSJeremy Linton if (acpi_disabled) 64*8571890eSJeremy Linton fw_level = of_find_last_cache_level(cpu); 65*8571890eSJeremy Linton else 66*8571890eSJeremy Linton fw_level = acpi_find_last_cache_level(cpu); 67*8571890eSJeremy Linton 68*8571890eSJeremy Linton if (level < fw_level) { 699a802431SSudeep Holla /* 709a802431SSudeep Holla * some external caches not specified in CLIDR_EL1 719a802431SSudeep Holla * the information may be available in the device tree 729a802431SSudeep Holla * only unified external caches are considered here 739a802431SSudeep Holla */ 74*8571890eSJeremy Linton leaves += (fw_level - level); 75*8571890eSJeremy Linton level = fw_level; 769a802431SSudeep Holla } 779a802431SSudeep Holla 785d425c18SSudeep Holla this_cpu_ci->num_levels = level; 795d425c18SSudeep Holla this_cpu_ci->num_leaves = leaves; 805d425c18SSudeep Holla return 0; 815d425c18SSudeep Holla } 825d425c18SSudeep Holla 835d425c18SSudeep Holla static int __populate_cache_leaves(unsigned int cpu) 845d425c18SSudeep Holla { 855d425c18SSudeep Holla unsigned int level, idx; 865d425c18SSudeep Holla enum cache_type type; 875d425c18SSudeep Holla struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); 885d425c18SSudeep Holla struct cacheinfo *this_leaf = this_cpu_ci->info_list; 895d425c18SSudeep Holla 905d425c18SSudeep Holla for (idx = 0, level = 1; level <= this_cpu_ci->num_levels && 915d425c18SSudeep Holla idx < this_cpu_ci->num_leaves; idx++, level++) { 925d425c18SSudeep Holla type = get_cache_type(level); 935d425c18SSudeep Holla if (type == CACHE_TYPE_SEPARATE) { 945d425c18SSudeep Holla ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); 955d425c18SSudeep Holla ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); 965d425c18SSudeep Holla } else { 975d425c18SSudeep Holla ci_leaf_init(this_leaf++, type, level); 985d425c18SSudeep Holla } 995d425c18SSudeep Holla } 1005d425c18SSudeep Holla return 0; 1015d425c18SSudeep Holla } 1025d425c18SSudeep Holla 1035d425c18SSudeep Holla DEFINE_SMP_CALL_CACHE_FUNCTION(init_cache_level) 1045d425c18SSudeep Holla DEFINE_SMP_CALL_CACHE_FUNCTION(populate_cache_leaves) 105