1*08e875c1SCatalin Marinas /* 2*08e875c1SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 3*08e875c1SCatalin Marinas * 4*08e875c1SCatalin Marinas * This program is free software; you can redistribute it and/or modify 5*08e875c1SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 6*08e875c1SCatalin Marinas * published by the Free Software Foundation. 7*08e875c1SCatalin Marinas * 8*08e875c1SCatalin Marinas * This program is distributed in the hope that it will be useful, 9*08e875c1SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 10*08e875c1SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11*08e875c1SCatalin Marinas * GNU General Public License for more details. 12*08e875c1SCatalin Marinas * 13*08e875c1SCatalin Marinas * You should have received a copy of the GNU General Public License 14*08e875c1SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 15*08e875c1SCatalin Marinas */ 16*08e875c1SCatalin Marinas #ifndef __ASM_SMP_H 17*08e875c1SCatalin Marinas #define __ASM_SMP_H 18*08e875c1SCatalin Marinas 19*08e875c1SCatalin Marinas #include <linux/threads.h> 20*08e875c1SCatalin Marinas #include <linux/cpumask.h> 21*08e875c1SCatalin Marinas #include <linux/thread_info.h> 22*08e875c1SCatalin Marinas 23*08e875c1SCatalin Marinas #ifndef CONFIG_SMP 24*08e875c1SCatalin Marinas # error "<asm/smp.h> included in non-SMP build" 25*08e875c1SCatalin Marinas #endif 26*08e875c1SCatalin Marinas 27*08e875c1SCatalin Marinas #define raw_smp_processor_id() (current_thread_info()->cpu) 28*08e875c1SCatalin Marinas 29*08e875c1SCatalin Marinas struct seq_file; 30*08e875c1SCatalin Marinas 31*08e875c1SCatalin Marinas /* 32*08e875c1SCatalin Marinas * generate IPI list text 33*08e875c1SCatalin Marinas */ 34*08e875c1SCatalin Marinas extern void show_ipi_list(struct seq_file *p, int prec); 35*08e875c1SCatalin Marinas 36*08e875c1SCatalin Marinas /* 37*08e875c1SCatalin Marinas * Called from C code, this handles an IPI. 38*08e875c1SCatalin Marinas */ 39*08e875c1SCatalin Marinas extern void handle_IPI(int ipinr, struct pt_regs *regs); 40*08e875c1SCatalin Marinas 41*08e875c1SCatalin Marinas /* 42*08e875c1SCatalin Marinas * Setup the set of possible CPUs (via set_cpu_possible) 43*08e875c1SCatalin Marinas */ 44*08e875c1SCatalin Marinas extern void smp_init_cpus(void); 45*08e875c1SCatalin Marinas 46*08e875c1SCatalin Marinas /* 47*08e875c1SCatalin Marinas * Provide a function to raise an IPI cross call on CPUs in callmap. 48*08e875c1SCatalin Marinas */ 49*08e875c1SCatalin Marinas extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int)); 50*08e875c1SCatalin Marinas 51*08e875c1SCatalin Marinas /* 52*08e875c1SCatalin Marinas * Called from the secondary holding pen, this is the secondary CPU entry point. 53*08e875c1SCatalin Marinas */ 54*08e875c1SCatalin Marinas asmlinkage void secondary_start_kernel(void); 55*08e875c1SCatalin Marinas 56*08e875c1SCatalin Marinas /* 57*08e875c1SCatalin Marinas * Initial data for bringing up a secondary CPU. 58*08e875c1SCatalin Marinas */ 59*08e875c1SCatalin Marinas struct secondary_data { 60*08e875c1SCatalin Marinas void *stack; 61*08e875c1SCatalin Marinas }; 62*08e875c1SCatalin Marinas extern struct secondary_data secondary_data; 63*08e875c1SCatalin Marinas extern void secondary_holding_pen(void); 64*08e875c1SCatalin Marinas extern volatile unsigned long secondary_holding_pen_release; 65*08e875c1SCatalin Marinas 66*08e875c1SCatalin Marinas extern void arch_send_call_function_single_ipi(int cpu); 67*08e875c1SCatalin Marinas extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); 68*08e875c1SCatalin Marinas 69*08e875c1SCatalin Marinas #endif /* ifndef __ASM_SMP_H */ 70