xref: /openbmc/linux/arch/arm64/include/asm/mmu_context.h (revision 5aec715d7d3122f77cabaa7578d9d25a0c1ed20e)
1b3901d54SCatalin Marinas /*
2b3901d54SCatalin Marinas  * Based on arch/arm/include/asm/mmu_context.h
3b3901d54SCatalin Marinas  *
4b3901d54SCatalin Marinas  * Copyright (C) 1996 Russell King.
5b3901d54SCatalin Marinas  * Copyright (C) 2012 ARM Ltd.
6b3901d54SCatalin Marinas  *
7b3901d54SCatalin Marinas  * This program is free software; you can redistribute it and/or modify
8b3901d54SCatalin Marinas  * it under the terms of the GNU General Public License version 2 as
9b3901d54SCatalin Marinas  * published by the Free Software Foundation.
10b3901d54SCatalin Marinas  *
11b3901d54SCatalin Marinas  * This program is distributed in the hope that it will be useful,
12b3901d54SCatalin Marinas  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13b3901d54SCatalin Marinas  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14b3901d54SCatalin Marinas  * GNU General Public License for more details.
15b3901d54SCatalin Marinas  *
16b3901d54SCatalin Marinas  * You should have received a copy of the GNU General Public License
17b3901d54SCatalin Marinas  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
18b3901d54SCatalin Marinas  */
19b3901d54SCatalin Marinas #ifndef __ASM_MMU_CONTEXT_H
20b3901d54SCatalin Marinas #define __ASM_MMU_CONTEXT_H
21b3901d54SCatalin Marinas 
22b3901d54SCatalin Marinas #include <linux/compiler.h>
23b3901d54SCatalin Marinas #include <linux/sched.h>
24b3901d54SCatalin Marinas 
25b3901d54SCatalin Marinas #include <asm/cacheflush.h>
26b3901d54SCatalin Marinas #include <asm/proc-fns.h>
27b3901d54SCatalin Marinas #include <asm-generic/mm_hooks.h>
28b3901d54SCatalin Marinas #include <asm/cputype.h>
29b3901d54SCatalin Marinas #include <asm/pgtable.h>
30b3901d54SCatalin Marinas 
31ec45d1cfSWill Deacon #ifdef CONFIG_PID_IN_CONTEXTIDR
32ec45d1cfSWill Deacon static inline void contextidr_thread_switch(struct task_struct *next)
33ec45d1cfSWill Deacon {
34ec45d1cfSWill Deacon 	asm(
35ec45d1cfSWill Deacon 	"	msr	contextidr_el1, %0\n"
36ec45d1cfSWill Deacon 	"	isb"
37ec45d1cfSWill Deacon 	:
38ec45d1cfSWill Deacon 	: "r" (task_pid_nr(next)));
39ec45d1cfSWill Deacon }
40ec45d1cfSWill Deacon #else
41ec45d1cfSWill Deacon static inline void contextidr_thread_switch(struct task_struct *next)
42ec45d1cfSWill Deacon {
43ec45d1cfSWill Deacon }
44ec45d1cfSWill Deacon #endif
45ec45d1cfSWill Deacon 
46b3901d54SCatalin Marinas /*
47b3901d54SCatalin Marinas  * Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0.
48b3901d54SCatalin Marinas  */
49b3901d54SCatalin Marinas static inline void cpu_set_reserved_ttbr0(void)
50b3901d54SCatalin Marinas {
51b3901d54SCatalin Marinas 	unsigned long ttbr = page_to_phys(empty_zero_page);
52b3901d54SCatalin Marinas 
53b3901d54SCatalin Marinas 	asm(
54b3901d54SCatalin Marinas 	"	msr	ttbr0_el1, %0			// set TTBR0\n"
55b3901d54SCatalin Marinas 	"	isb"
56b3901d54SCatalin Marinas 	:
57b3901d54SCatalin Marinas 	: "r" (ttbr));
58b3901d54SCatalin Marinas }
59b3901d54SCatalin Marinas 
60dd006da2SArd Biesheuvel /*
61dd006da2SArd Biesheuvel  * TCR.T0SZ value to use when the ID map is active. Usually equals
62dd006da2SArd Biesheuvel  * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in
63dd006da2SArd Biesheuvel  * physical memory, in which case it will be smaller.
64dd006da2SArd Biesheuvel  */
65dd006da2SArd Biesheuvel extern u64 idmap_t0sz;
66dd006da2SArd Biesheuvel 
67dd006da2SArd Biesheuvel static inline bool __cpu_uses_extended_idmap(void)
68dd006da2SArd Biesheuvel {
69dd006da2SArd Biesheuvel 	return (!IS_ENABLED(CONFIG_ARM64_VA_BITS_48) &&
70dd006da2SArd Biesheuvel 		unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS)));
71dd006da2SArd Biesheuvel }
72dd006da2SArd Biesheuvel 
73c51e97d8SWill Deacon /*
74c51e97d8SWill Deacon  * Set TCR.T0SZ to its default value (based on VA_BITS)
75c51e97d8SWill Deacon  */
76c51e97d8SWill Deacon static inline void cpu_set_default_tcr_t0sz(void)
77dd006da2SArd Biesheuvel {
78dd006da2SArd Biesheuvel 	unsigned long tcr;
79dd006da2SArd Biesheuvel 
80c51e97d8SWill Deacon 	if (!__cpu_uses_extended_idmap())
81c51e97d8SWill Deacon 		return;
82c51e97d8SWill Deacon 
83dd006da2SArd Biesheuvel 	asm volatile (
84dd006da2SArd Biesheuvel 	"	mrs	%0, tcr_el1	;"
85dd006da2SArd Biesheuvel 	"	bfi	%0, %1, %2, %3	;"
86dd006da2SArd Biesheuvel 	"	msr	tcr_el1, %0	;"
87dd006da2SArd Biesheuvel 	"	isb"
88dd006da2SArd Biesheuvel 	: "=&r" (tcr)
89c51e97d8SWill Deacon 	: "r"(TCR_T0SZ(VA_BITS)), "I"(TCR_T0SZ_OFFSET), "I"(TCR_TxSZ_WIDTH));
90dd006da2SArd Biesheuvel }
91dd006da2SArd Biesheuvel 
92b3901d54SCatalin Marinas /*
93*5aec715dSWill Deacon  * It would be nice to return ASIDs back to the allocator, but unfortunately
94*5aec715dSWill Deacon  * that introduces a race with a generation rollover where we could erroneously
95*5aec715dSWill Deacon  * free an ASID allocated in a future generation. We could workaround this by
96*5aec715dSWill Deacon  * freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap),
97*5aec715dSWill Deacon  * but we'd then need to make sure that we didn't dirty any TLBs afterwards.
98*5aec715dSWill Deacon  * Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you
99*5aec715dSWill Deacon  * take CPU migration into account.
100b3901d54SCatalin Marinas  */
101b3901d54SCatalin Marinas #define destroy_context(mm)		do { } while(0)
102*5aec715dSWill Deacon void check_and_switch_context(struct mm_struct *mm, unsigned int cpu);
103b3901d54SCatalin Marinas 
104*5aec715dSWill Deacon #define init_new_context(tsk,mm)	({ atomic64_set(&mm->context.id, 0); 0; })
105b3901d54SCatalin Marinas 
106b3901d54SCatalin Marinas /*
107b3901d54SCatalin Marinas  * This is called when "tsk" is about to enter lazy TLB mode.
108b3901d54SCatalin Marinas  *
109b3901d54SCatalin Marinas  * mm:  describes the currently active mm context
110b3901d54SCatalin Marinas  * tsk: task which is entering lazy tlb
111b3901d54SCatalin Marinas  * cpu: cpu number which is entering lazy tlb
112b3901d54SCatalin Marinas  *
113b3901d54SCatalin Marinas  * tsk->mm will be NULL
114b3901d54SCatalin Marinas  */
115b3901d54SCatalin Marinas static inline void
116b3901d54SCatalin Marinas enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
117b3901d54SCatalin Marinas {
118b3901d54SCatalin Marinas }
119b3901d54SCatalin Marinas 
120b3901d54SCatalin Marinas /*
121b3901d54SCatalin Marinas  * This is the actual mm switch as far as the scheduler
122b3901d54SCatalin Marinas  * is concerned.  No registers are touched.  We avoid
123b3901d54SCatalin Marinas  * calling the CPU specific function when the mm hasn't
124b3901d54SCatalin Marinas  * actually changed.
125b3901d54SCatalin Marinas  */
126b3901d54SCatalin Marinas static inline void
127b3901d54SCatalin Marinas switch_mm(struct mm_struct *prev, struct mm_struct *next,
128b3901d54SCatalin Marinas 	  struct task_struct *tsk)
129b3901d54SCatalin Marinas {
130b3901d54SCatalin Marinas 	unsigned int cpu = smp_processor_id();
131b3901d54SCatalin Marinas 
132e53f21bcSCatalin Marinas 	/*
133e53f21bcSCatalin Marinas 	 * init_mm.pgd does not contain any user mappings and it is always
134e53f21bcSCatalin Marinas 	 * active for kernel addresses in TTBR1. Just set the reserved TTBR0.
135e53f21bcSCatalin Marinas 	 */
136e53f21bcSCatalin Marinas 	if (next == &init_mm) {
137e53f21bcSCatalin Marinas 		cpu_set_reserved_ttbr0();
138e53f21bcSCatalin Marinas 		return;
139e53f21bcSCatalin Marinas 	}
140e53f21bcSCatalin Marinas 
141b3901d54SCatalin Marinas 	if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next)
142b3901d54SCatalin Marinas 		check_and_switch_context(next, tsk);
143b3901d54SCatalin Marinas }
144b3901d54SCatalin Marinas 
145b3901d54SCatalin Marinas #define deactivate_mm(tsk,mm)	do { } while (0)
146b3901d54SCatalin Marinas #define activate_mm(prev,next)	switch_mm(prev, next, NULL)
147b3901d54SCatalin Marinas 
148b3901d54SCatalin Marinas #endif
149