xref: /openbmc/linux/arch/arm64/include/asm/mmu.h (revision 83504032e6ddcc8b0942aa24dfad5db849090c9f)
14f04d8f0SCatalin Marinas /*
24f04d8f0SCatalin Marinas  * Copyright (C) 2012 ARM Ltd.
34f04d8f0SCatalin Marinas  *
44f04d8f0SCatalin Marinas  * This program is free software; you can redistribute it and/or modify
54f04d8f0SCatalin Marinas  * it under the terms of the GNU General Public License version 2 as
64f04d8f0SCatalin Marinas  * published by the Free Software Foundation.
74f04d8f0SCatalin Marinas  *
84f04d8f0SCatalin Marinas  * This program is distributed in the hope that it will be useful,
94f04d8f0SCatalin Marinas  * but WITHOUT ANY WARRANTY; without even the implied warranty of
104f04d8f0SCatalin Marinas  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
114f04d8f0SCatalin Marinas  * GNU General Public License for more details.
124f04d8f0SCatalin Marinas  *
134f04d8f0SCatalin Marinas  * You should have received a copy of the GNU General Public License
144f04d8f0SCatalin Marinas  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
154f04d8f0SCatalin Marinas  */
164f04d8f0SCatalin Marinas #ifndef __ASM_MMU_H
174f04d8f0SCatalin Marinas #define __ASM_MMU_H
184f04d8f0SCatalin Marinas 
19b89d82efSWill Deacon #include <asm/cputype.h>
20b89d82efSWill Deacon 
215ce93ab6SYury Norov #define MMCF_AARCH32	0x1	/* mm context flag for AArch32 executables */
2279e9aa59SJames Morse #define USER_ASID_BIT	48
2379e9aa59SJames Morse #define USER_ASID_FLAG	(UL(1) << USER_ASID_BIT)
24b519538dSWill Deacon #define TTBR_ASID_MASK	(UL(0xffff) << 48)
255ce93ab6SYury Norov 
264205a89bSMarc Zyngier #define BP_HARDEN_EL2_SLOTS 4
274205a89bSMarc Zyngier 
28fc0e1299SWill Deacon #ifndef __ASSEMBLY__
29fc0e1299SWill Deacon 
304f04d8f0SCatalin Marinas typedef struct {
315aec715dSWill Deacon 	atomic64_t	id;
324f04d8f0SCatalin Marinas 	void		*vdso;
3306beb72fSPratyush Anand 	unsigned long	flags;
344f04d8f0SCatalin Marinas } mm_context_t;
354f04d8f0SCatalin Marinas 
365aec715dSWill Deacon /*
375aec715dSWill Deacon  * This macro is only used by the TLBI code, which cannot race with an
385aec715dSWill Deacon  * ASID change and therefore doesn't need to reload the counter using
395aec715dSWill Deacon  * atomic64_read.
405aec715dSWill Deacon  */
415aec715dSWill Deacon #define ASID(mm)	((mm)->context.id.counter & 0xffff)
424f04d8f0SCatalin Marinas 
43fc0e1299SWill Deacon static inline bool arm64_kernel_unmapped_at_el0(void)
44fc0e1299SWill Deacon {
45ea1e3de8SWill Deacon 	return IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0) &&
46ea1e3de8SWill Deacon 	       cpus_have_const_cap(ARM64_UNMAP_KERNEL_AT_EL0);
47fc0e1299SWill Deacon }
48fc0e1299SWill Deacon 
49b89d82efSWill Deacon static inline bool arm64_kernel_use_ng_mappings(void)
50b89d82efSWill Deacon {
51b89d82efSWill Deacon 	bool tx1_bug;
52b89d82efSWill Deacon 
53b89d82efSWill Deacon 	/* What's a kpti? Use global mappings if we don't know. */
54b89d82efSWill Deacon 	if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0))
55b89d82efSWill Deacon 		return false;
56b89d82efSWill Deacon 
57b89d82efSWill Deacon 	/*
58b89d82efSWill Deacon 	 * Note: this function is called before the CPU capabilities have
59b89d82efSWill Deacon 	 * been configured, so our early mappings will be global. If we
60b89d82efSWill Deacon 	 * later determine that kpti is required, then
61b89d82efSWill Deacon 	 * kpti_install_ng_mappings() will make them non-global.
62b89d82efSWill Deacon 	 */
632f979675SJames Morse 	if (arm64_kernel_unmapped_at_el0())
642f979675SJames Morse 		return true;
652f979675SJames Morse 
66b89d82efSWill Deacon 	if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
672f979675SJames Morse 		return false;
68b89d82efSWill Deacon 
69b89d82efSWill Deacon 	/*
70b89d82efSWill Deacon 	 * KASLR is enabled so we're going to be enabling kpti on non-broken
71b89d82efSWill Deacon 	 * CPUs regardless of their susceptibility to Meltdown. Rather
72b89d82efSWill Deacon 	 * than force everybody to go through the G -> nG dance later on,
73b89d82efSWill Deacon 	 * just put down non-global mappings from the beginning.
74b89d82efSWill Deacon 	 */
75b89d82efSWill Deacon 	if (!IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
76b89d82efSWill Deacon 		tx1_bug = false;
77b89d82efSWill Deacon #ifndef MODULE
78b89d82efSWill Deacon 	} else if (!static_branch_likely(&arm64_const_caps_ready)) {
79b89d82efSWill Deacon 		extern const struct midr_range cavium_erratum_27456_cpus[];
80b89d82efSWill Deacon 
81b89d82efSWill Deacon 		tx1_bug = is_midr_in_range_list(read_cpuid_id(),
82b89d82efSWill Deacon 						cavium_erratum_27456_cpus);
83b89d82efSWill Deacon #endif
84b89d82efSWill Deacon 	} else {
85b89d82efSWill Deacon 		tx1_bug = __cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456);
86b89d82efSWill Deacon 	}
87b89d82efSWill Deacon 
88b89d82efSWill Deacon 	return !tx1_bug && kaslr_offset() > 0;
89b89d82efSWill Deacon }
90b89d82efSWill Deacon 
910f15adbbSWill Deacon typedef void (*bp_hardening_cb_t)(void);
920f15adbbSWill Deacon 
930f15adbbSWill Deacon struct bp_hardening_data {
940f15adbbSWill Deacon 	int			hyp_vectors_slot;
950f15adbbSWill Deacon 	bp_hardening_cb_t	fn;
960f15adbbSWill Deacon };
970f15adbbSWill Deacon 
98dee39247SMarc Zyngier #if (defined(CONFIG_HARDEN_BRANCH_PREDICTOR) ||	\
99dee39247SMarc Zyngier      defined(CONFIG_HARDEN_EL2_VECTORS))
1000f15adbbSWill Deacon extern char __bp_harden_hyp_vecs_start[], __bp_harden_hyp_vecs_end[];
1014205a89bSMarc Zyngier extern atomic_t arm64_el2_vector_last_slot;
102dee39247SMarc Zyngier #endif  /* CONFIG_HARDEN_BRANCH_PREDICTOR || CONFIG_HARDEN_EL2_VECTORS */
1030f15adbbSWill Deacon 
104dee39247SMarc Zyngier #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
1050f15adbbSWill Deacon DECLARE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
1060f15adbbSWill Deacon 
1070f15adbbSWill Deacon static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void)
1080f15adbbSWill Deacon {
1090f15adbbSWill Deacon 	return this_cpu_ptr(&bp_hardening_data);
1100f15adbbSWill Deacon }
1110f15adbbSWill Deacon 
1120f15adbbSWill Deacon static inline void arm64_apply_bp_hardening(void)
1130f15adbbSWill Deacon {
1140f15adbbSWill Deacon 	struct bp_hardening_data *d;
1150f15adbbSWill Deacon 
1160f15adbbSWill Deacon 	if (!cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR))
1170f15adbbSWill Deacon 		return;
1180f15adbbSWill Deacon 
1190f15adbbSWill Deacon 	d = arm64_get_bp_hardening_data();
1200f15adbbSWill Deacon 	if (d->fn)
1210f15adbbSWill Deacon 		d->fn();
1220f15adbbSWill Deacon }
1230f15adbbSWill Deacon #else
1240f15adbbSWill Deacon static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void)
1250f15adbbSWill Deacon {
1260f15adbbSWill Deacon 	return NULL;
1270f15adbbSWill Deacon }
1280f15adbbSWill Deacon 
1290f15adbbSWill Deacon static inline void arm64_apply_bp_hardening(void)	{ }
1300f15adbbSWill Deacon #endif	/* CONFIG_HARDEN_BRANCH_PREDICTOR */
1310f15adbbSWill Deacon 
132*83504032SWill Deacon extern void arm64_memblock_init(void);
1334f04d8f0SCatalin Marinas extern void paging_init(void);
1343194ac6eSDavid Daney extern void bootmem_init(void);
1352475ff9dSCatalin Marinas extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt);
1360bf757c7SMark Salter extern void init_mem_pgprot(void);
1378ce837ceSArd Biesheuvel extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys,
1388ce837ceSArd Biesheuvel 			       unsigned long virt, phys_addr_t size,
139f14c66ceSArd Biesheuvel 			       pgprot_t prot, bool page_mappings_only);
14061bd93ceSArd Biesheuvel extern void *fixmap_remap_fdt(phys_addr_t dt_phys);
1415ea5306cSArd Biesheuvel extern void mark_linear_text_alias_ro(void);
1424f04d8f0SCatalin Marinas 
1432b5548b6SJun Yao #define INIT_MM_CONTEXT(name)	\
1442b5548b6SJun Yao 	.pgd = init_pg_dir,
1452b5548b6SJun Yao 
146fc0e1299SWill Deacon #endif	/* !__ASSEMBLY__ */
1474f04d8f0SCatalin Marinas #endif
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