1478fcb2cSWill Deacon /* 2478fcb2cSWill Deacon * Copyright (C) 2012 ARM Ltd. 3478fcb2cSWill Deacon * 4478fcb2cSWill Deacon * This program is free software; you can redistribute it and/or modify 5478fcb2cSWill Deacon * it under the terms of the GNU General Public License version 2 as 6478fcb2cSWill Deacon * published by the Free Software Foundation. 7478fcb2cSWill Deacon * 8478fcb2cSWill Deacon * This program is distributed in the hope that it will be useful, 9478fcb2cSWill Deacon * but WITHOUT ANY WARRANTY; without even the implied warranty of 10478fcb2cSWill Deacon * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11478fcb2cSWill Deacon * GNU General Public License for more details. 12478fcb2cSWill Deacon * 13478fcb2cSWill Deacon * You should have received a copy of the GNU General Public License 14478fcb2cSWill Deacon * along with this program. If not, see <http://www.gnu.org/licenses/>. 15478fcb2cSWill Deacon */ 16478fcb2cSWill Deacon #ifndef __ASM_DEBUG_MONITORS_H 17478fcb2cSWill Deacon #define __ASM_DEBUG_MONITORS_H 18478fcb2cSWill Deacon 19478fcb2cSWill Deacon #ifdef __KERNEL__ 20478fcb2cSWill Deacon 21*951757aeSDave P Martin #include <asm/insn.h> 22*951757aeSDave P Martin 2351ba2481SMarc Zyngier /* Low-level stepping controls. */ 2451ba2481SMarc Zyngier #define DBG_MDSCR_SS (1 << 0) 2551ba2481SMarc Zyngier #define DBG_SPSR_SS (1 << 21) 2651ba2481SMarc Zyngier 2751ba2481SMarc Zyngier /* MDSCR_EL1 enabling bits */ 2851ba2481SMarc Zyngier #define DBG_MDSCR_KDE (1 << 13) 2951ba2481SMarc Zyngier #define DBG_MDSCR_MDE (1 << 15) 3051ba2481SMarc Zyngier #define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE) 3151ba2481SMarc Zyngier 32478fcb2cSWill Deacon #define DBG_ESR_EVT(x) (((x) >> 27) & 0x7) 33478fcb2cSWill Deacon 34478fcb2cSWill Deacon /* AArch64 */ 35478fcb2cSWill Deacon #define DBG_ESR_EVT_HWBP 0x0 36478fcb2cSWill Deacon #define DBG_ESR_EVT_HWSS 0x1 37478fcb2cSWill Deacon #define DBG_ESR_EVT_HWWP 0x2 38478fcb2cSWill Deacon #define DBG_ESR_EVT_BRK 0x6 39478fcb2cSWill Deacon 40bcf5763bSVijaya Kumar K /* 41bcf5763bSVijaya Kumar K * Break point instruction encoding 42bcf5763bSVijaya Kumar K */ 43*951757aeSDave P Martin #define BREAK_INSTR_SIZE AARCH64_INSN_SIZE 44bcf5763bSVijaya Kumar K 45bcf5763bSVijaya Kumar K /* 46bcf5763bSVijaya Kumar K * ESR values expected for dynamic and compile time BRK instruction 47bcf5763bSVijaya Kumar K */ 48bcf5763bSVijaya Kumar K #define DBG_ESR_VAL_BRK(x) (0xf2000000 | ((x) & 0xfffff)) 49bcf5763bSVijaya Kumar K 50bcf5763bSVijaya Kumar K /* 51bcf5763bSVijaya Kumar K * #imm16 values used for BRK instruction generation 52bcf5763bSVijaya Kumar K * Allowed values for kgbd are 0x400 - 0x7ff 53a9ae04c9SMark Brown * 0x100: for triggering a fault on purpose (reserved) 54bcf5763bSVijaya Kumar K * 0x400: for dynamic BRK instruction 55bcf5763bSVijaya Kumar K * 0x401: for compile time BRK instruction 56bcf5763bSVijaya Kumar K */ 57a9ae04c9SMark Brown #define FAULT_BRK_IMM 0x100 587acf71d1SCatalin Marinas #define KGDB_DYN_DBG_BRK_IMM 0x400 597acf71d1SCatalin Marinas #define KGDB_COMPILED_DBG_BRK_IMM 0x401 60bcf5763bSVijaya Kumar K 61bcf5763bSVijaya Kumar K /* 62bcf5763bSVijaya Kumar K * BRK instruction encoding 63bcf5763bSVijaya Kumar K * The #imm16 value should be placed at bits[20:5] within BRK ins 64bcf5763bSVijaya Kumar K */ 65bcf5763bSVijaya Kumar K #define AARCH64_BREAK_MON 0xd4200000 66bcf5763bSVijaya Kumar K 67bcf5763bSVijaya Kumar K /* 68a9ae04c9SMark Brown * BRK instruction for provoking a fault on purpose 69a9ae04c9SMark Brown * Unlike kgdb, #imm16 value with unallocated handler is used for faulting. 70a9ae04c9SMark Brown */ 71a9ae04c9SMark Brown #define AARCH64_BREAK_FAULT (AARCH64_BREAK_MON | (FAULT_BRK_IMM << 5)) 72a9ae04c9SMark Brown 73a9ae04c9SMark Brown /* 74bcf5763bSVijaya Kumar K * Extract byte from BRK instruction 75bcf5763bSVijaya Kumar K */ 767acf71d1SCatalin Marinas #define KGDB_DYN_DBG_BRK_INS_BYTE(x) \ 77bcf5763bSVijaya Kumar K ((((AARCH64_BREAK_MON) & 0xffe0001f) >> (x * 8)) & 0xff) 78bcf5763bSVijaya Kumar K 79bcf5763bSVijaya Kumar K /* 80bcf5763bSVijaya Kumar K * Extract byte from BRK #imm16 81bcf5763bSVijaya Kumar K */ 827acf71d1SCatalin Marinas #define KGBD_DYN_DBG_BRK_IMM_BYTE(x) \ 837acf71d1SCatalin Marinas (((((KGDB_DYN_DBG_BRK_IMM) & 0xffff) << 5) >> (x * 8)) & 0xff) 84bcf5763bSVijaya Kumar K 857acf71d1SCatalin Marinas #define KGDB_DYN_DBG_BRK_BYTE(x) \ 867acf71d1SCatalin Marinas (KGDB_DYN_DBG_BRK_INS_BYTE(x) | KGBD_DYN_DBG_BRK_IMM_BYTE(x)) 87bcf5763bSVijaya Kumar K 887acf71d1SCatalin Marinas #define KGDB_DYN_BRK_INS_BYTE0 KGDB_DYN_DBG_BRK_BYTE(0) 897acf71d1SCatalin Marinas #define KGDB_DYN_BRK_INS_BYTE1 KGDB_DYN_DBG_BRK_BYTE(1) 907acf71d1SCatalin Marinas #define KGDB_DYN_BRK_INS_BYTE2 KGDB_DYN_DBG_BRK_BYTE(2) 917acf71d1SCatalin Marinas #define KGDB_DYN_BRK_INS_BYTE3 KGDB_DYN_DBG_BRK_BYTE(3) 92bcf5763bSVijaya Kumar K 93bcf5763bSVijaya Kumar K #define CACHE_FLUSH_IS_SAFE 1 94bcf5763bSVijaya Kumar K 95478fcb2cSWill Deacon /* AArch32 */ 96478fcb2cSWill Deacon #define DBG_ESR_EVT_BKPT 0x4 97478fcb2cSWill Deacon #define DBG_ESR_EVT_VECC 0x5 98478fcb2cSWill Deacon 99478fcb2cSWill Deacon #define AARCH32_BREAK_ARM 0x07f001f0 100478fcb2cSWill Deacon #define AARCH32_BREAK_THUMB 0xde01 101478fcb2cSWill Deacon #define AARCH32_BREAK_THUMB2_LO 0xf7f0 102478fcb2cSWill Deacon #define AARCH32_BREAK_THUMB2_HI 0xa000 103478fcb2cSWill Deacon 104478fcb2cSWill Deacon #ifndef __ASSEMBLY__ 105478fcb2cSWill Deacon struct task_struct; 106478fcb2cSWill Deacon 107478fcb2cSWill Deacon #define DBG_ARCH_ID_RESERVED 0 /* In case of ptrace ABI updates. */ 108478fcb2cSWill Deacon 109ee6214ceSSandeepa Prabhu #define DBG_HOOK_HANDLED 0 110ee6214ceSSandeepa Prabhu #define DBG_HOOK_ERROR 1 111ee6214ceSSandeepa Prabhu 112ee6214ceSSandeepa Prabhu struct step_hook { 113ee6214ceSSandeepa Prabhu struct list_head node; 114ee6214ceSSandeepa Prabhu int (*fn)(struct pt_regs *regs, unsigned int esr); 115ee6214ceSSandeepa Prabhu }; 116ee6214ceSSandeepa Prabhu 117ee6214ceSSandeepa Prabhu void register_step_hook(struct step_hook *hook); 118ee6214ceSSandeepa Prabhu void unregister_step_hook(struct step_hook *hook); 119ee6214ceSSandeepa Prabhu 120ee6214ceSSandeepa Prabhu struct break_hook { 121ee6214ceSSandeepa Prabhu struct list_head node; 122ee6214ceSSandeepa Prabhu u32 esr_val; 123ee6214ceSSandeepa Prabhu u32 esr_mask; 124ee6214ceSSandeepa Prabhu int (*fn)(struct pt_regs *regs, unsigned int esr); 125ee6214ceSSandeepa Prabhu }; 126ee6214ceSSandeepa Prabhu 127ee6214ceSSandeepa Prabhu void register_break_hook(struct break_hook *hook); 128ee6214ceSSandeepa Prabhu void unregister_break_hook(struct break_hook *hook); 129ee6214ceSSandeepa Prabhu 130478fcb2cSWill Deacon u8 debug_monitors_arch(void); 131478fcb2cSWill Deacon 13251ba2481SMarc Zyngier enum debug_el { 13351ba2481SMarc Zyngier DBG_ACTIVE_EL0 = 0, 13451ba2481SMarc Zyngier DBG_ACTIVE_EL1, 13551ba2481SMarc Zyngier }; 13651ba2481SMarc Zyngier 137478fcb2cSWill Deacon void enable_debug_monitors(enum debug_el el); 138478fcb2cSWill Deacon void disable_debug_monitors(enum debug_el el); 139478fcb2cSWill Deacon 140478fcb2cSWill Deacon void user_rewind_single_step(struct task_struct *task); 141478fcb2cSWill Deacon void user_fastforward_single_step(struct task_struct *task); 142478fcb2cSWill Deacon 143478fcb2cSWill Deacon void kernel_enable_single_step(struct pt_regs *regs); 144478fcb2cSWill Deacon void kernel_disable_single_step(void); 145478fcb2cSWill Deacon int kernel_active_single_step(void); 146478fcb2cSWill Deacon 147478fcb2cSWill Deacon #ifdef CONFIG_HAVE_HW_BREAKPOINT 148478fcb2cSWill Deacon int reinstall_suspended_bps(struct pt_regs *regs); 149478fcb2cSWill Deacon #else 150478fcb2cSWill Deacon static inline int reinstall_suspended_bps(struct pt_regs *regs) 151478fcb2cSWill Deacon { 152478fcb2cSWill Deacon return -ENODEV; 153478fcb2cSWill Deacon } 154478fcb2cSWill Deacon #endif 155478fcb2cSWill Deacon 1561442b6edSWill Deacon int aarch32_break_handler(struct pt_regs *regs); 1571442b6edSWill Deacon 158478fcb2cSWill Deacon #endif /* __ASSEMBLY */ 159478fcb2cSWill Deacon #endif /* __KERNEL__ */ 160478fcb2cSWill Deacon #endif /* __ASM_DEBUG_MONITORS_H */ 161