1478fcb2cSWill Deacon /* 2478fcb2cSWill Deacon * Copyright (C) 2012 ARM Ltd. 3478fcb2cSWill Deacon * 4478fcb2cSWill Deacon * This program is free software; you can redistribute it and/or modify 5478fcb2cSWill Deacon * it under the terms of the GNU General Public License version 2 as 6478fcb2cSWill Deacon * published by the Free Software Foundation. 7478fcb2cSWill Deacon * 8478fcb2cSWill Deacon * This program is distributed in the hope that it will be useful, 9478fcb2cSWill Deacon * but WITHOUT ANY WARRANTY; without even the implied warranty of 10478fcb2cSWill Deacon * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11478fcb2cSWill Deacon * GNU General Public License for more details. 12478fcb2cSWill Deacon * 13478fcb2cSWill Deacon * You should have received a copy of the GNU General Public License 14478fcb2cSWill Deacon * along with this program. If not, see <http://www.gnu.org/licenses/>. 15478fcb2cSWill Deacon */ 16478fcb2cSWill Deacon #ifndef __ASM_DEBUG_MONITORS_H 17478fcb2cSWill Deacon #define __ASM_DEBUG_MONITORS_H 18478fcb2cSWill Deacon 19478fcb2cSWill Deacon #ifdef __KERNEL__ 20478fcb2cSWill Deacon 2151ba2481SMarc Zyngier /* Low-level stepping controls. */ 2251ba2481SMarc Zyngier #define DBG_MDSCR_SS (1 << 0) 2351ba2481SMarc Zyngier #define DBG_SPSR_SS (1 << 21) 2451ba2481SMarc Zyngier 2551ba2481SMarc Zyngier /* MDSCR_EL1 enabling bits */ 2651ba2481SMarc Zyngier #define DBG_MDSCR_KDE (1 << 13) 2751ba2481SMarc Zyngier #define DBG_MDSCR_MDE (1 << 15) 2851ba2481SMarc Zyngier #define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE) 2951ba2481SMarc Zyngier 30478fcb2cSWill Deacon #define DBG_ESR_EVT(x) (((x) >> 27) & 0x7) 31478fcb2cSWill Deacon 32478fcb2cSWill Deacon /* AArch64 */ 33478fcb2cSWill Deacon #define DBG_ESR_EVT_HWBP 0x0 34478fcb2cSWill Deacon #define DBG_ESR_EVT_HWSS 0x1 35478fcb2cSWill Deacon #define DBG_ESR_EVT_HWWP 0x2 36478fcb2cSWill Deacon #define DBG_ESR_EVT_BRK 0x6 37478fcb2cSWill Deacon 38bcf5763bSVijaya Kumar K /* 39bcf5763bSVijaya Kumar K * Break point instruction encoding 40bcf5763bSVijaya Kumar K */ 41bcf5763bSVijaya Kumar K #define BREAK_INSTR_SIZE 4 42bcf5763bSVijaya Kumar K 43bcf5763bSVijaya Kumar K /* 44bcf5763bSVijaya Kumar K * ESR values expected for dynamic and compile time BRK instruction 45bcf5763bSVijaya Kumar K */ 46bcf5763bSVijaya Kumar K #define DBG_ESR_VAL_BRK(x) (0xf2000000 | ((x) & 0xfffff)) 47bcf5763bSVijaya Kumar K 48bcf5763bSVijaya Kumar K /* 49bcf5763bSVijaya Kumar K * #imm16 values used for BRK instruction generation 50bcf5763bSVijaya Kumar K * Allowed values for kgbd are 0x400 - 0x7ff 51a9ae04c9SMark Brown * 0x100: for triggering a fault on purpose (reserved) 52bcf5763bSVijaya Kumar K * 0x400: for dynamic BRK instruction 53bcf5763bSVijaya Kumar K * 0x401: for compile time BRK instruction 54bcf5763bSVijaya Kumar K */ 55a9ae04c9SMark Brown #define FAULT_BRK_IMM 0x100 56*7acf71d1SCatalin Marinas #define KGDB_DYN_DBG_BRK_IMM 0x400 57*7acf71d1SCatalin Marinas #define KGDB_COMPILED_DBG_BRK_IMM 0x401 58bcf5763bSVijaya Kumar K 59bcf5763bSVijaya Kumar K /* 60bcf5763bSVijaya Kumar K * BRK instruction encoding 61bcf5763bSVijaya Kumar K * The #imm16 value should be placed at bits[20:5] within BRK ins 62bcf5763bSVijaya Kumar K */ 63bcf5763bSVijaya Kumar K #define AARCH64_BREAK_MON 0xd4200000 64bcf5763bSVijaya Kumar K 65bcf5763bSVijaya Kumar K /* 66a9ae04c9SMark Brown * BRK instruction for provoking a fault on purpose 67a9ae04c9SMark Brown * Unlike kgdb, #imm16 value with unallocated handler is used for faulting. 68a9ae04c9SMark Brown */ 69a9ae04c9SMark Brown #define AARCH64_BREAK_FAULT (AARCH64_BREAK_MON | (FAULT_BRK_IMM << 5)) 70a9ae04c9SMark Brown 71a9ae04c9SMark Brown /* 72bcf5763bSVijaya Kumar K * Extract byte from BRK instruction 73bcf5763bSVijaya Kumar K */ 74*7acf71d1SCatalin Marinas #define KGDB_DYN_DBG_BRK_INS_BYTE(x) \ 75bcf5763bSVijaya Kumar K ((((AARCH64_BREAK_MON) & 0xffe0001f) >> (x * 8)) & 0xff) 76bcf5763bSVijaya Kumar K 77bcf5763bSVijaya Kumar K /* 78bcf5763bSVijaya Kumar K * Extract byte from BRK #imm16 79bcf5763bSVijaya Kumar K */ 80*7acf71d1SCatalin Marinas #define KGBD_DYN_DBG_BRK_IMM_BYTE(x) \ 81*7acf71d1SCatalin Marinas (((((KGDB_DYN_DBG_BRK_IMM) & 0xffff) << 5) >> (x * 8)) & 0xff) 82bcf5763bSVijaya Kumar K 83*7acf71d1SCatalin Marinas #define KGDB_DYN_DBG_BRK_BYTE(x) \ 84*7acf71d1SCatalin Marinas (KGDB_DYN_DBG_BRK_INS_BYTE(x) | KGBD_DYN_DBG_BRK_IMM_BYTE(x)) 85bcf5763bSVijaya Kumar K 86*7acf71d1SCatalin Marinas #define KGDB_DYN_BRK_INS_BYTE0 KGDB_DYN_DBG_BRK_BYTE(0) 87*7acf71d1SCatalin Marinas #define KGDB_DYN_BRK_INS_BYTE1 KGDB_DYN_DBG_BRK_BYTE(1) 88*7acf71d1SCatalin Marinas #define KGDB_DYN_BRK_INS_BYTE2 KGDB_DYN_DBG_BRK_BYTE(2) 89*7acf71d1SCatalin Marinas #define KGDB_DYN_BRK_INS_BYTE3 KGDB_DYN_DBG_BRK_BYTE(3) 90bcf5763bSVijaya Kumar K 91bcf5763bSVijaya Kumar K #define CACHE_FLUSH_IS_SAFE 1 92bcf5763bSVijaya Kumar K 93478fcb2cSWill Deacon /* AArch32 */ 94478fcb2cSWill Deacon #define DBG_ESR_EVT_BKPT 0x4 95478fcb2cSWill Deacon #define DBG_ESR_EVT_VECC 0x5 96478fcb2cSWill Deacon 97478fcb2cSWill Deacon #define AARCH32_BREAK_ARM 0x07f001f0 98478fcb2cSWill Deacon #define AARCH32_BREAK_THUMB 0xde01 99478fcb2cSWill Deacon #define AARCH32_BREAK_THUMB2_LO 0xf7f0 100478fcb2cSWill Deacon #define AARCH32_BREAK_THUMB2_HI 0xa000 101478fcb2cSWill Deacon 102478fcb2cSWill Deacon #ifndef __ASSEMBLY__ 103478fcb2cSWill Deacon struct task_struct; 104478fcb2cSWill Deacon 105478fcb2cSWill Deacon #define DBG_ARCH_ID_RESERVED 0 /* In case of ptrace ABI updates. */ 106478fcb2cSWill Deacon 107ee6214ceSSandeepa Prabhu #define DBG_HOOK_HANDLED 0 108ee6214ceSSandeepa Prabhu #define DBG_HOOK_ERROR 1 109ee6214ceSSandeepa Prabhu 110ee6214ceSSandeepa Prabhu struct step_hook { 111ee6214ceSSandeepa Prabhu struct list_head node; 112ee6214ceSSandeepa Prabhu int (*fn)(struct pt_regs *regs, unsigned int esr); 113ee6214ceSSandeepa Prabhu }; 114ee6214ceSSandeepa Prabhu 115ee6214ceSSandeepa Prabhu void register_step_hook(struct step_hook *hook); 116ee6214ceSSandeepa Prabhu void unregister_step_hook(struct step_hook *hook); 117ee6214ceSSandeepa Prabhu 118ee6214ceSSandeepa Prabhu struct break_hook { 119ee6214ceSSandeepa Prabhu struct list_head node; 120ee6214ceSSandeepa Prabhu u32 esr_val; 121ee6214ceSSandeepa Prabhu u32 esr_mask; 122ee6214ceSSandeepa Prabhu int (*fn)(struct pt_regs *regs, unsigned int esr); 123ee6214ceSSandeepa Prabhu }; 124ee6214ceSSandeepa Prabhu 125ee6214ceSSandeepa Prabhu void register_break_hook(struct break_hook *hook); 126ee6214ceSSandeepa Prabhu void unregister_break_hook(struct break_hook *hook); 127ee6214ceSSandeepa Prabhu 128478fcb2cSWill Deacon u8 debug_monitors_arch(void); 129478fcb2cSWill Deacon 13051ba2481SMarc Zyngier enum debug_el { 13151ba2481SMarc Zyngier DBG_ACTIVE_EL0 = 0, 13251ba2481SMarc Zyngier DBG_ACTIVE_EL1, 13351ba2481SMarc Zyngier }; 13451ba2481SMarc Zyngier 135478fcb2cSWill Deacon void enable_debug_monitors(enum debug_el el); 136478fcb2cSWill Deacon void disable_debug_monitors(enum debug_el el); 137478fcb2cSWill Deacon 138478fcb2cSWill Deacon void user_rewind_single_step(struct task_struct *task); 139478fcb2cSWill Deacon void user_fastforward_single_step(struct task_struct *task); 140478fcb2cSWill Deacon 141478fcb2cSWill Deacon void kernel_enable_single_step(struct pt_regs *regs); 142478fcb2cSWill Deacon void kernel_disable_single_step(void); 143478fcb2cSWill Deacon int kernel_active_single_step(void); 144478fcb2cSWill Deacon 145478fcb2cSWill Deacon #ifdef CONFIG_HAVE_HW_BREAKPOINT 146478fcb2cSWill Deacon int reinstall_suspended_bps(struct pt_regs *regs); 147478fcb2cSWill Deacon #else 148478fcb2cSWill Deacon static inline int reinstall_suspended_bps(struct pt_regs *regs) 149478fcb2cSWill Deacon { 150478fcb2cSWill Deacon return -ENODEV; 151478fcb2cSWill Deacon } 152478fcb2cSWill Deacon #endif 153478fcb2cSWill Deacon 1541442b6edSWill Deacon int aarch32_break_handler(struct pt_regs *regs); 1551442b6edSWill Deacon 156478fcb2cSWill Deacon #endif /* __ASSEMBLY */ 157478fcb2cSWill Deacon #endif /* __KERNEL__ */ 158478fcb2cSWill Deacon #endif /* __ASM_DEBUG_MONITORS_H */ 159