1478fcb2cSWill Deacon /* 2478fcb2cSWill Deacon * Copyright (C) 2012 ARM Ltd. 3478fcb2cSWill Deacon * 4478fcb2cSWill Deacon * This program is free software; you can redistribute it and/or modify 5478fcb2cSWill Deacon * it under the terms of the GNU General Public License version 2 as 6478fcb2cSWill Deacon * published by the Free Software Foundation. 7478fcb2cSWill Deacon * 8478fcb2cSWill Deacon * This program is distributed in the hope that it will be useful, 9478fcb2cSWill Deacon * but WITHOUT ANY WARRANTY; without even the implied warranty of 10478fcb2cSWill Deacon * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11478fcb2cSWill Deacon * GNU General Public License for more details. 12478fcb2cSWill Deacon * 13478fcb2cSWill Deacon * You should have received a copy of the GNU General Public License 14478fcb2cSWill Deacon * along with this program. If not, see <http://www.gnu.org/licenses/>. 15478fcb2cSWill Deacon */ 16478fcb2cSWill Deacon #ifndef __ASM_DEBUG_MONITORS_H 17478fcb2cSWill Deacon #define __ASM_DEBUG_MONITORS_H 18478fcb2cSWill Deacon 19478fcb2cSWill Deacon #ifdef __KERNEL__ 20478fcb2cSWill Deacon 21*03923696SDave P Martin #include <asm/esr.h> 22951757aeSDave P Martin #include <asm/insn.h> 23951757aeSDave P Martin 2451ba2481SMarc Zyngier /* Low-level stepping controls. */ 2551ba2481SMarc Zyngier #define DBG_MDSCR_SS (1 << 0) 2651ba2481SMarc Zyngier #define DBG_SPSR_SS (1 << 21) 2751ba2481SMarc Zyngier 2851ba2481SMarc Zyngier /* MDSCR_EL1 enabling bits */ 2951ba2481SMarc Zyngier #define DBG_MDSCR_KDE (1 << 13) 3051ba2481SMarc Zyngier #define DBG_MDSCR_MDE (1 << 15) 3151ba2481SMarc Zyngier #define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE) 3251ba2481SMarc Zyngier 33478fcb2cSWill Deacon #define DBG_ESR_EVT(x) (((x) >> 27) & 0x7) 34478fcb2cSWill Deacon 35478fcb2cSWill Deacon /* AArch64 */ 36478fcb2cSWill Deacon #define DBG_ESR_EVT_HWBP 0x0 37478fcb2cSWill Deacon #define DBG_ESR_EVT_HWSS 0x1 38478fcb2cSWill Deacon #define DBG_ESR_EVT_HWWP 0x2 39478fcb2cSWill Deacon #define DBG_ESR_EVT_BRK 0x6 40478fcb2cSWill Deacon 41bcf5763bSVijaya Kumar K /* 42bcf5763bSVijaya Kumar K * Break point instruction encoding 43bcf5763bSVijaya Kumar K */ 44951757aeSDave P Martin #define BREAK_INSTR_SIZE AARCH64_INSN_SIZE 45bcf5763bSVijaya Kumar K 46bcf5763bSVijaya Kumar K /* 47bcf5763bSVijaya Kumar K * ESR values expected for dynamic and compile time BRK instruction 48bcf5763bSVijaya Kumar K */ 49*03923696SDave P Martin #define DBG_ESR_VAL_BRK(x) \ 50*03923696SDave P Martin ((ESR_ELx_EC_BRK64 << ESR_ELx_EC_SHIFT) | ESR_ELx_IL | ((x) & 0xffff)) 51bcf5763bSVijaya Kumar K 52bcf5763bSVijaya Kumar K /* 53bcf5763bSVijaya Kumar K * #imm16 values used for BRK instruction generation 54bcf5763bSVijaya Kumar K * Allowed values for kgbd are 0x400 - 0x7ff 55a9ae04c9SMark Brown * 0x100: for triggering a fault on purpose (reserved) 56bcf5763bSVijaya Kumar K * 0x400: for dynamic BRK instruction 57bcf5763bSVijaya Kumar K * 0x401: for compile time BRK instruction 58bcf5763bSVijaya Kumar K */ 59a9ae04c9SMark Brown #define FAULT_BRK_IMM 0x100 607acf71d1SCatalin Marinas #define KGDB_DYN_DBG_BRK_IMM 0x400 617acf71d1SCatalin Marinas #define KGDB_COMPILED_DBG_BRK_IMM 0x401 62bcf5763bSVijaya Kumar K 63bcf5763bSVijaya Kumar K /* 64bcf5763bSVijaya Kumar K * BRK instruction encoding 65bcf5763bSVijaya Kumar K * The #imm16 value should be placed at bits[20:5] within BRK ins 66bcf5763bSVijaya Kumar K */ 67bcf5763bSVijaya Kumar K #define AARCH64_BREAK_MON 0xd4200000 68bcf5763bSVijaya Kumar K 69bcf5763bSVijaya Kumar K /* 70a9ae04c9SMark Brown * BRK instruction for provoking a fault on purpose 71a9ae04c9SMark Brown * Unlike kgdb, #imm16 value with unallocated handler is used for faulting. 72a9ae04c9SMark Brown */ 73a9ae04c9SMark Brown #define AARCH64_BREAK_FAULT (AARCH64_BREAK_MON | (FAULT_BRK_IMM << 5)) 74a9ae04c9SMark Brown 75a9ae04c9SMark Brown /* 76bcf5763bSVijaya Kumar K * Extract byte from BRK instruction 77bcf5763bSVijaya Kumar K */ 787acf71d1SCatalin Marinas #define KGDB_DYN_DBG_BRK_INS_BYTE(x) \ 79bcf5763bSVijaya Kumar K ((((AARCH64_BREAK_MON) & 0xffe0001f) >> (x * 8)) & 0xff) 80bcf5763bSVijaya Kumar K 81bcf5763bSVijaya Kumar K /* 82bcf5763bSVijaya Kumar K * Extract byte from BRK #imm16 83bcf5763bSVijaya Kumar K */ 847acf71d1SCatalin Marinas #define KGBD_DYN_DBG_BRK_IMM_BYTE(x) \ 857acf71d1SCatalin Marinas (((((KGDB_DYN_DBG_BRK_IMM) & 0xffff) << 5) >> (x * 8)) & 0xff) 86bcf5763bSVijaya Kumar K 877acf71d1SCatalin Marinas #define KGDB_DYN_DBG_BRK_BYTE(x) \ 887acf71d1SCatalin Marinas (KGDB_DYN_DBG_BRK_INS_BYTE(x) | KGBD_DYN_DBG_BRK_IMM_BYTE(x)) 89bcf5763bSVijaya Kumar K 907acf71d1SCatalin Marinas #define KGDB_DYN_BRK_INS_BYTE0 KGDB_DYN_DBG_BRK_BYTE(0) 917acf71d1SCatalin Marinas #define KGDB_DYN_BRK_INS_BYTE1 KGDB_DYN_DBG_BRK_BYTE(1) 927acf71d1SCatalin Marinas #define KGDB_DYN_BRK_INS_BYTE2 KGDB_DYN_DBG_BRK_BYTE(2) 937acf71d1SCatalin Marinas #define KGDB_DYN_BRK_INS_BYTE3 KGDB_DYN_DBG_BRK_BYTE(3) 94bcf5763bSVijaya Kumar K 95bcf5763bSVijaya Kumar K #define CACHE_FLUSH_IS_SAFE 1 96bcf5763bSVijaya Kumar K 97478fcb2cSWill Deacon /* AArch32 */ 98478fcb2cSWill Deacon #define DBG_ESR_EVT_BKPT 0x4 99478fcb2cSWill Deacon #define DBG_ESR_EVT_VECC 0x5 100478fcb2cSWill Deacon 101478fcb2cSWill Deacon #define AARCH32_BREAK_ARM 0x07f001f0 102478fcb2cSWill Deacon #define AARCH32_BREAK_THUMB 0xde01 103478fcb2cSWill Deacon #define AARCH32_BREAK_THUMB2_LO 0xf7f0 104478fcb2cSWill Deacon #define AARCH32_BREAK_THUMB2_HI 0xa000 105478fcb2cSWill Deacon 106478fcb2cSWill Deacon #ifndef __ASSEMBLY__ 107478fcb2cSWill Deacon struct task_struct; 108478fcb2cSWill Deacon 109478fcb2cSWill Deacon #define DBG_ARCH_ID_RESERVED 0 /* In case of ptrace ABI updates. */ 110478fcb2cSWill Deacon 111ee6214ceSSandeepa Prabhu #define DBG_HOOK_HANDLED 0 112ee6214ceSSandeepa Prabhu #define DBG_HOOK_ERROR 1 113ee6214ceSSandeepa Prabhu 114ee6214ceSSandeepa Prabhu struct step_hook { 115ee6214ceSSandeepa Prabhu struct list_head node; 116ee6214ceSSandeepa Prabhu int (*fn)(struct pt_regs *regs, unsigned int esr); 117ee6214ceSSandeepa Prabhu }; 118ee6214ceSSandeepa Prabhu 119ee6214ceSSandeepa Prabhu void register_step_hook(struct step_hook *hook); 120ee6214ceSSandeepa Prabhu void unregister_step_hook(struct step_hook *hook); 121ee6214ceSSandeepa Prabhu 122ee6214ceSSandeepa Prabhu struct break_hook { 123ee6214ceSSandeepa Prabhu struct list_head node; 124ee6214ceSSandeepa Prabhu u32 esr_val; 125ee6214ceSSandeepa Prabhu u32 esr_mask; 126ee6214ceSSandeepa Prabhu int (*fn)(struct pt_regs *regs, unsigned int esr); 127ee6214ceSSandeepa Prabhu }; 128ee6214ceSSandeepa Prabhu 129ee6214ceSSandeepa Prabhu void register_break_hook(struct break_hook *hook); 130ee6214ceSSandeepa Prabhu void unregister_break_hook(struct break_hook *hook); 131ee6214ceSSandeepa Prabhu 132478fcb2cSWill Deacon u8 debug_monitors_arch(void); 133478fcb2cSWill Deacon 13451ba2481SMarc Zyngier enum debug_el { 13551ba2481SMarc Zyngier DBG_ACTIVE_EL0 = 0, 13651ba2481SMarc Zyngier DBG_ACTIVE_EL1, 13751ba2481SMarc Zyngier }; 13851ba2481SMarc Zyngier 139478fcb2cSWill Deacon void enable_debug_monitors(enum debug_el el); 140478fcb2cSWill Deacon void disable_debug_monitors(enum debug_el el); 141478fcb2cSWill Deacon 142478fcb2cSWill Deacon void user_rewind_single_step(struct task_struct *task); 143478fcb2cSWill Deacon void user_fastforward_single_step(struct task_struct *task); 144478fcb2cSWill Deacon 145478fcb2cSWill Deacon void kernel_enable_single_step(struct pt_regs *regs); 146478fcb2cSWill Deacon void kernel_disable_single_step(void); 147478fcb2cSWill Deacon int kernel_active_single_step(void); 148478fcb2cSWill Deacon 149478fcb2cSWill Deacon #ifdef CONFIG_HAVE_HW_BREAKPOINT 150478fcb2cSWill Deacon int reinstall_suspended_bps(struct pt_regs *regs); 151478fcb2cSWill Deacon #else 152478fcb2cSWill Deacon static inline int reinstall_suspended_bps(struct pt_regs *regs) 153478fcb2cSWill Deacon { 154478fcb2cSWill Deacon return -ENODEV; 155478fcb2cSWill Deacon } 156478fcb2cSWill Deacon #endif 157478fcb2cSWill Deacon 1581442b6edSWill Deacon int aarch32_break_handler(struct pt_regs *regs); 1591442b6edSWill Deacon 160478fcb2cSWill Deacon #endif /* __ASSEMBLY */ 161478fcb2cSWill Deacon #endif /* __KERNEL__ */ 162478fcb2cSWill Deacon #endif /* __ASM_DEBUG_MONITORS_H */ 163