1*ef797b53SMichal Simek// SPDX-License-Identifier: GPL-2.0+ 2*ef797b53SMichal Simek/* 3*ef797b53SMichal Simek * dts file for Xilinx ZynqMP ZCU102 Rev1.0 4*ef797b53SMichal Simek * 5*ef797b53SMichal Simek * (C) Copyright 2016 - 2018, Xilinx, Inc. 6*ef797b53SMichal Simek * 7*ef797b53SMichal Simek * Michal Simek <michal.simek@xilinx.com> 8*ef797b53SMichal Simek */ 9*ef797b53SMichal Simek 10*ef797b53SMichal Simek#include "zynqmp-zcu102-revB.dts" 11*ef797b53SMichal Simek 12*ef797b53SMichal Simek/ { 13*ef797b53SMichal Simek model = "ZynqMP ZCU102 Rev1.0"; 14*ef797b53SMichal Simek compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 15*ef797b53SMichal Simek}; 16*ef797b53SMichal Simek 17*ef797b53SMichal Simek&eeprom { 18*ef797b53SMichal Simek #address-cells = <1>; 19*ef797b53SMichal Simek #size-cells = <1>; 20*ef797b53SMichal Simek 21*ef797b53SMichal Simek board_sn: board-sn@0 { 22*ef797b53SMichal Simek reg = <0x0 0x14>; 23*ef797b53SMichal Simek }; 24*ef797b53SMichal Simek 25*ef797b53SMichal Simek eth_mac: eth-mac@20 { 26*ef797b53SMichal Simek reg = <0x20 0x6>; 27*ef797b53SMichal Simek }; 28*ef797b53SMichal Simek 29*ef797b53SMichal Simek board_name: board-name@d0 { 30*ef797b53SMichal Simek reg = <0xd0 0x6>; 31*ef797b53SMichal Simek }; 32*ef797b53SMichal Simek 33*ef797b53SMichal Simek board_revision: board-revision@e0 { 34*ef797b53SMichal Simek reg = <0xe0 0x3>; 35*ef797b53SMichal Simek }; 36*ef797b53SMichal Simek}; 37