1ef797b53SMichal Simek// SPDX-License-Identifier: GPL-2.0+ 2ef797b53SMichal Simek/* 3ef797b53SMichal Simek * dts file for Xilinx ZynqMP ZCU102 Rev1.0 4ef797b53SMichal Simek * 5ef797b53SMichal Simek * (C) Copyright 2016 - 2018, Xilinx, Inc. 6ef797b53SMichal Simek * 7*4e4ddd3dSMichal Simek * Michal Simek <michal.simek@amd.com> 8ef797b53SMichal Simek */ 9ef797b53SMichal Simek 10ef797b53SMichal Simek#include "zynqmp-zcu102-revB.dts" 11ef797b53SMichal Simek 12ef797b53SMichal Simek/ { 13ef797b53SMichal Simek model = "ZynqMP ZCU102 Rev1.0"; 14ef797b53SMichal Simek compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 15ef797b53SMichal Simek}; 16ef797b53SMichal Simek 17ef797b53SMichal Simek&eeprom { 18ef797b53SMichal Simek #address-cells = <1>; 19ef797b53SMichal Simek #size-cells = <1>; 20ef797b53SMichal Simek 21ef797b53SMichal Simek board_sn: board-sn@0 { 22ef797b53SMichal Simek reg = <0x0 0x14>; 23ef797b53SMichal Simek }; 24ef797b53SMichal Simek 25ef797b53SMichal Simek eth_mac: eth-mac@20 { 26ef797b53SMichal Simek reg = <0x20 0x6>; 27ef797b53SMichal Simek }; 28ef797b53SMichal Simek 29ef797b53SMichal Simek board_name: board-name@d0 { 30ef797b53SMichal Simek reg = <0xd0 0x6>; 31ef797b53SMichal Simek }; 32ef797b53SMichal Simek 33ef797b53SMichal Simek board_revision: board-revision@e0 { 34ef797b53SMichal Simek reg = <0xe0 0x3>; 35ef797b53SMichal Simek }; 36ef797b53SMichal Simek}; 37