1*8abae938SDave Gerlach// SPDX-License-Identifier: GPL-2.0 2*8abae938SDave Gerlach/* 3*8abae938SDave Gerlach * Device Tree Source for AM642 SoC family in Dual core configuration 4*8abae938SDave Gerlach * 5*8abae938SDave Gerlach * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6*8abae938SDave Gerlach */ 7*8abae938SDave Gerlach 8*8abae938SDave Gerlach/dts-v1/; 9*8abae938SDave Gerlach 10*8abae938SDave Gerlach#include "k3-am64.dtsi" 11*8abae938SDave Gerlach 12*8abae938SDave Gerlach/ { 13*8abae938SDave Gerlach cpus { 14*8abae938SDave Gerlach #address-cells = <1>; 15*8abae938SDave Gerlach #size-cells = <0>; 16*8abae938SDave Gerlach 17*8abae938SDave Gerlach cpu-map { 18*8abae938SDave Gerlach cluster0: cluster0 { 19*8abae938SDave Gerlach core0 { 20*8abae938SDave Gerlach cpu = <&cpu0>; 21*8abae938SDave Gerlach }; 22*8abae938SDave Gerlach 23*8abae938SDave Gerlach core1 { 24*8abae938SDave Gerlach cpu = <&cpu1>; 25*8abae938SDave Gerlach }; 26*8abae938SDave Gerlach }; 27*8abae938SDave Gerlach }; 28*8abae938SDave Gerlach 29*8abae938SDave Gerlach cpu0: cpu@0 { 30*8abae938SDave Gerlach compatible = "arm,cortex-a53"; 31*8abae938SDave Gerlach reg = <0x000>; 32*8abae938SDave Gerlach device_type = "cpu"; 33*8abae938SDave Gerlach enable-method = "psci"; 34*8abae938SDave Gerlach i-cache-size = <0x8000>; 35*8abae938SDave Gerlach i-cache-line-size = <64>; 36*8abae938SDave Gerlach i-cache-sets = <256>; 37*8abae938SDave Gerlach d-cache-size = <0x8000>; 38*8abae938SDave Gerlach d-cache-line-size = <64>; 39*8abae938SDave Gerlach d-cache-sets = <128>; 40*8abae938SDave Gerlach next-level-cache = <&L2_0>; 41*8abae938SDave Gerlach }; 42*8abae938SDave Gerlach 43*8abae938SDave Gerlach cpu1: cpu@1 { 44*8abae938SDave Gerlach compatible = "arm,cortex-a53"; 45*8abae938SDave Gerlach reg = <0x001>; 46*8abae938SDave Gerlach device_type = "cpu"; 47*8abae938SDave Gerlach enable-method = "psci"; 48*8abae938SDave Gerlach i-cache-size = <0x8000>; 49*8abae938SDave Gerlach i-cache-line-size = <64>; 50*8abae938SDave Gerlach i-cache-sets = <256>; 51*8abae938SDave Gerlach d-cache-size = <0x8000>; 52*8abae938SDave Gerlach d-cache-line-size = <64>; 53*8abae938SDave Gerlach d-cache-sets = <128>; 54*8abae938SDave Gerlach next-level-cache = <&L2_0>; 55*8abae938SDave Gerlach }; 56*8abae938SDave Gerlach }; 57*8abae938SDave Gerlach 58*8abae938SDave Gerlach L2_0: l2-cache0 { 59*8abae938SDave Gerlach compatible = "cache"; 60*8abae938SDave Gerlach cache-level = <2>; 61*8abae938SDave Gerlach cache-size = <0x40000>; 62*8abae938SDave Gerlach cache-line-size = <64>; 63*8abae938SDave Gerlach cache-sets = <512>; 64*8abae938SDave Gerlach }; 65*8abae938SDave Gerlach}; 66