11e6550d3SDave Gerlach// SPDX-License-Identifier: GPL-2.0 21e6550d3SDave Gerlach/* 31e6550d3SDave Gerlach * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 41e6550d3SDave Gerlach */ 51e6550d3SDave Gerlach 61e6550d3SDave Gerlach/dts-v1/; 71e6550d3SDave Gerlach 81e6550d3SDave Gerlach#include <dt-bindings/leds/common.h> 9985204ecSVignesh Raghavendra#include <dt-bindings/gpio/gpio.h> 10985204ecSVignesh Raghavendra#include <dt-bindings/net/ti-dp83867.h> 111e6550d3SDave Gerlach#include "k3-am642.dtsi" 121e6550d3SDave Gerlach 131e6550d3SDave Gerlach/ { 141e6550d3SDave Gerlach compatible = "ti,am642-evm", "ti,am642"; 151e6550d3SDave Gerlach model = "Texas Instruments AM642 EVM"; 161e6550d3SDave Gerlach 171e6550d3SDave Gerlach chosen { 181e6550d3SDave Gerlach stdout-path = "serial2:115200n8"; 191e6550d3SDave Gerlach bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 201e6550d3SDave Gerlach }; 211e6550d3SDave Gerlach 221e6550d3SDave Gerlach memory@80000000 { 231e6550d3SDave Gerlach device_type = "memory"; 241e6550d3SDave Gerlach /* 2G RAM */ 251e6550d3SDave Gerlach reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 261e6550d3SDave Gerlach 271e6550d3SDave Gerlach }; 281e6550d3SDave Gerlach 291e6550d3SDave Gerlach reserved-memory { 301e6550d3SDave Gerlach #address-cells = <2>; 311e6550d3SDave Gerlach #size-cells = <2>; 321e6550d3SDave Gerlach ranges; 331e6550d3SDave Gerlach 341e6550d3SDave Gerlach secure_ddr: optee@9e800000 { 351e6550d3SDave Gerlach reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 361e6550d3SDave Gerlach alignment = <0x1000>; 371e6550d3SDave Gerlach no-map; 381e6550d3SDave Gerlach }; 391e6550d3SDave Gerlach }; 401e6550d3SDave Gerlach 411e6550d3SDave Gerlach evm_12v0: fixedregulator-evm12v0 { 421e6550d3SDave Gerlach /* main DC jack */ 431e6550d3SDave Gerlach compatible = "regulator-fixed"; 441e6550d3SDave Gerlach regulator-name = "evm_12v0"; 451e6550d3SDave Gerlach regulator-min-microvolt = <12000000>; 461e6550d3SDave Gerlach regulator-max-microvolt = <12000000>; 471e6550d3SDave Gerlach regulator-always-on; 481e6550d3SDave Gerlach regulator-boot-on; 491e6550d3SDave Gerlach }; 501e6550d3SDave Gerlach 511e6550d3SDave Gerlach vsys_5v0: fixedregulator-vsys5v0 { 521e6550d3SDave Gerlach /* output of LM5140 */ 531e6550d3SDave Gerlach compatible = "regulator-fixed"; 541e6550d3SDave Gerlach regulator-name = "vsys_5v0"; 551e6550d3SDave Gerlach regulator-min-microvolt = <5000000>; 561e6550d3SDave Gerlach regulator-max-microvolt = <5000000>; 571e6550d3SDave Gerlach vin-supply = <&evm_12v0>; 581e6550d3SDave Gerlach regulator-always-on; 591e6550d3SDave Gerlach regulator-boot-on; 601e6550d3SDave Gerlach }; 611e6550d3SDave Gerlach 621e6550d3SDave Gerlach vsys_3v3: fixedregulator-vsys3v3 { 631e6550d3SDave Gerlach /* output of LM5140 */ 641e6550d3SDave Gerlach compatible = "regulator-fixed"; 651e6550d3SDave Gerlach regulator-name = "vsys_3v3"; 661e6550d3SDave Gerlach regulator-min-microvolt = <3300000>; 671e6550d3SDave Gerlach regulator-max-microvolt = <3300000>; 681e6550d3SDave Gerlach vin-supply = <&evm_12v0>; 691e6550d3SDave Gerlach regulator-always-on; 701e6550d3SDave Gerlach regulator-boot-on; 711e6550d3SDave Gerlach }; 721e6550d3SDave Gerlach 731e6550d3SDave Gerlach vdd_mmc1: fixed-regulator-sd { 741e6550d3SDave Gerlach /* TPS2051BD */ 751e6550d3SDave Gerlach compatible = "regulator-fixed"; 761e6550d3SDave Gerlach regulator-name = "vdd_mmc1"; 771e6550d3SDave Gerlach regulator-min-microvolt = <3300000>; 781e6550d3SDave Gerlach regulator-max-microvolt = <3300000>; 791e6550d3SDave Gerlach regulator-boot-on; 801e6550d3SDave Gerlach enable-active-high; 811e6550d3SDave Gerlach vin-supply = <&vsys_3v3>; 821e6550d3SDave Gerlach gpio = <&exp1 6 GPIO_ACTIVE_HIGH>; 831e6550d3SDave Gerlach }; 841e6550d3SDave Gerlach 851e6550d3SDave Gerlach vddb: fixedregulator-vddb { 861e6550d3SDave Gerlach compatible = "regulator-fixed"; 871e6550d3SDave Gerlach regulator-name = "vddb_3v3_display"; 881e6550d3SDave Gerlach regulator-min-microvolt = <3300000>; 891e6550d3SDave Gerlach regulator-max-microvolt = <3300000>; 901e6550d3SDave Gerlach vin-supply = <&vsys_3v3>; 911e6550d3SDave Gerlach regulator-always-on; 921e6550d3SDave Gerlach regulator-boot-on; 931e6550d3SDave Gerlach }; 941e6550d3SDave Gerlach 951e6550d3SDave Gerlach leds { 961e6550d3SDave Gerlach compatible = "gpio-leds"; 971e6550d3SDave Gerlach 981e6550d3SDave Gerlach led-0 { 991e6550d3SDave Gerlach label = "am64-evm:red:heartbeat"; 1001e6550d3SDave Gerlach gpios = <&exp1 16 GPIO_ACTIVE_HIGH>; 1011e6550d3SDave Gerlach linux,default-trigger = "heartbeat"; 1021e6550d3SDave Gerlach function = LED_FUNCTION_HEARTBEAT; 1031e6550d3SDave Gerlach default-state = "off"; 1041e6550d3SDave Gerlach }; 1051e6550d3SDave Gerlach }; 106985204ecSVignesh Raghavendra 107985204ecSVignesh Raghavendra mdio_mux: mux-controller { 108985204ecSVignesh Raghavendra compatible = "gpio-mux"; 109985204ecSVignesh Raghavendra #mux-control-cells = <0>; 110985204ecSVignesh Raghavendra 111985204ecSVignesh Raghavendra mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>; 112985204ecSVignesh Raghavendra }; 113985204ecSVignesh Raghavendra 114985204ecSVignesh Raghavendra mdio-mux-1 { 115985204ecSVignesh Raghavendra compatible = "mdio-mux-multiplexer"; 116985204ecSVignesh Raghavendra mux-controls = <&mdio_mux>; 117985204ecSVignesh Raghavendra mdio-parent-bus = <&cpsw3g_mdio>; 118985204ecSVignesh Raghavendra #address-cells = <1>; 119985204ecSVignesh Raghavendra #size-cells = <0>; 120985204ecSVignesh Raghavendra 121985204ecSVignesh Raghavendra mdio@1 { 122985204ecSVignesh Raghavendra reg = <0x1>; 123985204ecSVignesh Raghavendra #address-cells = <1>; 124985204ecSVignesh Raghavendra #size-cells = <0>; 125985204ecSVignesh Raghavendra 126985204ecSVignesh Raghavendra cpsw3g_phy3: ethernet-phy@3 { 127985204ecSVignesh Raghavendra reg = <3>; 128985204ecSVignesh Raghavendra }; 129985204ecSVignesh Raghavendra }; 130985204ecSVignesh Raghavendra }; 1311e6550d3SDave Gerlach}; 1321e6550d3SDave Gerlach 1331e6550d3SDave Gerlach&main_pmx0 { 1341e6550d3SDave Gerlach main_mmc1_pins_default: main-mmc1-pins-default { 1351e6550d3SDave Gerlach pinctrl-single,pins = < 1361e6550d3SDave Gerlach AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ 1371e6550d3SDave Gerlach AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ 1381e6550d3SDave Gerlach AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ 1391e6550d3SDave Gerlach AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ 1401e6550d3SDave Gerlach AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ 1411e6550d3SDave Gerlach AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ 1421e6550d3SDave Gerlach AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ 1431e6550d3SDave Gerlach AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */ 1441e6550d3SDave Gerlach AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */ 1451e6550d3SDave Gerlach >; 1461e6550d3SDave Gerlach }; 1471e6550d3SDave Gerlach 1481e6550d3SDave Gerlach main_uart0_pins_default: main-uart0-pins-default { 1491e6550d3SDave Gerlach pinctrl-single,pins = < 1501e6550d3SDave Gerlach AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ 1511e6550d3SDave Gerlach AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ 1521e6550d3SDave Gerlach AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ 1531e6550d3SDave Gerlach AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ 1541e6550d3SDave Gerlach >; 1551e6550d3SDave Gerlach }; 1561e6550d3SDave Gerlach 1574fb6c046SAswath Govindraju main_spi0_pins_default: main-spi0-pins-default { 1584fb6c046SAswath Govindraju pinctrl-single,pins = < 1594fb6c046SAswath Govindraju AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ 1604fb6c046SAswath Govindraju AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */ 1614fb6c046SAswath Govindraju AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */ 1624fb6c046SAswath Govindraju AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ 1634fb6c046SAswath Govindraju >; 1644fb6c046SAswath Govindraju }; 1654fb6c046SAswath Govindraju 1661e6550d3SDave Gerlach main_i2c1_pins_default: main-i2c1-pins-default { 1671e6550d3SDave Gerlach pinctrl-single,pins = < 1681e6550d3SDave Gerlach AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ 1691e6550d3SDave Gerlach AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ 1701e6550d3SDave Gerlach >; 1711e6550d3SDave Gerlach }; 172985204ecSVignesh Raghavendra 173985204ecSVignesh Raghavendra mdio1_pins_default: mdio1-pins-default { 174985204ecSVignesh Raghavendra pinctrl-single,pins = < 175985204ecSVignesh Raghavendra AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ 176985204ecSVignesh Raghavendra AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ 177985204ecSVignesh Raghavendra >; 178985204ecSVignesh Raghavendra }; 179985204ecSVignesh Raghavendra 180985204ecSVignesh Raghavendra rgmii1_pins_default: rgmii1-pins-default { 181985204ecSVignesh Raghavendra pinctrl-single,pins = < 182985204ecSVignesh Raghavendra AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ 183985204ecSVignesh Raghavendra AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ 184985204ecSVignesh Raghavendra AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ 185985204ecSVignesh Raghavendra AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ 186985204ecSVignesh Raghavendra AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ 187985204ecSVignesh Raghavendra AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ 188985204ecSVignesh Raghavendra AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ 189985204ecSVignesh Raghavendra AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ 190985204ecSVignesh Raghavendra AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ 191985204ecSVignesh Raghavendra AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ 192985204ecSVignesh Raghavendra AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ 193985204ecSVignesh Raghavendra AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 194985204ecSVignesh Raghavendra >; 195985204ecSVignesh Raghavendra }; 196985204ecSVignesh Raghavendra 197985204ecSVignesh Raghavendra rgmii2_pins_default: rgmii2-pins-default { 198985204ecSVignesh Raghavendra pinctrl-single,pins = < 199985204ecSVignesh Raghavendra AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ 200985204ecSVignesh Raghavendra AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ 201985204ecSVignesh Raghavendra AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ 202985204ecSVignesh Raghavendra AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ 203985204ecSVignesh Raghavendra AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ 204985204ecSVignesh Raghavendra AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 205985204ecSVignesh Raghavendra AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ 206985204ecSVignesh Raghavendra AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ 207985204ecSVignesh Raghavendra AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ 208985204ecSVignesh Raghavendra AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ 209985204ecSVignesh Raghavendra AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ 210985204ecSVignesh Raghavendra AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 211985204ecSVignesh Raghavendra >; 212985204ecSVignesh Raghavendra }; 21304a80a75SAswath Govindraju 21404a80a75SAswath Govindraju main_usb0_pins_default: main-usb0-pins-default { 21504a80a75SAswath Govindraju pinctrl-single,pins = < 21604a80a75SAswath Govindraju AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ 21704a80a75SAswath Govindraju >; 21804a80a75SAswath Govindraju }; 219e4e4e894SVignesh Raghavendra 220e4e4e894SVignesh Raghavendra ospi0_pins_default: ospi0-pins-default { 221e4e4e894SVignesh Raghavendra pinctrl-single,pins = < 222e4e4e894SVignesh Raghavendra AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ 223e4e4e894SVignesh Raghavendra AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ 224e4e4e894SVignesh Raghavendra AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ 225e4e4e894SVignesh Raghavendra AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ 226e4e4e894SVignesh Raghavendra AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ 227e4e4e894SVignesh Raghavendra AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ 228e4e4e894SVignesh Raghavendra AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ 229e4e4e894SVignesh Raghavendra AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ 230e4e4e894SVignesh Raghavendra AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ 231e4e4e894SVignesh Raghavendra AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ 232e4e4e894SVignesh Raghavendra AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ 233e4e4e894SVignesh Raghavendra >; 234e4e4e894SVignesh Raghavendra }; 2351e6550d3SDave Gerlach}; 2361e6550d3SDave Gerlach 2371e6550d3SDave Gerlach&main_uart0 { 2381e6550d3SDave Gerlach pinctrl-names = "default"; 2391e6550d3SDave Gerlach pinctrl-0 = <&main_uart0_pins_default>; 2401e6550d3SDave Gerlach}; 2411e6550d3SDave Gerlach 2421e6550d3SDave Gerlach/* main_uart1 is reserved for firmware usage */ 2431e6550d3SDave Gerlach&main_uart1 { 2441e6550d3SDave Gerlach status = "reserved"; 2451e6550d3SDave Gerlach}; 2461e6550d3SDave Gerlach 2471e6550d3SDave Gerlach&main_uart2 { 2481e6550d3SDave Gerlach status = "disabled"; 2491e6550d3SDave Gerlach}; 2501e6550d3SDave Gerlach 2511e6550d3SDave Gerlach&main_uart3 { 2521e6550d3SDave Gerlach status = "disabled"; 2531e6550d3SDave Gerlach}; 2541e6550d3SDave Gerlach 2551e6550d3SDave Gerlach&main_uart4 { 2561e6550d3SDave Gerlach status = "disabled"; 2571e6550d3SDave Gerlach}; 2581e6550d3SDave Gerlach 2591e6550d3SDave Gerlach&main_uart5 { 2601e6550d3SDave Gerlach status = "disabled"; 2611e6550d3SDave Gerlach}; 2621e6550d3SDave Gerlach 2631e6550d3SDave Gerlach&main_uart6 { 2641e6550d3SDave Gerlach status = "disabled"; 2651e6550d3SDave Gerlach}; 2661e6550d3SDave Gerlach 2671e6550d3SDave Gerlach&mcu_uart0 { 2681e6550d3SDave Gerlach status = "disabled"; 2691e6550d3SDave Gerlach}; 2701e6550d3SDave Gerlach 2711e6550d3SDave Gerlach&mcu_uart1 { 2721e6550d3SDave Gerlach status = "disabled"; 2731e6550d3SDave Gerlach}; 2741e6550d3SDave Gerlach 2751e6550d3SDave Gerlach&main_i2c1 { 2761e6550d3SDave Gerlach pinctrl-names = "default"; 2771e6550d3SDave Gerlach pinctrl-0 = <&main_i2c1_pins_default>; 2781e6550d3SDave Gerlach clock-frequency = <400000>; 2791e6550d3SDave Gerlach 2801e6550d3SDave Gerlach exp1: gpio@22 { 2811e6550d3SDave Gerlach compatible = "ti,tca6424"; 2821e6550d3SDave Gerlach reg = <0x22>; 2831e6550d3SDave Gerlach gpio-controller; 2841e6550d3SDave Gerlach #gpio-cells = <2>; 2851e6550d3SDave Gerlach gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL", 2861e6550d3SDave Gerlach "GPIO_CPSW1_RST", "GPIO_RGMII1_RST", 2871e6550d3SDave Gerlach "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT", 2881e6550d3SDave Gerlach "MMC1_SD_EN", "FSI_FET_SEL", 2891e6550d3SDave Gerlach "MCAN0_STB_3V3", "MCAN1_STB_3V3", 2901e6550d3SDave Gerlach "CPSW_FET_SEL", "CPSW_FET2_SEL", 2911e6550d3SDave Gerlach "PRG1_RGMII2_FET_SEL", "TEST_GPIO2", 2921e6550d3SDave Gerlach "GPIO_OLED_RESETn", "VPP_LDO_EN", 2931e6550d3SDave Gerlach "TEST_LED1", "TP92", "TP90", "TP88", 2941e6550d3SDave Gerlach "TP87", "TP86", "TP89", "TP91"; 2951e6550d3SDave Gerlach }; 2961e6550d3SDave Gerlach 2971e6550d3SDave Gerlach /* osd9616p0899-10 */ 2981e6550d3SDave Gerlach display@3c { 2991e6550d3SDave Gerlach compatible = "solomon,ssd1306fb-i2c"; 3001e6550d3SDave Gerlach reg = <0x3c>; 3011e6550d3SDave Gerlach reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>; 3021e6550d3SDave Gerlach vbat-supply = <&vddb>; 3031e6550d3SDave Gerlach solomon,height = <16>; 3041e6550d3SDave Gerlach solomon,width = <96>; 3051e6550d3SDave Gerlach solomon,com-seq; 3061e6550d3SDave Gerlach solomon,com-invdir; 3071e6550d3SDave Gerlach solomon,page-offset = <0>; 3081e6550d3SDave Gerlach solomon,prechargep1 = <2>; 3091e6550d3SDave Gerlach solomon,prechargep2 = <13>; 3101e6550d3SDave Gerlach }; 3111e6550d3SDave Gerlach}; 3121e6550d3SDave Gerlach 313d5a4d541SAswath Govindraju/* mcu_gpio0 is reserved for mcu firmware usage */ 314d5a4d541SAswath Govindraju&mcu_gpio0 { 315d5a4d541SAswath Govindraju status = "reserved"; 316d5a4d541SAswath Govindraju}; 317d5a4d541SAswath Govindraju 3181e6550d3SDave Gerlach&mcu_i2c0 { 3191e6550d3SDave Gerlach status = "disabled"; 3201e6550d3SDave Gerlach}; 3211e6550d3SDave Gerlach 3221e6550d3SDave Gerlach&mcu_i2c1 { 3231e6550d3SDave Gerlach status = "disabled"; 3241e6550d3SDave Gerlach}; 3251e6550d3SDave Gerlach 3261e6550d3SDave Gerlach&mcu_spi0 { 3271e6550d3SDave Gerlach status = "disabled"; 3281e6550d3SDave Gerlach}; 3291e6550d3SDave Gerlach 3301e6550d3SDave Gerlach&mcu_spi1 { 3311e6550d3SDave Gerlach status = "disabled"; 3321e6550d3SDave Gerlach}; 3331e6550d3SDave Gerlach 3344fb6c046SAswath Govindraju&main_spi0 { 3354fb6c046SAswath Govindraju pinctrl-names = "default"; 3364fb6c046SAswath Govindraju pinctrl-0 = <&main_spi0_pins_default>; 3374fb6c046SAswath Govindraju ti,pindir-d0-out-d1-in = <1>; 3384fb6c046SAswath Govindraju eeprom@0 { 3394fb6c046SAswath Govindraju compatible = "microchip,93lc46b"; 3404fb6c046SAswath Govindraju reg = <0>; 3414fb6c046SAswath Govindraju spi-max-frequency = <1000000>; 3424fb6c046SAswath Govindraju spi-cs-high; 3434fb6c046SAswath Govindraju data-size = <16>; 3444fb6c046SAswath Govindraju }; 3454fb6c046SAswath Govindraju}; 3464fb6c046SAswath Govindraju 3471e6550d3SDave Gerlach&sdhci0 { 3481e6550d3SDave Gerlach /* emmc */ 3491e6550d3SDave Gerlach bus-width = <8>; 3501e6550d3SDave Gerlach non-removable; 3511e6550d3SDave Gerlach ti,driver-strength-ohm = <50>; 3521e6550d3SDave Gerlach disable-wp; 3531e6550d3SDave Gerlach}; 3541e6550d3SDave Gerlach 3551e6550d3SDave Gerlach&sdhci1 { 3561e6550d3SDave Gerlach /* SD/MMC */ 3571e6550d3SDave Gerlach vmmc-supply = <&vdd_mmc1>; 3581e6550d3SDave Gerlach pinctrl-names = "default"; 3591e6550d3SDave Gerlach bus-width = <4>; 3601e6550d3SDave Gerlach pinctrl-0 = <&main_mmc1_pins_default>; 3611e6550d3SDave Gerlach ti,driver-strength-ohm = <50>; 3621e6550d3SDave Gerlach disable-wp; 3631e6550d3SDave Gerlach}; 364985204ecSVignesh Raghavendra 36504a80a75SAswath Govindraju&usbss0 { 36604a80a75SAswath Govindraju ti,vbus-divider; 36704a80a75SAswath Govindraju ti,usb2-only; 36804a80a75SAswath Govindraju}; 36904a80a75SAswath Govindraju 37004a80a75SAswath Govindraju&usb0 { 37104a80a75SAswath Govindraju dr_mode = "otg"; 37204a80a75SAswath Govindraju maximum-speed = "high-speed"; 37304a80a75SAswath Govindraju pinctrl-names = "default"; 37404a80a75SAswath Govindraju pinctrl-0 = <&main_usb0_pins_default>; 37504a80a75SAswath Govindraju}; 37604a80a75SAswath Govindraju 377985204ecSVignesh Raghavendra&cpsw3g { 378985204ecSVignesh Raghavendra pinctrl-names = "default"; 379985204ecSVignesh Raghavendra pinctrl-0 = <&mdio1_pins_default 380985204ecSVignesh Raghavendra &rgmii1_pins_default 381985204ecSVignesh Raghavendra &rgmii2_pins_default>; 382985204ecSVignesh Raghavendra}; 383985204ecSVignesh Raghavendra 384985204ecSVignesh Raghavendra&cpsw_port1 { 385985204ecSVignesh Raghavendra phy-mode = "rgmii-rxid"; 386985204ecSVignesh Raghavendra phy-handle = <&cpsw3g_phy0>; 387985204ecSVignesh Raghavendra}; 388985204ecSVignesh Raghavendra 389985204ecSVignesh Raghavendra&cpsw_port2 { 390985204ecSVignesh Raghavendra phy-mode = "rgmii-rxid"; 391985204ecSVignesh Raghavendra phy-handle = <&cpsw3g_phy3>; 392985204ecSVignesh Raghavendra}; 393985204ecSVignesh Raghavendra 394985204ecSVignesh Raghavendra&cpsw3g_mdio { 395985204ecSVignesh Raghavendra cpsw3g_phy0: ethernet-phy@0 { 396985204ecSVignesh Raghavendra reg = <0>; 397985204ecSVignesh Raghavendra ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 398985204ecSVignesh Raghavendra ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 399985204ecSVignesh Raghavendra }; 400985204ecSVignesh Raghavendra}; 401fad4e18fSVignesh Raghavendra 402fad4e18fSVignesh Raghavendra&tscadc0 { 403fad4e18fSVignesh Raghavendra /* ADC is reserved for R5 usage */ 404fad4e18fSVignesh Raghavendra status = "reserved"; 405fad4e18fSVignesh Raghavendra}; 406e4e4e894SVignesh Raghavendra 407e4e4e894SVignesh Raghavendra&ospi0 { 408e4e4e894SVignesh Raghavendra pinctrl-names = "default"; 409e4e4e894SVignesh Raghavendra pinctrl-0 = <&ospi0_pins_default>; 410e4e4e894SVignesh Raghavendra 411e4e4e894SVignesh Raghavendra flash@0{ 412e4e4e894SVignesh Raghavendra compatible = "jedec,spi-nor"; 413e4e4e894SVignesh Raghavendra reg = <0x0>; 414e4e4e894SVignesh Raghavendra spi-tx-bus-width = <8>; 415e4e4e894SVignesh Raghavendra spi-rx-bus-width = <8>; 416e4e4e894SVignesh Raghavendra spi-max-frequency = <25000000>; 417e4e4e894SVignesh Raghavendra cdns,tshsl-ns = <60>; 418e4e4e894SVignesh Raghavendra cdns,tsd2d-ns = <60>; 419e4e4e894SVignesh Raghavendra cdns,tchsh-ns = <60>; 420e4e4e894SVignesh Raghavendra cdns,tslch-ns = <60>; 421e4e4e894SVignesh Raghavendra cdns,read-delay = <4>; 422e4e4e894SVignesh Raghavendra #address-cells = <1>; 423e4e4e894SVignesh Raghavendra #size-cells = <1>; 424e4e4e894SVignesh Raghavendra }; 425e4e4e894SVignesh Raghavendra}; 426*7dd84752SSuman Anna 427*7dd84752SSuman Anna&mailbox0_cluster2 { 428*7dd84752SSuman Anna mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 429*7dd84752SSuman Anna ti,mbox-rx = <0 0 2>; 430*7dd84752SSuman Anna ti,mbox-tx = <1 0 2>; 431*7dd84752SSuman Anna }; 432*7dd84752SSuman Anna 433*7dd84752SSuman Anna mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 434*7dd84752SSuman Anna ti,mbox-rx = <2 0 2>; 435*7dd84752SSuman Anna ti,mbox-tx = <3 0 2>; 436*7dd84752SSuman Anna }; 437*7dd84752SSuman Anna}; 438*7dd84752SSuman Anna 439*7dd84752SSuman Anna&mailbox0_cluster3 { 440*7dd84752SSuman Anna status = "disabled"; 441*7dd84752SSuman Anna}; 442*7dd84752SSuman Anna 443*7dd84752SSuman Anna&mailbox0_cluster4 { 444*7dd84752SSuman Anna mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 445*7dd84752SSuman Anna ti,mbox-rx = <0 0 2>; 446*7dd84752SSuman Anna ti,mbox-tx = <1 0 2>; 447*7dd84752SSuman Anna }; 448*7dd84752SSuman Anna 449*7dd84752SSuman Anna mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 450*7dd84752SSuman Anna ti,mbox-rx = <2 0 2>; 451*7dd84752SSuman Anna ti,mbox-tx = <3 0 2>; 452*7dd84752SSuman Anna }; 453*7dd84752SSuman Anna}; 454*7dd84752SSuman Anna 455*7dd84752SSuman Anna&mailbox0_cluster5 { 456*7dd84752SSuman Anna status = "disabled"; 457*7dd84752SSuman Anna}; 458*7dd84752SSuman Anna 459*7dd84752SSuman Anna&mailbox0_cluster6 { 460*7dd84752SSuman Anna mbox_m4_0: mbox-m4-0 { 461*7dd84752SSuman Anna ti,mbox-rx = <0 0 2>; 462*7dd84752SSuman Anna ti,mbox-tx = <1 0 2>; 463*7dd84752SSuman Anna }; 464*7dd84752SSuman Anna}; 465*7dd84752SSuman Anna 466*7dd84752SSuman Anna&mailbox0_cluster7 { 467*7dd84752SSuman Anna status = "disabled"; 468*7dd84752SSuman Anna}; 469